1/* $NetBSD: if_rtw_cardbus.c,v 1.45 2016/07/07 06:55:41 msaitoh Exp $ */
2
3/*-
4 * Copyright (c) 2004, 2005 David Young. All rights reserved.
5 *
6 * Adapted for the RTL8180 by David Young.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
28 * OF SUCH DAMAGE.
29 */
30/*-
31 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
32 * All rights reserved.
33 *
34 * This code is derived from software contributed to The NetBSD Foundation
35 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
36 * NASA Ames Research Center.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 * 1. Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * 2. Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in the
45 * documentation and/or other materials provided with the distribution.
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
48 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
57 * POSSIBILITY OF SUCH DAMAGE.
58 */
59
60/*
61 * Cardbus front-end for the Realtek RTL8180 802.11 MAC/BBP driver.
62 *
63 * TBD factor with atw, tlp Cardbus front-ends?
64 */
65
66#include <sys/cdefs.h>
67__KERNEL_RCSID(0, "$NetBSD: if_rtw_cardbus.c,v 1.45 2016/07/07 06:55:41 msaitoh Exp $");
68
69#include "opt_inet.h"
70
71#include <sys/param.h>
72#include <sys/systm.h>
73#include <sys/mbuf.h>
74#include <sys/malloc.h>
75#include <sys/kernel.h>
76#include <sys/socket.h>
77#include <sys/ioctl.h>
78#include <sys/errno.h>
79#include <sys/device.h>
80
81#include <machine/endian.h>
82
83#include <net/if.h>
84#include <net/if_dl.h>
85#include <net/if_media.h>
86#include <net/if_ether.h>
87
88#include <net80211/ieee80211_netbsd.h>
89#include <net80211/ieee80211_radiotap.h>
90#include <net80211/ieee80211_var.h>
91
92#include <sys/bus.h>
93#include <sys/intr.h>
94
95#include <dev/ic/rtwreg.h>
96#include <dev/ic/rtwvar.h>
97
98#include <dev/pci/pcivar.h>
99#include <dev/pci/pcireg.h>
100#include <dev/pci/pcidevs.h>
101
102#include <dev/cardbus/cardbusvar.h>
103#include <dev/pci/pcidevs.h>
104
105/*
106 * PCI configuration space registers used by the RTL8180.
107 */
108#define RTW_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
109#define RTW_PCI_MMBA PCI_BAR(1) /* memory mapped base */
110
111struct rtw_cardbus_softc {
112 struct rtw_softc sc_rtw; /* real RTL8180 softc */
113
114 /* CardBus-specific goo. */
115 void *sc_ih; /* interrupt handle */
116 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
117 pcitag_t sc_tag; /* our CardBus tag */
118 int sc_csr; /* CSR bits */
119 bus_size_t sc_mapsize; /* size of the mapped bus space
120 * region
121 */
122
123 int sc_bar; /* which BAR to use */
124};
125
126int rtw_cardbus_match(device_t, cfdata_t, void *);
127void rtw_cardbus_attach(device_t, device_t, void *);
128int rtw_cardbus_detach(device_t, int);
129
130CFATTACH_DECL3_NEW(rtw_cardbus, sizeof(struct rtw_cardbus_softc),
131 rtw_cardbus_match, rtw_cardbus_attach, rtw_cardbus_detach, NULL, NULL,
132 NULL, DVF_DETACH_SHUTDOWN);
133
134void rtw_cardbus_setup(struct rtw_cardbus_softc *);
135
136bool rtw_cardbus_resume(device_t, const pmf_qual_t *);
137bool rtw_cardbus_suspend(device_t, const pmf_qual_t *);
138
139const struct rtw_cardbus_product *rtw_cardbus_lookup(
140 const struct cardbus_attach_args *);
141
142const struct rtw_cardbus_product {
143 u_int32_t rcp_vendor; /* PCI vendor ID */
144 u_int32_t rcp_product; /* PCI product ID */
145 const char *rcp_product_name;
146} rtw_cardbus_products[] = {
147 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180,
148 "Realtek RTL8180 802.11 MAC/BBP" },
149
150 { PCI_VENDOR_BELKIN, PCI_PRODUCT_BELKIN_F5D6020V3,
151 "Belkin F5D6020v3 802.11b (RTL8180 MAC/BBP)" },
152
153 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610,
154 "DWL-610 D-Link Air 802.11b (RTL8180 MAC/BBP)" },
155
156 { 0, 0, NULL },
157};
158
159const struct rtw_cardbus_product *
160rtw_cardbus_lookup(const struct cardbus_attach_args *ca)
161{
162 const struct rtw_cardbus_product *rcp;
163
164 for (rcp = rtw_cardbus_products; rcp->rcp_product_name != NULL; rcp++) {
165 if (PCI_VENDOR(ca->ca_id) == rcp->rcp_vendor &&
166 PCI_PRODUCT(ca->ca_id) == rcp->rcp_product)
167 return rcp;
168 }
169 return NULL;
170}
171
172int
173rtw_cardbus_match(device_t parent, cfdata_t match, void *aux)
174{
175 struct cardbus_attach_args *ca = aux;
176
177 if (rtw_cardbus_lookup(ca) != NULL)
178 return 1;
179
180 return 0;
181}
182
183static void
184rtw_cardbus_funcregen(struct rtw_regs *regs, int enable)
185{
186 u_int32_t reg;
187 rtw_config0123_enable(regs, 1);
188 reg = RTW_READ(regs, RTW_CONFIG3);
189 if (enable)
190 RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN);
191 else
192 RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN);
193 rtw_config0123_enable(regs, 0);
194}
195
196void
197rtw_cardbus_attach(device_t parent, device_t self, void *aux)
198{
199 struct rtw_cardbus_softc *csc = device_private(self);
200 struct rtw_softc *sc = &csc->sc_rtw;
201 struct rtw_regs *regs = &sc->sc_regs;
202 struct cardbus_attach_args *ca = aux;
203 cardbus_devfunc_t ct = ca->ca_ct;
204 const struct rtw_cardbus_product *rcp;
205 bus_addr_t adr;
206
207 sc->sc_dev = self;
208 sc->sc_dmat = ca->ca_dmat;
209 csc->sc_ct = ct;
210 csc->sc_tag = ca->ca_tag;
211
212 rcp = rtw_cardbus_lookup(ca);
213 if (rcp == NULL) {
214 printf("\n");
215 panic("rtw_cardbus_attach: impossible");
216 }
217
218 printf(": %s\n", rcp->rcp_product_name);
219
220#ifdef notyet
221 /* Get revision info. */
222 int rev = PCI_REVISION(ca->ca_class);
223
224 RTW_DPRINTF(RTW_DEBUG_ATTACH,
225 ("%s: pass %d.%d signature %08x\n", device_xname(self),
226 (rev >> 4) & 0xf, rev & 0xf,
227 Cardbus_conf_read(ct, csc->sc_tag, 0x80)));
228#endif
229
230 /*
231 * Map the device.
232 */
233 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE |
234 PCI_COMMAND_PARITY_ENABLE |
235 PCI_COMMAND_SERR_ENABLE;
236 if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
237 &regs->r_bt, &regs->r_bh, &adr, &regs->r_sz) == 0) {
238 RTW_DPRINTF(RTW_DEBUG_ATTACH,
239 ("%s: %s mapped %" PRIuMAX " bytes mem space\n",
240 device_xname(self), __func__, (uintmax_t)regs->r_sz));
241 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
242 csc->sc_bar = RTW_PCI_MMBA;
243 } else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA, PCI_MAPREG_TYPE_IO,
244 0, &regs->r_bt, &regs->r_bh, &adr, &regs->r_sz) == 0) {
245 RTW_DPRINTF(RTW_DEBUG_ATTACH,
246 ("%s: %s mapped %" PRIuMAX " bytes I/O space\n",
247 device_xname(self), __func__, (uintmax_t)regs->r_sz));
248 csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
249 csc->sc_bar = RTW_PCI_IOBA;
250 } else {
251 aprint_error_dev(self, "unable to map device registers\n");
252 return;
253 }
254
255 /*
256 * Bring the chip out of powersave mode and initialize the
257 * configuration registers.
258 */
259 rtw_cardbus_setup(csc);
260
261 /*
262 * Finish off the attach.
263 */
264 rtw_attach(sc);
265
266 rtw_cardbus_funcregen(regs, 1);
267
268 RTW_WRITE(regs, RTW_FEMR, 0);
269 RTW_WRITE(regs, RTW_FER, RTW_READ(regs, RTW_FER));
270
271 if (pmf_device_register(self,
272 rtw_cardbus_suspend, rtw_cardbus_resume)) {
273 pmf_class_network_register(self, &sc->sc_if);
274 /*
275 * Power down the socket.
276 */
277 pmf_device_suspend(self, &sc->sc_qual);
278 } else
279 aprint_error_dev(self, "couldn't establish power handler\n");
280}
281
282int
283rtw_cardbus_detach(device_t self, int flags)
284{
285 struct rtw_cardbus_softc *csc = device_private(self);
286 struct rtw_softc *sc = &csc->sc_rtw;
287 struct rtw_regs *regs = &sc->sc_regs;
288 struct cardbus_devfunc *ct = csc->sc_ct;
289 int rc;
290
291#if defined(DIAGNOSTIC)
292 if (ct == NULL)
293 panic("%s: data structure lacks", device_xname(self));
294#endif
295
296 if ((rc = rtw_detach(sc)) != 0)
297 return rc;
298
299 /*
300 * Unhook the interrupt handler.
301 */
302 if (csc->sc_ih != NULL)
303 Cardbus_intr_disestablish(ct, csc->sc_ih);
304
305 /*
306 * Release bus space and close window.
307 */
308 if (csc->sc_bar != 0)
309 Cardbus_mapreg_unmap(ct, csc->sc_bar,
310 regs->r_bt, regs->r_bh, regs->r_sz);
311
312 return 0;
313}
314
315bool
316rtw_cardbus_resume(device_t self, const pmf_qual_t *qual)
317{
318 struct rtw_cardbus_softc *csc = device_private(self);
319 struct rtw_softc *sc = &csc->sc_rtw;
320 cardbus_devfunc_t ct = csc->sc_ct;
321
322 /*
323 * Map and establish the interrupt.
324 */
325 csc->sc_ih = Cardbus_intr_establish(ct, IPL_NET, rtw_intr, sc);
326 if (csc->sc_ih == NULL) {
327 aprint_error_dev(sc->sc_dev,
328 "unable to establish interrupt\n");
329 return false;
330 }
331
332 rtw_cardbus_funcregen(&sc->sc_regs, 1);
333
334 RTW_WRITE(&sc->sc_regs, RTW_FEMR, RTW_FEMR_INTR);
335 RTW_WRITE(&sc->sc_regs, RTW_FER, RTW_FER_INTR);
336
337 return rtw_resume(self, qual);
338}
339
340bool
341rtw_cardbus_suspend(device_t self, const pmf_qual_t *qual)
342{
343 struct rtw_cardbus_softc *csc = device_private(self);
344 struct rtw_softc *sc = &csc->sc_rtw;
345 cardbus_devfunc_t ct = csc->sc_ct;
346
347 if (!rtw_suspend(self, qual))
348 return false;
349
350 RTW_WRITE(&sc->sc_regs, RTW_FEMR,
351 RTW_READ(&sc->sc_regs, RTW_FEMR) & ~RTW_FEMR_INTR);
352
353 rtw_cardbus_funcregen(&sc->sc_regs, 0);
354
355 /* Unhook the interrupt handler. */
356 Cardbus_intr_disestablish(ct, csc->sc_ih);
357 csc->sc_ih = NULL;
358 return true;
359}
360
361void
362rtw_cardbus_setup(struct rtw_cardbus_softc *csc)
363{
364 pcitag_t tag = csc->sc_tag;
365 cardbus_devfunc_t ct = csc->sc_ct;
366 pcireg_t bhlc, csr, lattimer;
367
368 (void)cardbus_set_powerstate(ct, tag, PCI_PWR_D0);
369
370 /* I believe the datasheet tries to warn us that the RTL8180
371 * wants for 16 (0x10) to divide the latency timer.
372 */
373 bhlc = Cardbus_conf_read(ct, tag, PCI_BHLC_REG);
374 lattimer = rounddown(PCI_LATTIMER(bhlc), 0x10);
375 if (PCI_LATTIMER(bhlc) != lattimer) {
376 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
377 bhlc |= (lattimer << PCI_LATTIMER_SHIFT);
378 Cardbus_conf_write(ct, tag, PCI_BHLC_REG, bhlc);
379 }
380
381 /* Enable the appropriate bits in the PCI CSR. */
382 csr = Cardbus_conf_read(ct, tag, PCI_COMMAND_STATUS_REG);
383 csr &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
384 csr |= csc->sc_csr;
385 Cardbus_conf_write(ct, tag, PCI_COMMAND_STATUS_REG, csr);
386}
387