1 | /* $NetBSD: pcireg.h,v 1.117 2016/10/31 05:10:45 msaitoh Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1995, 1996, 1999, 2000 |
5 | * Christopher G. Demetriou. All rights reserved. |
6 | * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. |
7 | * |
8 | * Redistribution and use in source and binary forms, with or without |
9 | * modification, are permitted provided that the following conditions |
10 | * are met: |
11 | * 1. Redistributions of source code must retain the above copyright |
12 | * notice, this list of conditions and the following disclaimer. |
13 | * 2. Redistributions in binary form must reproduce the above copyright |
14 | * notice, this list of conditions and the following disclaimer in the |
15 | * documentation and/or other materials provided with the distribution. |
16 | * 3. All advertising materials mentioning features or use of this software |
17 | * must display the following acknowledgement: |
18 | * This product includes software developed by Charles M. Hannum. |
19 | * 4. The name of the author may not be used to endorse or promote products |
20 | * derived from this software without specific prior written permission. |
21 | * |
22 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
24 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
25 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
28 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
29 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
32 | */ |
33 | |
34 | #ifndef _DEV_PCI_PCIREG_H_ |
35 | #define _DEV_PCI_PCIREG_H_ |
36 | |
37 | /* |
38 | * Standardized PCI configuration information |
39 | */ |
40 | |
41 | /* |
42 | * Size of each function's configuration space. |
43 | */ |
44 | |
45 | #define PCI_CONF_SIZE 0x100 |
46 | #define PCI_EXTCONF_SIZE 0x1000 |
47 | |
48 | /* |
49 | * Device identification register; contains a vendor ID and a device ID. |
50 | */ |
51 | #define PCI_ID_REG 0x00 |
52 | |
53 | typedef u_int16_t pci_vendor_id_t; |
54 | typedef u_int16_t pci_product_id_t; |
55 | |
56 | #define PCI_VENDOR_SHIFT 0 |
57 | #define PCI_VENDOR_MASK 0xffff |
58 | #define PCI_VENDOR(id) \ |
59 | (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) |
60 | |
61 | #define PCI_PRODUCT_SHIFT 16 |
62 | #define PCI_PRODUCT_MASK 0xffff |
63 | #define PCI_PRODUCT(id) \ |
64 | (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) |
65 | |
66 | #define PCI_ID_CODE(vid,pid) \ |
67 | ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ |
68 | (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ |
69 | |
70 | /* |
71 | * Command and status register. |
72 | */ |
73 | #define PCI_COMMAND_STATUS_REG 0x04 |
74 | #define PCI_COMMAND_SHIFT 0 |
75 | #define PCI_COMMAND_MASK 0xffff |
76 | #define PCI_STATUS_SHIFT 16 |
77 | #define PCI_STATUS_MASK 0xffff |
78 | |
79 | #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ |
80 | ((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) | \ |
81 | (((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT)) \ |
82 | |
83 | #define PCI_COMMAND_IO_ENABLE 0x00000001 |
84 | #define PCI_COMMAND_MEM_ENABLE 0x00000002 |
85 | #define PCI_COMMAND_MASTER_ENABLE 0x00000004 |
86 | #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 |
87 | #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 |
88 | #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 |
89 | #define PCI_COMMAND_PARITY_ENABLE 0x00000040 |
90 | #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 |
91 | #define PCI_COMMAND_SERR_ENABLE 0x00000100 |
92 | #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 |
93 | #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 |
94 | |
95 | #define PCI_STATUS_IMMD_READNESS __BIT(0+16) |
96 | #define PCI_STATUS_INT_STATUS 0x00080000 |
97 | #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 |
98 | #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 |
99 | #define PCI_STATUS_UDF_SUPPORT 0x00400000 |
100 | #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 |
101 | #define PCI_STATUS_PARITY_ERROR 0x01000000 |
102 | #define PCI_STATUS_DEVSEL_FAST 0x00000000 |
103 | #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 |
104 | #define PCI_STATUS_DEVSEL_SLOW 0x04000000 |
105 | #define PCI_STATUS_DEVSEL_MASK 0x06000000 |
106 | #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 |
107 | #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 |
108 | #define PCI_STATUS_MASTER_ABORT 0x20000000 |
109 | #define PCI_STATUS_SPECIAL_ERROR 0x40000000 |
110 | #define PCI_STATUS_PARITY_DETECT 0x80000000 |
111 | |
112 | /* |
113 | * PCI Class and Revision Register; defines type and revision of device. |
114 | */ |
115 | #define PCI_CLASS_REG 0x08 |
116 | |
117 | typedef u_int8_t pci_class_t; |
118 | typedef u_int8_t pci_subclass_t; |
119 | typedef u_int8_t pci_interface_t; |
120 | typedef u_int8_t pci_revision_t; |
121 | |
122 | #define PCI_CLASS_SHIFT 24 |
123 | #define PCI_CLASS_MASK 0xff |
124 | #define PCI_CLASS(cr) \ |
125 | (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) |
126 | |
127 | #define PCI_SUBCLASS_SHIFT 16 |
128 | #define PCI_SUBCLASS_MASK 0xff |
129 | #define PCI_SUBCLASS(cr) \ |
130 | (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) |
131 | |
132 | #define PCI_INTERFACE_SHIFT 8 |
133 | #define PCI_INTERFACE_MASK 0xff |
134 | #define PCI_INTERFACE(cr) \ |
135 | (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) |
136 | |
137 | #define PCI_REVISION_SHIFT 0 |
138 | #define PCI_REVISION_MASK 0xff |
139 | #define PCI_REVISION(cr) \ |
140 | (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) |
141 | |
142 | #define PCI_CLASS_CODE(mainclass, subclass, interface) \ |
143 | ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ |
144 | (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ |
145 | (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) |
146 | |
147 | /* base classes */ |
148 | #define PCI_CLASS_PREHISTORIC 0x00 |
149 | #define PCI_CLASS_MASS_STORAGE 0x01 |
150 | #define PCI_CLASS_NETWORK 0x02 |
151 | #define PCI_CLASS_DISPLAY 0x03 |
152 | #define PCI_CLASS_MULTIMEDIA 0x04 |
153 | #define PCI_CLASS_MEMORY 0x05 |
154 | #define PCI_CLASS_BRIDGE 0x06 |
155 | #define PCI_CLASS_COMMUNICATIONS 0x07 |
156 | #define PCI_CLASS_SYSTEM 0x08 |
157 | #define PCI_CLASS_INPUT 0x09 |
158 | #define PCI_CLASS_DOCK 0x0a |
159 | #define PCI_CLASS_PROCESSOR 0x0b |
160 | #define PCI_CLASS_SERIALBUS 0x0c |
161 | #define PCI_CLASS_WIRELESS 0x0d |
162 | #define PCI_CLASS_I2O 0x0e |
163 | #define PCI_CLASS_SATCOM 0x0f |
164 | #define PCI_CLASS_CRYPTO 0x10 |
165 | #define PCI_CLASS_DASP 0x11 |
166 | #define PCI_CLASS_UNDEFINED 0xff |
167 | |
168 | /* 0x00 prehistoric subclasses */ |
169 | #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 |
170 | #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 |
171 | |
172 | /* 0x01 mass storage subclasses */ |
173 | #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 |
174 | #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 |
175 | #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 |
176 | #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 |
177 | #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 |
178 | #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 |
179 | #define PCI_INTERFACE_ATA_SINGLEDMA 0x20 |
180 | #define PCI_INTERFACE_ATA_CHAINEDDMA 0x30 |
181 | #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 |
182 | #define PCI_INTERFACE_SATA_VND 0x00 |
183 | #define PCI_INTERFACE_SATA_AHCI10 0x01 |
184 | #define PCI_INTERFACE_SATA_SSBI 0x02 |
185 | #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 |
186 | #define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08 |
187 | #define PCI_INTERFACE_NVM_VND 0x00 |
188 | #define PCI_INTERFACE_NVM_NVMHCI10 0x01 |
189 | #define PCI_INTERFACE_NVM_NVME 0x02 |
190 | #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 |
191 | |
192 | /* 0x02 network subclasses */ |
193 | #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 |
194 | #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 |
195 | #define PCI_SUBCLASS_NETWORK_FDDI 0x02 |
196 | #define PCI_SUBCLASS_NETWORK_ATM 0x03 |
197 | #define PCI_SUBCLASS_NETWORK_ISDN 0x04 |
198 | #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 |
199 | #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 |
200 | #define PCI_SUBCLASS_NETWORK_INFINIBAND 0x07 |
201 | #define PCI_SUBCLASS_NETWORK_MISC 0x80 |
202 | |
203 | /* 0x03 display subclasses */ |
204 | #define PCI_SUBCLASS_DISPLAY_VGA 0x00 |
205 | #define PCI_INTERFACE_VGA_VGA 0x00 |
206 | #define PCI_INTERFACE_VGA_8514 0x01 |
207 | #define PCI_SUBCLASS_DISPLAY_XGA 0x01 |
208 | #define PCI_SUBCLASS_DISPLAY_3D 0x02 |
209 | #define PCI_SUBCLASS_DISPLAY_MISC 0x80 |
210 | |
211 | /* 0x04 multimedia subclasses */ |
212 | #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 |
213 | #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 |
214 | #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 |
215 | #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 |
216 | #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 |
217 | |
218 | /* 0x05 memory subclasses */ |
219 | #define PCI_SUBCLASS_MEMORY_RAM 0x00 |
220 | #define PCI_SUBCLASS_MEMORY_FLASH 0x01 |
221 | #define PCI_SUBCLASS_MEMORY_MISC 0x80 |
222 | |
223 | /* 0x06 bridge subclasses */ |
224 | #define PCI_SUBCLASS_BRIDGE_HOST 0x00 |
225 | #define PCI_SUBCLASS_BRIDGE_ISA 0x01 |
226 | #define PCI_SUBCLASS_BRIDGE_EISA 0x02 |
227 | #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA */ |
228 | #define PCI_SUBCLASS_BRIDGE_PCI 0x04 |
229 | #define PCI_INTERFACE_BRIDGE_PCI_PCI 0x00 |
230 | #define PCI_INTERFACE_BRIDGE_PCI_SUBDEC 0x01 |
231 | #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 |
232 | #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 |
233 | #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 |
234 | #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 |
235 | /* bit0 == 0 ? "transparent mode" : "endpoint mode" */ |
236 | #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 |
237 | #define PCI_INTERFACE_STPCI_PRIMARY 0x40 |
238 | #define PCI_INTERFACE_STPCI_SECONDARY 0x80 |
239 | #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a |
240 | #define PCI_SUBCLASS_BRIDGE_ADVSW 0x0b |
241 | #define PCI_INTERFACE_ADVSW_CUSTOM 0x00 |
242 | #define PCI_INTERFACE_ADVSW_ASISIG 0x01 |
243 | #define PCI_SUBCLASS_BRIDGE_MISC 0x80 |
244 | |
245 | /* 0x07 communications subclasses */ |
246 | #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 |
247 | #define PCI_INTERFACE_SERIAL_XT 0x00 |
248 | #define PCI_INTERFACE_SERIAL_16450 0x01 |
249 | #define PCI_INTERFACE_SERIAL_16550 0x02 |
250 | #define PCI_INTERFACE_SERIAL_16650 0x03 |
251 | #define PCI_INTERFACE_SERIAL_16750 0x04 |
252 | #define PCI_INTERFACE_SERIAL_16850 0x05 |
253 | #define PCI_INTERFACE_SERIAL_16950 0x06 |
254 | #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 |
255 | #define PCI_INTERFACE_PARALLEL 0x00 |
256 | #define PCI_INTERFACE_PARALLEL_BIDIRECTIONAL 0x01 |
257 | #define PCI_INTERFACE_PARALLEL_ECP1X 0x02 |
258 | #define PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL 0x03 |
259 | #define PCI_INTERFACE_PARALLEL_IEEE1284_TGT 0xfe |
260 | #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 |
261 | #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 |
262 | #define PCI_INTERFACE_MODEM 0x00 |
263 | #define PCI_INTERFACE_MODEM_HAYES16450 0x01 |
264 | #define PCI_INTERFACE_MODEM_HAYES16550 0x02 |
265 | #define PCI_INTERFACE_MODEM_HAYES16650 0x03 |
266 | #define PCI_INTERFACE_MODEM_HAYES16750 0x04 |
267 | #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 |
268 | #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 |
269 | #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 |
270 | |
271 | /* 0x08 system subclasses */ |
272 | #define PCI_SUBCLASS_SYSTEM_PIC 0x00 |
273 | #define PCI_INTERFACE_PIC_8259 0x00 |
274 | #define PCI_INTERFACE_PIC_ISA 0x01 |
275 | #define PCI_INTERFACE_PIC_EISA 0x02 |
276 | #define PCI_INTERFACE_PIC_IOAPIC 0x10 |
277 | #define PCI_INTERFACE_PIC_IOXAPIC 0x20 |
278 | #define PCI_SUBCLASS_SYSTEM_DMA 0x01 |
279 | #define PCI_INTERFACE_DMA_8237 0x00 |
280 | #define PCI_INTERFACE_DMA_ISA 0x01 |
281 | #define PCI_INTERFACE_DMA_EISA 0x02 |
282 | #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 |
283 | #define PCI_INTERFACE_TIMER_8254 0x00 |
284 | #define PCI_INTERFACE_TIMER_ISA 0x01 |
285 | #define PCI_INTERFACE_TIMER_EISA 0x02 |
286 | #define PCI_INTERFACE_TIMER_HPET 0x03 |
287 | #define PCI_SUBCLASS_SYSTEM_RTC 0x03 |
288 | #define PCI_INTERFACE_RTC_GENERIC 0x00 |
289 | #define PCI_INTERFACE_RTC_ISA 0x01 |
290 | #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 |
291 | #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 |
292 | #define PCI_SUBCLASS_SYSTEM_IOMMU 0x06 /* or RCEC in old spec */ |
293 | #define PCI_SUBCLASS_SYSTEM_RCEC 0x07 |
294 | #define PCI_SUBCLASS_SYSTEM_MISC 0x80 |
295 | |
296 | /* 0x09 input subclasses */ |
297 | #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 |
298 | #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 |
299 | #define PCI_SUBCLASS_INPUT_MOUSE 0x02 |
300 | #define PCI_SUBCLASS_INPUT_SCANNER 0x03 |
301 | #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 |
302 | #define PCI_INTERFACE_GAMEPORT_GENERIC 0x00 |
303 | #define PCI_INTERFACE_GAMEPORT_LEGACY 0x10 |
304 | #define PCI_SUBCLASS_INPUT_MISC 0x80 |
305 | |
306 | /* 0x0a dock subclasses */ |
307 | #define PCI_SUBCLASS_DOCK_GENERIC 0x00 |
308 | #define PCI_SUBCLASS_DOCK_MISC 0x80 |
309 | |
310 | /* 0x0b processor subclasses */ |
311 | #define PCI_SUBCLASS_PROCESSOR_386 0x00 |
312 | #define PCI_SUBCLASS_PROCESSOR_486 0x01 |
313 | #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 |
314 | #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 |
315 | #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 |
316 | #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 |
317 | #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 |
318 | #define PCI_SUBCLASS_PROCESSOR_MISC 0x80 |
319 | |
320 | /* 0x0c serial bus subclasses */ |
321 | #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 |
322 | #define PCI_INTERFACE_IEEE1394_FIREWIRE 0x00 |
323 | #define PCI_INTERFACE_IEEE1394_OPENHCI 0x10 |
324 | #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 |
325 | #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 |
326 | #define PCI_SUBCLASS_SERIALBUS_USB 0x03 |
327 | #define PCI_INTERFACE_USB_UHCI 0x00 |
328 | #define PCI_INTERFACE_USB_OHCI 0x10 |
329 | #define PCI_INTERFACE_USB_EHCI 0x20 |
330 | #define PCI_INTERFACE_USB_XHCI 0x30 |
331 | #define PCI_INTERFACE_USB_OTHERHC 0x80 |
332 | #define PCI_INTERFACE_USB_DEVICE 0xfe |
333 | #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ |
334 | #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 |
335 | #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 /* Deprecated */ |
336 | #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 |
337 | #define PCI_INTERFACE_IPMI_SMIC 0x00 |
338 | #define PCI_INTERFACE_IPMI_KBD 0x01 |
339 | #define PCI_INTERFACE_IPMI_BLOCKXFER 0x02 |
340 | #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 |
341 | #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 |
342 | #define PCI_SUBCLASS_SERIALBUS_MISC 0x80 |
343 | |
344 | /* 0x0d wireless subclasses */ |
345 | #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 |
346 | #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 |
347 | #define PCI_INTERFACE_CONSUMERIR 0x00 |
348 | #define PCI_INTERFACE_UWB 0x10 |
349 | #define PCI_SUBCLASS_WIRELESS_RF 0x10 |
350 | #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 |
351 | #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 |
352 | #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 |
353 | #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 |
354 | #define PCI_SUBCLASS_WIRELESS_MISC 0x80 |
355 | |
356 | /* 0x0e I2O (Intelligent I/O) subclasses */ |
357 | #define PCI_SUBCLASS_I2O_STANDARD 0x00 |
358 | #define PCI_INTERFACE_I2O_FIFOAT40 0x00 |
359 | /* others for I2O spec */ |
360 | #define PCI_SUBCLASS_I2O_MISC 0x80 |
361 | |
362 | /* 0x0f satellite communication subclasses */ |
363 | /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ |
364 | #define PCI_SUBCLASS_SATCOM_TV 0x01 |
365 | #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 |
366 | #define PCI_SUBCLASS_SATCOM_VOICE 0x03 |
367 | #define PCI_SUBCLASS_SATCOM_DATA 0x04 |
368 | #define PCI_SUBCLASS_SATCOM_MISC 0x80 |
369 | |
370 | /* 0x10 encryption/decryption subclasses */ |
371 | #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 |
372 | #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 |
373 | #define PCI_SUBCLASS_CRYPTO_MISC 0x80 |
374 | |
375 | /* 0x11 data acquisition and signal processing subclasses */ |
376 | #define PCI_SUBCLASS_DASP_DPIO 0x00 |
377 | #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 /* performance counters */ |
378 | #define PCI_SUBCLASS_DASP_SYNC 0x10 |
379 | #define PCI_SUBCLASS_DASP_MGMT 0x20 |
380 | #define PCI_SUBCLASS_DASP_MISC 0x80 |
381 | |
382 | /* |
383 | * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. |
384 | */ |
385 | #define PCI_BHLC_REG 0x0c |
386 | |
387 | #define PCI_BIST_SHIFT 24 |
388 | #define PCI_BIST_MASK 0xff |
389 | #define PCI_BIST(bhlcr) \ |
390 | (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) |
391 | |
392 | #define PCI_HDRTYPE_SHIFT 16 |
393 | #define PCI_HDRTYPE_MASK 0xff |
394 | #define PCI_HDRTYPE(bhlcr) \ |
395 | (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) |
396 | |
397 | #define PCI_HDRTYPE_TYPE(bhlcr) \ |
398 | (PCI_HDRTYPE(bhlcr) & 0x7f) |
399 | #define PCI_HDRTYPE_MULTIFN(bhlcr) \ |
400 | ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) |
401 | |
402 | #define PCI_LATTIMER_SHIFT 8 |
403 | #define PCI_LATTIMER_MASK 0xff |
404 | #define PCI_LATTIMER(bhlcr) \ |
405 | (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) |
406 | |
407 | #define PCI_CACHELINE_SHIFT 0 |
408 | #define PCI_CACHELINE_MASK 0xff |
409 | #define PCI_CACHELINE(bhlcr) \ |
410 | (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) |
411 | |
412 | #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ |
413 | ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ |
414 | (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ |
415 | (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ |
416 | (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ |
417 | (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) |
418 | |
419 | /* |
420 | * PCI header type |
421 | */ |
422 | #define PCI_HDRTYPE_DEVICE 0 /* PCI/PCIX/Cardbus */ |
423 | #define PCI_HDRTYPE_PPB 1 /* PCI/PCIX/Cardbus */ |
424 | #define PCI_HDRTYPE_PCB 2 /* PCI/PCIX/Cardbus */ |
425 | #define PCI_HDRTYPE_EP 0 /* PCI Express */ |
426 | #define PCI_HDRTYPE_RC 1 /* PCI Express */ |
427 | |
428 | |
429 | /* |
430 | * Mapping registers |
431 | */ |
432 | #define PCI_MAPREG_START 0x10 |
433 | #define PCI_MAPREG_END 0x28 |
434 | #define PCI_MAPREG_ROM 0x30 |
435 | #define PCI_MAPREG_PPB_END 0x18 |
436 | #define PCI_MAPREG_PCB_END 0x14 |
437 | |
438 | #define PCI_BAR0 0x10 |
439 | #define PCI_BAR1 0x14 |
440 | #define PCI_BAR2 0x18 |
441 | #define PCI_BAR3 0x1C |
442 | #define PCI_BAR4 0x20 |
443 | #define PCI_BAR5 0x24 |
444 | |
445 | #define PCI_BAR(__n) (PCI_MAPREG_START + 4 * (__n)) |
446 | |
447 | #define PCI_MAPREG_TYPE(mr) \ |
448 | ((mr) & PCI_MAPREG_TYPE_MASK) |
449 | #define PCI_MAPREG_TYPE_MASK 0x00000001 |
450 | |
451 | #define PCI_MAPREG_TYPE_MEM 0x00000000 |
452 | #define PCI_MAPREG_TYPE_ROM 0x00000000 |
453 | #define PCI_MAPREG_TYPE_IO 0x00000001 |
454 | #define PCI_MAPREG_ROM_ENABLE 0x00000001 |
455 | |
456 | #define PCI_MAPREG_MEM_TYPE(mr) \ |
457 | ((mr) & PCI_MAPREG_MEM_TYPE_MASK) |
458 | #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 |
459 | |
460 | #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 |
461 | #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 |
462 | #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 |
463 | |
464 | #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ |
465 | (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) |
466 | #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 |
467 | |
468 | #define PCI_MAPREG_MEM_ADDR(mr) \ |
469 | ((mr) & PCI_MAPREG_MEM_ADDR_MASK) |
470 | #define PCI_MAPREG_MEM_SIZE(mr) \ |
471 | (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) |
472 | #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 |
473 | |
474 | #define PCI_MAPREG_MEM64_ADDR(mr) \ |
475 | ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) |
476 | #define PCI_MAPREG_MEM64_SIZE(mr) \ |
477 | (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) |
478 | #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL |
479 | |
480 | #define PCI_MAPREG_IO_ADDR(mr) \ |
481 | ((mr) & PCI_MAPREG_IO_ADDR_MASK) |
482 | #define PCI_MAPREG_IO_SIZE(mr) \ |
483 | (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) |
484 | #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc |
485 | |
486 | #define PCI_MAPREG_SIZE_TO_MASK(size) \ |
487 | (-(size)) |
488 | |
489 | #define PCI_MAPREG_NUM(offset) \ |
490 | (((unsigned)(offset)-PCI_MAPREG_START)/4) |
491 | |
492 | |
493 | /* |
494 | * Cardbus CIS pointer (PCI rev. 2.1) |
495 | */ |
496 | #define PCI_CARDBUS_CIS_REG 0x28 |
497 | |
498 | /* |
499 | * Subsystem identification register; contains a vendor ID and a device ID. |
500 | * Types/macros for PCI_ID_REG apply. |
501 | * (PCI rev. 2.1) |
502 | */ |
503 | #define PCI_SUBSYS_ID_REG 0x2c |
504 | |
505 | #define PCI_SUBSYS_VENDOR_MASK __BITS(15, 0) |
506 | #define PCI_SUBSYS_ID_MASK __BITS(31, 16) |
507 | |
508 | #define PCI_SUBSYS_VENDOR(__subsys_id) \ |
509 | __SHIFTOUT(__subsys_id, PCI_SUBSYS_VENDOR_MASK) |
510 | |
511 | #define PCI_SUBSYS_ID(__subsys_id) \ |
512 | __SHIFTOUT(__subsys_id, PCI_SUBSYS_ID_MASK) |
513 | |
514 | /* |
515 | * Capabilities link list (PCI rev. 2.2) |
516 | */ |
517 | #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ |
518 | #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ |
519 | #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) |
520 | #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) |
521 | #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) |
522 | |
523 | #define PCI_CAP_RESERVED0 0x00 |
524 | #define PCI_CAP_PWRMGMT 0x01 |
525 | #define PCI_CAP_AGP 0x02 |
526 | #define PCI_CAP_VPD 0x03 |
527 | #define PCI_CAP_SLOTID 0x04 |
528 | #define PCI_CAP_MSI 0x05 |
529 | #define PCI_CAP_CPCI_HOTSWAP 0x06 |
530 | #define PCI_CAP_PCIX 0x07 |
531 | #define PCI_CAP_LDT 0x08 /* HyperTransport */ |
532 | #define PCI_CAP_VENDSPEC 0x09 |
533 | #define PCI_CAP_DEBUGPORT 0x0a |
534 | #define PCI_CAP_CPCI_RSRCCTL 0x0b |
535 | #define PCI_CAP_HOTPLUG 0x0c /* Standard Hot-Plug Controller(SHPC)*/ |
536 | #define PCI_CAP_SUBVENDOR 0x0d |
537 | #define PCI_CAP_AGP8 0x0e |
538 | #define PCI_CAP_SECURE 0x0f |
539 | #define PCI_CAP_PCIEXPRESS 0x10 |
540 | #define PCI_CAP_MSIX 0x11 |
541 | #define PCI_CAP_SATA 0x12 |
542 | #define PCI_CAP_PCIAF 0x13 |
543 | #define PCI_CAP_EA 0x14 /* Enhanced Allocation (EA) */ |
544 | |
545 | /* |
546 | * Capability ID: 0x01 |
547 | * Power Management Capability; access via capability pointer. |
548 | */ |
549 | |
550 | /* Power Management Capability Register */ |
551 | #define PCI_PMCR_SHIFT 16 |
552 | #define PCI_PMCR 0x02 |
553 | #define PCI_PMCR_VERSION_MASK 0x0007 |
554 | #define PCI_PMCR_VERSION_10 0x0001 |
555 | #define PCI_PMCR_VERSION_11 0x0002 |
556 | #define PCI_PMCR_VERSION_12 0x0003 |
557 | #define PCI_PMCR_PME_CLOCK 0x0008 |
558 | #define PCI_PMCR_DSI 0x0020 |
559 | #define PCI_PMCR_AUXCUR_MASK 0x01c0 |
560 | #define PCI_PMCR_AUXCUR_0 0x0000 |
561 | #define PCI_PMCR_AUXCUR_55 0x0040 |
562 | #define PCI_PMCR_AUXCUR_100 0x0080 |
563 | #define PCI_PMCR_AUXCUR_160 0x00c0 |
564 | #define PCI_PMCR_AUXCUR_220 0x0100 |
565 | #define PCI_PMCR_AUXCUR_270 0x0140 |
566 | #define PCI_PMCR_AUXCUR_320 0x0180 |
567 | #define PCI_PMCR_AUXCUR_375 0x01c0 |
568 | #define PCI_PMCR_D1SUPP 0x0200 |
569 | #define PCI_PMCR_D2SUPP 0x0400 |
570 | #define PCI_PMCR_PME_D0 0x0800 |
571 | #define PCI_PMCR_PME_D1 0x1000 |
572 | #define PCI_PMCR_PME_D2 0x2000 |
573 | #define PCI_PMCR_PME_D3HOT 0x4000 |
574 | #define PCI_PMCR_PME_D3COLD 0x8000 |
575 | /* |
576 | * Power Management Control Status Register, Bridge Support Extensions Register |
577 | * and Data Register. |
578 | */ |
579 | #define PCI_PMCSR 0x04 |
580 | #define PCI_PMCSR_STATE_MASK 0x00000003 |
581 | #define PCI_PMCSR_STATE_D0 0x00000000 |
582 | #define PCI_PMCSR_STATE_D1 0x00000001 |
583 | #define PCI_PMCSR_STATE_D2 0x00000002 |
584 | #define PCI_PMCSR_STATE_D3 0x00000003 |
585 | #define PCI_PMCSR_NO_SOFTRST 0x00000008 |
586 | #define PCI_PMCSR_PME_EN 0x00000100 |
587 | #define PCI_PMCSR_DATASEL_MASK 0x00001e00 |
588 | #define PCI_PMCSR_DATASCL_MASK 0x00006000 |
589 | #define PCI_PMCSR_PME_STS 0x00008000 |
590 | #define PCI_PMCSR_B2B3_SUPPORT 0x00400000 |
591 | #define PCI_PMCSR_BPCC_EN 0x00800000 |
592 | |
593 | |
594 | /* |
595 | * Capability ID: 0x02 |
596 | * AGP |
597 | */ |
598 | #define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf) |
599 | #define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf) |
600 | |
601 | /* |
602 | * Capability ID: 0x03 |
603 | * Vital Product Data; access via capability pointer (PCI rev 2.2). |
604 | */ |
605 | #define PCI_VPD_ADDRESS_MASK 0x7fff |
606 | #define PCI_VPD_ADDRESS_SHIFT 16 |
607 | #define PCI_VPD_ADDRESS(ofs) \ |
608 | (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) |
609 | #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) |
610 | #define PCI_VPD_OPFLAG 0x80000000 |
611 | |
612 | /* |
613 | * Capability ID: 0x04 |
614 | * Slot ID |
615 | */ |
616 | |
617 | /* |
618 | * Capability ID: 0x05 |
619 | * MSI |
620 | */ |
621 | |
622 | #define PCI_MSI_CTL 0x0 /* Message Control Register offset */ |
623 | #define PCI_MSI_MADDR 0x4 /* Message Address Register (least |
624 | * significant bits) offset |
625 | */ |
626 | #define PCI_MSI_MADDR64_LO 0x4 /* 64-bit Message Address Register |
627 | * (least significant bits) offset |
628 | */ |
629 | #define PCI_MSI_MADDR64_HI 0x8 /* 64-bit Message Address Register |
630 | * (most significant bits) offset |
631 | */ |
632 | #define PCI_MSI_MDATA 0x8 /* Message Data Register offset */ |
633 | #define PCI_MSI_MDATA64 0xC /* 64-bit Message Data Register |
634 | * offset |
635 | */ |
636 | #define PCI_MSI_MASK 0x10 /* Vector Mask register */ |
637 | #define PCI_MSI_PENDING 0x14 /* Vector Pending register */ |
638 | |
639 | #define PCI_MSI_CTL_MASK __BITS(31, 16) |
640 | #define PCI_MSI_CTL_EXTMDATA_EN __SHIFTIN(__BIT(10), PCI_MSI_CTL_MASK) |
641 | #define PCI_MSI_CTL_EXTMDATA_CAP __SHIFTIN(__BIT(9), PCI_MSI_CTL_MASK) |
642 | #define PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK) |
643 | #define PCI_MSI_CTL_64BIT_ADDR __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK) |
644 | #define PCI_MSI_CTL_MME_MASK __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK) |
645 | #define PCI_MSI_CTL_MME(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MME_MASK) |
646 | #define PCI_MSI_CTL_MMC_MASK __SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK) |
647 | #define PCI_MSI_CTL_MMC(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MMC_MASK) |
648 | #define PCI_MSI_CTL_MSI_ENABLE __SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK) |
649 | |
650 | /* |
651 | * MSI Message Address is at offset 4. |
652 | * MSI Message Upper Address (if 64bit) is at offset 8. |
653 | * MSI Message data is at offset 8 or 12 and is 16 bits. |
654 | * [16 bit reserved field] |
655 | * MSI Mask Bits (32 bit field) |
656 | * MSI Pending Bits (32 bit field) |
657 | */ |
658 | |
659 | /* Max number of MSI vectors. See PCI-SIG specification. */ |
660 | #define PCI_MSI_MAX_VECTORS 32 |
661 | |
662 | /* |
663 | * Capability ID: 0x07 |
664 | * PCI-X capability. |
665 | * |
666 | * PCI-X capability register has two different layouts. One is for bridge |
667 | * function. Another is for non-bridge functions. |
668 | */ |
669 | |
670 | |
671 | /* For non-bridge functions */ |
672 | |
673 | /* |
674 | * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit |
675 | * word at the capability; the lower 16 bits are the capability ID and |
676 | * next capability pointer). |
677 | * |
678 | * Since we always read PCI config space in 32-bit words, we define these |
679 | * as 32-bit values, offset and shifted appropriately. Make sure you perform |
680 | * the appropriate R/M/W cycles! |
681 | */ |
682 | #define PCIX_CMD 0x00 |
683 | #define PCIX_CMD_PERR_RECOVER 0x00010000 |
684 | #define PCIX_CMD_RELAXED_ORDER 0x00020000 |
685 | #define PCIX_CMD_BYTECNT_MASK 0x000c0000 |
686 | #define PCIX_CMD_BYTECNT_SHIFT 18 |
687 | #define PCIX_CMD_BYTECNT(reg) \ |
688 | (512 << (((reg) & PCIX_CMD_BYTECNT_MASK) >> PCIX_CMD_BYTECNT_SHIFT)) |
689 | #define PCIX_CMD_BCNT_512 0x00000000 |
690 | #define PCIX_CMD_BCNT_1024 0x00040000 |
691 | #define PCIX_CMD_BCNT_2048 0x00080000 |
692 | #define PCIX_CMD_BCNT_4096 0x000c0000 |
693 | #define PCIX_CMD_SPLTRANS_MASK 0x00700000 |
694 | #define PCIX_CMD_SPLTRANS_SHIFT 20 |
695 | #define PCIX_CMD_SPLTRANS_1 0x00000000 |
696 | #define PCIX_CMD_SPLTRANS_2 0x00100000 |
697 | #define PCIX_CMD_SPLTRANS_3 0x00200000 |
698 | #define PCIX_CMD_SPLTRANS_4 0x00300000 |
699 | #define PCIX_CMD_SPLTRANS_8 0x00400000 |
700 | #define PCIX_CMD_SPLTRANS_12 0x00500000 |
701 | #define PCIX_CMD_SPLTRANS_16 0x00600000 |
702 | #define PCIX_CMD_SPLTRANS_32 0x00700000 |
703 | |
704 | /* |
705 | * Status. 32 bits at offset 4. |
706 | */ |
707 | #define PCIX_STATUS 0x04 |
708 | #define PCIX_STATUS_FN_MASK 0x00000007 |
709 | #define PCIX_STATUS_DEV_MASK 0x000000f8 |
710 | #define PCIX_STATUS_DEV_SHIFT 3 |
711 | #define PCIX_STATUS_BUS_MASK 0x0000ff00 |
712 | #define PCIX_STATUS_BUS_SHIFT 8 |
713 | #define PCIX_STATUS_FN(val) ((val) & PCIX_STATUS_FN_MASK) |
714 | #define PCIX_STATUS_DEV(val) \ |
715 | (((val) & PCIX_STATUS_DEV_MASK) >> PCIX_STATUS_DEV_SHIFT) |
716 | #define PCIX_STATUS_BUS(val) \ |
717 | (((val) & PCIX_STATUS_BUS_MASK) >> PCIX_STATUS_BUS_SHIFT) |
718 | #define PCIX_STATUS_64BIT 0x00010000 /* 64bit device */ |
719 | #define PCIX_STATUS_133 0x00020000 /* 133MHz capable */ |
720 | #define PCIX_STATUS_SPLDISC 0x00040000 /* Split completion discarded*/ |
721 | #define PCIX_STATUS_SPLUNEX 0x00080000 /* Unexpected split complet. */ |
722 | #define PCIX_STATUS_DEVCPLX 0x00100000 /* Device Complexity */ |
723 | #define PCIX_STATUS_MAXB_MASK 0x00600000 /* MAX memory read Byte count*/ |
724 | #define PCIX_STATUS_MAXB_SHIFT 21 |
725 | #define PCIX_STATUS_MAXB_512 0x00000000 |
726 | #define PCIX_STATUS_MAXB_1024 0x00200000 |
727 | #define PCIX_STATUS_MAXB_2048 0x00400000 |
728 | #define PCIX_STATUS_MAXB_4096 0x00600000 |
729 | #define PCIX_STATUS_MAXST_MASK 0x03800000 /* MAX outstand. Split Trans.*/ |
730 | #define PCIX_STATUS_MAXST_SHIFT 23 |
731 | #define PCIX_STATUS_MAXST_1 0x00000000 |
732 | #define PCIX_STATUS_MAXST_2 0x00800000 |
733 | #define PCIX_STATUS_MAXST_3 0x01000000 |
734 | #define PCIX_STATUS_MAXST_4 0x01800000 |
735 | #define PCIX_STATUS_MAXST_8 0x02000000 |
736 | #define PCIX_STATUS_MAXST_12 0x02800000 |
737 | #define PCIX_STATUS_MAXST_16 0x03000000 |
738 | #define PCIX_STATUS_MAXST_32 0x03800000 |
739 | #define PCIX_STATUS_MAXRS_MASK 0x1c000000 /* MAX cumulative Read Size */ |
740 | #define PCIX_STATUS_MAXRS_SHIFT 26 |
741 | #define PCIX_STATUS_MAXRS_1K 0x00000000 |
742 | #define PCIX_STATUS_MAXRS_2K 0x04000000 |
743 | #define PCIX_STATUS_MAXRS_4K 0x08000000 |
744 | #define PCIX_STATUS_MAXRS_8K 0x0c000000 |
745 | #define PCIX_STATUS_MAXRS_16K 0x10000000 |
746 | #define PCIX_STATUS_MAXRS_32K 0x14000000 |
747 | #define PCIX_STATUS_MAXRS_64K 0x18000000 |
748 | #define PCIX_STATUS_MAXRS_128K 0x1c000000 |
749 | #define PCIX_STATUS_SCERR 0x20000000 /* rcv. Split Completion ERR.*/ |
750 | #define PCIX_STATUS_266 0x40000000 /* 266MHz capable */ |
751 | #define PCIX_STATUS_533 0x80000000 /* 533MHz capable */ |
752 | |
753 | /* For bridge function */ |
754 | |
755 | #define PCIX_BRIDGE_2ND_STATUS 0x00 |
756 | #define PCIX_BRIDGE_ST_64BIT 0x00010000 /* Same as PCIX_STATUS (nonb)*/ |
757 | #define PCIX_BRIDGE_ST_133 0x00020000 /* Same as PCIX_STATUS (nonb)*/ |
758 | #define PCIX_BRIDGE_ST_SPLDISC 0x00040000 /* Same as PCIX_STATUS (nonb)*/ |
759 | #define PCIX_BRIDGE_ST_SPLUNEX 0x00080000 /* Same as PCIX_STATUS (nonb)*/ |
760 | #define PCIX_BRIDGE_ST_SPLOVRN 0x00100000 /* Split completion overrun */ |
761 | #define PCIX_BRIDGE_ST_SPLRQDL 0x00200000 /* Split request delayed */ |
762 | #define PCIX_BRIDGE_2NDST_CLKF 0x03c00000 /* Secondary clock frequency */ |
763 | #define PCIX_BRIDGE_2NDST_CLKF_SHIFT 22 |
764 | #define PCIX_BRIDGE_2NDST_VER_MASK 0x30000000 /* Version */ |
765 | #define PCIX_BRIDGE_2NDST_VER_SHIFT 28 |
766 | #define PCIX_BRIDGE_ST_266 0x40000000 /* Same as PCIX_STATUS (nonb)*/ |
767 | #define PCIX_BRIDGE_ST_533 0x80000000 /* Same as PCIX_STATUS (nonb)*/ |
768 | |
769 | #define PCIX_BRIDGE_PRI_STATUS 0x04 |
770 | /* Bit 0 to 15 are the same as PCIX_STATUS */ |
771 | /* Bit 16 to 21 are the same as PCIX_BRIDGE_2ND_STATUS */ |
772 | /* Bit 30 and 31 are the same as PCIX_BRIDGE_2ND_STATUS */ |
773 | |
774 | #define PCIX_BRIDGE_UP_STCR 0x08 /* Upstream Split Transaction Control */ |
775 | #define PCIX_BRIDGE_DOWN_STCR 0x0c /* Downstream Split Transaction Control */ |
776 | /* The layouts of above two registers are the same */ |
777 | #define PCIX_BRIDGE_STCAP 0x0000ffff /* Sp. Tr. Capacity */ |
778 | #define PCIX_BRIDGE_STCLIM 0xffff0000 /* Sp. Tr. Commitment Limit */ |
779 | #define PCIX_BRIDGE_STCLIM_SHIFT 16 |
780 | |
781 | /* |
782 | * Capability ID: 0x08 |
783 | * HyperTransport |
784 | */ |
785 | |
786 | #define PCI_HT_CMD 0x00 /* Capability List & Command Register */ |
787 | #define PCI_HT_CMD_MASK __BITS(31, 16) |
788 | #define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \ |
789 | (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f)) |
790 | #define PCI_HT_CAPMASK __BITS(31, 27) |
791 | #define PCI_HT_CAP_SLAVE 0b00000 /* 000xx */ |
792 | #define PCI_HT_CAP_HOST 0b00100 /* 001xx */ |
793 | #define PCI_HT_CAP_SWITCH 0b01000 |
794 | #define PCI_HT_CAP_INTERRUPT 0b10000 |
795 | #define PCI_HT_CAP_REVID 0b10001 |
796 | #define PCI_HT_CAP_UNITID_CLUMP 0b10010 |
797 | #define PCI_HT_CAP_EXTCNFSPACE 0b10011 |
798 | #define PCI_HT_CAP_ADDRMAP 0b10100 |
799 | #define PCI_HT_CAP_MSIMAP 0b10101 |
800 | #define PCI_HT_CAP_DIRECTROUTE 0b10110 |
801 | #define PCI_HT_CAP_VCSET 0b10111 |
802 | #define PCI_HT_CAP_RETRYMODE 0b11000 |
803 | #define PCI_HT_CAP_X86ENCODE 0b11001 |
804 | #define PCI_HT_CAP_GEN3 0b11010 |
805 | #define PCI_HT_CAP_FLE 0b11011 |
806 | #define PCI_HT_CAP_PM 0b11100 |
807 | #define PCI_HT_CAP_HIGHNODECNT 0b11101 |
808 | |
809 | /* |
810 | * HT Cap ID: 0b10101 |
811 | * MSI Mapping |
812 | */ |
813 | |
814 | /* Command register bits (31-16)*/ |
815 | #define PCI_HT_MSI_ENABLED __BIT(16) |
816 | #define PCI_HT_MSI_FIXED __BIT(17) |
817 | |
818 | #define PCI_HT_MSI_ADDR_LO 0x04 /* Address register (low) */ |
819 | #define PCI_HT_MSI_ADDR_LO_MASK __BITS(31, 20) |
820 | #define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL |
821 | #define PCI_HT_MSI_ADDR_HI 0x08 /* Address Register (high) */ |
822 | |
823 | /* |
824 | * Capability ID: 0x09 |
825 | * Vendor Specific |
826 | */ |
827 | #define PCI_VENDORSPECIFIC_SHIFT 16 |
828 | #define PCI_VENDORSPECIFIC 0x02 |
829 | |
830 | /* |
831 | * Capability ID: 0x0a |
832 | * Debug Port |
833 | */ |
834 | #define PCI_DEBUG_BASER 0x00 /* Debug Base Register */ |
835 | #define PCI_DEBUG_BASER_SHIFT 16 |
836 | #define PCI_DEBUG_PORTOFF_SHIFT 16 |
837 | #define PCI_DEBUG_PORTOFF_MASK 0x1fff0000 /* Debug port offset */ |
838 | #define PCI_DEBUG_BARNUM_SHIFT 29 |
839 | #define PCI_DEBUG_BARNUM_MASK 0xe0000000 /* BAR number */ |
840 | |
841 | /* |
842 | * Capability ID: 0x0b |
843 | * Compact PCI |
844 | */ |
845 | |
846 | /* |
847 | * Capability ID: 0x0c |
848 | * Hotplug |
849 | */ |
850 | |
851 | /* |
852 | * Capability ID: 0x0d |
853 | * Subsystem |
854 | */ |
855 | #define PCI_CAP_SUBSYS_ID 0x04 |
856 | /* bit field layout is the same as PCI_SUBSYS_ID_REG's one */ |
857 | |
858 | /* |
859 | * Capability ID: 0x0e |
860 | * AGP8 |
861 | */ |
862 | |
863 | /* |
864 | * Capability ID: 0x0f |
865 | * Secure |
866 | */ |
867 | |
868 | /* |
869 | * Capability ID: 0x10 |
870 | * PCI Express; access via capability pointer. |
871 | */ |
872 | #define PCIE_XCAP 0x00 /* Capability List & Capabilities Register */ |
873 | #define PCIE_XCAP_MASK __BITS(31, 16) |
874 | /* Capability Version */ |
875 | #define PCIE_XCAP_VER_MASK __SHIFTIN(__BITS(3, 0), PCIE_XCAP_MASK) |
876 | #define PCIE_XCAP_VER(x) __SHIFTOUT((x), PCIE_XCAP_VER_MASK) |
877 | #define PCIE_XCAP_VER_1 1 |
878 | #define PCIE_XCAP_VER_2 2 |
879 | #define PCIE_XCAP_TYPE_MASK __SHIFTIN(__BITS(7, 4), PCIE_XCAP_MASK) |
880 | #define PCIE_XCAP_TYPE(x) __SHIFTOUT((x), PCIE_XCAP_TYPE_MASK) |
881 | #define PCIE_XCAP_TYPE_PCIE_DEV 0x0 |
882 | #define PCIE_XCAP_TYPE_PCI_DEV 0x1 |
883 | #define PCIE_XCAP_TYPE_ROOT 0x4 |
884 | #define PCIE_XCAP_TYPE_UP 0x5 |
885 | #define PCIE_XCAP_TYPE_DOWN 0x6 |
886 | #define PCIE_XCAP_TYPE_PCIE2PCI 0x7 |
887 | #define PCIE_XCAP_TYPE_PCI2PCIE 0x8 |
888 | #define PCIE_XCAP_TYPE_ROOT_INTEP 0x9 |
889 | #define PCIE_XCAP_TYPE_ROOT_EVNTC 0xa |
890 | #define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */ |
891 | #define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK) |
892 | #define PCIE_DCAP 0x04 /* Device Capabilities Register */ |
893 | #define PCIE_DCAP_MAX_PAYLOAD __BITS(2, 0) /* Max Payload Size Supported */ |
894 | #define PCIE_DCAP_PHANTOM_FUNCS __BITS(4, 3) /* Phantom Functions Supported*/ |
895 | #define PCIE_DCAP_EXT_TAG_FIELD __BIT(5) /* Extended Tag Field Support */ |
896 | #define PCIE_DCAP_L0S_LATENCY __BITS(8, 6) /* Endpoint L0 Accptbl Latency*/ |
897 | #define PCIE_DCAP_L1_LATENCY __BITS(11, 9) /* Endpoint L1 Accptbl Latency*/ |
898 | #define PCIE_DCAP_ATTN_BUTTON __BIT(12) /* Attention Indicator Button */ |
899 | #define PCIE_DCAP_ATTN_IND __BIT(13) /* Attention Indicator Present*/ |
900 | #define PCIE_DCAP_PWR_IND __BIT(14) /* Power Indicator Present */ |
901 | #define PCIE_DCAP_ROLE_ERR_RPT __BIT(15) /* Role-Based Error Reporting */ |
902 | #define PCIE_DCAP_SLOT_PWR_LIM_VAL __BITS(25, 18) /* Cap. Slot PWR Limit Val */ |
903 | #define PCIE_DCAP_SLOT_PWR_LIM_SCALE __BITS(27, 26) /* Cap. SlotPWRLimit Scl */ |
904 | #define PCIE_DCAP_FLR __BIT(28) /* Function-Level Reset Cap. */ |
905 | #define PCIE_DCSR 0x08 /* Device Control & Status Register */ |
906 | #define PCIE_DCSR_ENA_COR_ERR __BIT(0) /* Correctable Error Report En*/ |
907 | #define PCIE_DCSR_ENA_NFER __BIT(1) /* Non-Fatal Error Report En. */ |
908 | #define PCIE_DCSR_ENA_FER __BIT(2) /* Fatal Error Reporting Enabl*/ |
909 | #define PCIE_DCSR_ENA_URR __BIT(3) /* Unsupported Request Rpt En */ |
910 | #define PCIE_DCSR_ENA_RELAX_ORD __BIT(4) /* Enable Relaxed Ordering */ |
911 | #define PCIE_DCSR_MAX_PAYLOAD __BITS(7, 5) /* Max Payload Size */ |
912 | #define PCIE_DCSR_EXT_TAG_FIELD __BIT(8) /* Extended Tag Field Enable */ |
913 | #define PCIE_DCSR_PHANTOM_FUNCS __BIT(9) /* Phantom Functions Enable */ |
914 | #define PCIE_DCSR_AUX_POWER_PM __BIT(10) /* Aux Power PM Enable */ |
915 | #define PCIE_DCSR_ENA_NO_SNOOP __BIT(11) /* Enable No Snoop */ |
916 | #define PCIE_DCSR_MAX_READ_REQ __BITS(14, 12) /* Max Read Request Size */ |
917 | #define PCIE_DCSR_BRDG_CFG_RETRY __BIT(15) /* Bridge Config Retry Enable */ |
918 | #define PCIE_DCSR_INITIATE_FLR __BIT(15) /* Initiate Function-Level Rst*/ |
919 | #define PCIE_DCSR_CED __BIT(0 + 16) /* Correctable Error Detected */ |
920 | #define PCIE_DCSR_NFED __BIT(1 + 16) /* Non-Fatal Error Detected */ |
921 | #define PCIE_DCSR_FED __BIT(2 + 16) /* Fatal Error Detected */ |
922 | #define PCIE_DCSR_URD __BIT(3 + 16) /* Unsupported Req. Detected */ |
923 | #define PCIE_DCSR_AUX_PWR __BIT(4 + 16) /* Aux Power Detected */ |
924 | #define PCIE_DCSR_TRANSACTION_PND __BIT(5 + 16) /* Transaction Pending */ |
925 | #define PCIE_DCSR_EMGPWRREDD __BIT(6 + 16) /* Emg. Pwr. Reduct. Detected */ |
926 | #define PCIE_LCAP 0x0c /* Link Capabilities Register */ |
927 | #define PCIE_LCAP_MAX_SPEED __BITS(3, 0) /* Max Link Speed */ |
928 | #define PCIE_LCAP_MAX_WIDTH __BITS(9, 4) /* Maximum Link Width */ |
929 | #define PCIE_LCAP_ASPM __BITS(11, 10) /* Active State Link PM Supp. */ |
930 | #define PCIE_LCAP_L0S_EXIT __BITS(14, 12) /* L0s Exit Latency */ |
931 | #define PCIE_LCAP_L1_EXIT __BITS(17, 15) /* L1 Exit Latency */ |
932 | #define PCIE_LCAP_CLOCK_PM __BIT(18) /* Clock Power Management */ |
933 | #define PCIE_LCAP_SURPRISE_DOWN __BIT(19) /* Surprise Down Err Rpt Cap. */ |
934 | #define PCIE_LCAP_DL_ACTIVE __BIT(20) /* Data Link Layer Link Active*/ |
935 | #define PCIE_LCAP_LINK_BW_NOTIFY __BIT(21) /* Link BW Notification Capabl*/ |
936 | #define PCIE_LCAP_ASPM_COMPLIANCE __BIT(22) /* ASPM Optionally Compliance */ |
937 | #define PCIE_LCAP_PORT __BITS(31, 24) /* Port Number */ |
938 | #define PCIE_LCSR 0x10 /* Link Control & Status Register */ |
939 | #define PCIE_LCSR_ASPM_L0S __BIT(0) /* Active State PM Control L0s*/ |
940 | #define PCIE_LCSR_ASPM_L1 __BIT(1) /* Active State PM Control L1 */ |
941 | #define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundry Ctl*/ |
942 | #define PCIE_LCSR_LINK_DIS __BIT(4) /* Link Disable */ |
943 | #define PCIE_LCSR_RETRAIN __BIT(5) /* Retrain Link */ |
944 | #define PCIE_LCSR_COMCLKCFG __BIT(6) /* Common Clock Configuration */ |
945 | #define PCIE_LCSR_EXTNDSYNC __BIT(7) /* Extended Synch */ |
946 | #define PCIE_LCSR_ENCLKPM __BIT(8) /* Enable Clock Power Managmt */ |
947 | #define PCIE_LCSR_HAWD __BIT(9) /* HW Autonomous Width Disable*/ |
948 | #define PCIE_LCSR_LBMIE __BIT(10) /* Link BW Management Intr En */ |
949 | #define PCIE_LCSR_LABIE __BIT(11) /* Link Autonomous BW Intr En */ |
950 | #define __BITS(15, 14) /* DRS Signaling */ |
951 | #define PCIE_LCSR_LINKSPEED __BITS(19, 16) /* Link Speed */ |
952 | #define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */ |
953 | #define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */ |
954 | #define PCIE_LCSR_LINKTRAIN __BIT(11 + 16) /* Link Training */ |
955 | #define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */ |
956 | #define PCIE_LCSR_DLACTIVE __BIT(13 + 16) /* Data Link Layer Link Active*/ |
957 | #define PCIE_LCSR_LINK_BW_MGMT __BIT(14 + 16) /* Link BW Management Status */ |
958 | #define PCIE_LCSR_LINK_AUTO_BW __BIT(15 + 16) /* Link Autonomous BW Status */ |
959 | #define PCIE_SLCAP 0x14 /* Slot Capabilities Register */ |
960 | #define PCIE_SLCAP_ABP __BIT(0) /* Attention Button Present */ |
961 | #define PCIE_SLCAP_PCP __BIT(1) /* Power Controller Present */ |
962 | #define PCIE_SLCAP_MSP __BIT(2) /* MRL Sensor Present */ |
963 | #define PCIE_SLCAP_AIP __BIT(3) /* Attention Indicator Present*/ |
964 | #define PCIE_SLCAP_PIP __BIT(4) /* Power Indicator Present */ |
965 | #define PCIE_SLCAP_HPS __BIT(5) /* Hot-Plug Surprise */ |
966 | #define PCIE_SLCAP_HPC __BIT(6) /* Hot-Plug Capable */ |
967 | #define PCIE_SLCAP_SPLV __BITS(14, 7) /* Slot Power Limit Value */ |
968 | #define PCIE_SLCAP_SPLS __BITS(16, 15) /* Slot Power Limit Scale */ |
969 | #define PCIE_SLCAP_EIP __BIT(17) /* Electromechanical Interlock*/ |
970 | #define PCIE_SLCAP_NCCS __BIT(18) /* No Command Completed Supp. */ |
971 | #define PCIE_SLCAP_PSN __BITS(31, 19) /* Physical Slot Number */ |
972 | #define PCIE_SLCSR 0x18 /* Slot Control & Status Register */ |
973 | #define PCIE_SLCSR_ABE __BIT(0) /* Attention Button Pressed En*/ |
974 | #define PCIE_SLCSR_PFE __BIT(1) /* Power Button Pressed Enable*/ |
975 | #define PCIE_SLCSR_MSE __BIT(2) /* MRL Sensor Changed Enable */ |
976 | #define PCIE_SLCSR_PDE __BIT(3) /* Presence Detect Changed Ena*/ |
977 | #define PCIE_SLCSR_CCE __BIT(4) /* Command Completed Intr. En */ |
978 | #define PCIE_SLCSR_HPE __BIT(5) /* Hot Plug Interrupt Enable */ |
979 | #define PCIE_SLCSR_AIC __BITS(7, 6) /* Attention Indicator Control*/ |
980 | #define PCIE_SLCSR_PIC __BITS(9, 8) /* Power Indicator Control */ |
981 | #define PCIE_SLCSR_PCC __BIT(10) /* Power Controller Control */ |
982 | #define PCIE_SLCSR_EIC __BIT(11) /* Electromechanical Interlock*/ |
983 | #define PCIE_SLCSR_DLLSCE __BIT(12) /* DataLinkLayer State Changed*/ |
984 | #define PCIE_SLCSR_AUTOSPLDIS __BIT(13) /* Auto Slot Power Limit Dis. */ |
985 | #define PCIE_SLCSR_ABP __BIT(0 + 16) /* Attention Button Pressed */ |
986 | #define PCIE_SLCSR_PFD __BIT(1 + 16) /* Power Fault Detected */ |
987 | #define PCIE_SLCSR_MSC __BIT(2 + 16) /* MRL Sensor Changed */ |
988 | #define PCIE_SLCSR_PDC __BIT(3 + 16) /* Presence Detect Changed */ |
989 | #define PCIE_SLCSR_CC __BIT(4 + 16) /* Command Completed */ |
990 | #define PCIE_SLCSR_MS __BIT(5 + 16) /* MRL Sensor State */ |
991 | #define PCIE_SLCSR_PDS __BIT(6 + 16) /* Presence Detect State */ |
992 | #define PCIE_SLCSR_EIS __BIT(7 + 16) /* Electromechanical Interlock*/ |
993 | #define PCIE_SLCSR_LACS __BIT(8 + 16) /* Data Link Layer State Chg. */ |
994 | #define PCIE_RCR 0x1c /* Root Control & Capabilities Reg. */ |
995 | #define PCIE_RCR_SERR_CER __BIT(0) /* SERR on Correctable Err. En*/ |
996 | #define PCIE_RCR_SERR_NFER __BIT(1) /* SERR on Non-Fatal Error En */ |
997 | #define PCIE_RCR_SERR_FER __BIT(2) /* SERR on Fatal Error Enable */ |
998 | #define PCIE_RCR_PME_IE __BIT(3) /* PME Interrupt Enable */ |
999 | #define PCIE_RCR_CRS_SVE __BIT(4) /* CRS Software Visibility En */ |
1000 | #define PCIE_RCR_CRS_SV __BIT(16) /* CRS Software Visibility */ |
1001 | #define PCIE_RSR 0x20 /* Root Status Register */ |
1002 | #define PCIE_RSR_PME_REQESTER __BITS(15, 0) /* PME Requester ID */ |
1003 | #define PCIE_RSR_PME_STAT __BIT(16) /* PME Status */ |
1004 | #define PCIE_RSR_PME_PEND __BIT(17) /* PME Pending */ |
1005 | #define PCIE_DCAP2 0x24 /* Device Capabilities 2 Register */ |
1006 | #define PCIE_DCAP2_COMPT_RANGE __BITS(3,0) /* Compl. Timeout Ranges Supp */ |
1007 | #define PCIE_DCAP2_COMPT_DIS __BIT(4) /* Compl. Timeout Disable Supp*/ |
1008 | #define PCIE_DCAP2_ARI_FWD __BIT(5) /* ARI Forward Supported */ |
1009 | #define PCIE_DCAP2_ATOM_ROUT __BIT(6) /* AtomicOp Routing Supported */ |
1010 | #define PCIE_DCAP2_32ATOM __BIT(7) /* 32bit AtomicOp Compl. Supp */ |
1011 | #define PCIE_DCAP2_64ATOM __BIT(8) /* 64bit AtomicOp Compl. Supp */ |
1012 | #define PCIE_DCAP2_128CAS __BIT(9) /* 128bit Cas Completer Supp. */ |
1013 | #define PCIE_DCAP2_NO_ROPR_PASS __BIT(10) /* No RO-enabled PR-PR Passng */ |
1014 | #define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */ |
1015 | #define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */ |
1016 | #define PCIE_DCAP2_LNSYSCLS __BITS(15, 14) /* LN System CLS */ |
1017 | #define PCIE_DCAP2_OBFF __BITS(19, 18) /* Optimized Buffer Flush/Fill*/ |
1018 | #define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */ |
1019 | #define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */ |
1020 | #define PCIE_DCAP2_MAX_EETLP __BITS(23, 22) /* Max End-End TLP Prefix Sup */ |
1021 | #define PCIE_DCAP2_EMGPWRRED __BITS(25, 24) /* Emergency Power Reduc. Sup */ |
1022 | #define PCIE_DCAP2_EMGPWRRED_INI __BIT(26) /* Emrg. Pwr. Reduc. Ini. Req */ |
1023 | #define PCIE_DCAP2_FRS __BIT(31) /* FRS Supported */ |
1024 | #define PCIE_DCSR2 0x28 /* Device Control & Status 2 Register */ |
1025 | #define PCIE_DCSR2_COMPT_VAL __BITS(3, 0) /* Completion Timeout Value */ |
1026 | #define PCIE_DCSR2_COMPT_DIS __BIT(4) /* Completion Timeout Disable */ |
1027 | #define PCIE_DCSR2_ARI_FWD __BIT(5) /* ARI Forwarding Enable */ |
1028 | #define PCIE_DCSR2_ATOM_REQ __BIT(6) /* AtomicOp Requester Enable */ |
1029 | #define PCIE_DCSR2_ATOM_EBLK __BIT(7) /* AtomicOp Egress Blocking */ |
1030 | #define PCIE_DCSR2_IDO_REQ __BIT(8) /* IDO Request Enable */ |
1031 | #define PCIE_DCSR2_IDO_COMP __BIT(9) /* IDO Completion Enable */ |
1032 | #define PCIE_DCSR2_LTR_MEC __BIT(10) /* LTR Mechanism Enable */ |
1033 | #define PCIE_DCSR2_EMGPWRRED_REQ __BIT(11) /* Emergency Power Reduc. Req */ |
1034 | #define PCIE_DCSR2_OBFF_EN __BITS(14, 13) /* OBFF Enable */ |
1035 | #define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */ |
1036 | #define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */ |
1037 | #define PCIE_LCAP2_SUP_LNKSV __BITS(7, 1) /* Supported Link Speeds Vect */ |
1038 | #define PCIE_LCAP2_CROSSLNK __BIT(8) /* Crosslink Supported */ |
1039 | #define PCIE_LCAP2_LOWSKPOS_GENSUPPSV __BITS(15, 9) |
1040 | /* Lower SKP OS Generation Supp. Spd. Vect */ |
1041 | #define PCIE_LCAP2_LOWSKPOS_RECSUPPSV __BITS(22, 16) |
1042 | /* Lower SKP OS Reception Supp. Spd. Vect */ |
1043 | #define PCIE_LCAP2_RETIMERPD __BIT(23) /* Retimer Presence Detect */ |
1044 | #define PCIE_LCAP2_DRS __BIT(31) /* DRS Supported */ |
1045 | #define PCIE_LCSR2 0x30 /* Link Control & Status 2 Register */ |
1046 | #define PCIE_LCSR2_TGT_LSPEED __BITS(3, 0) /* Target Link Speed */ |
1047 | #define PCIE_LCSR2_ENT_COMPL __BIT(4) /* Enter Compliance */ |
1048 | #define PCIE_LCSR2_HW_AS_DIS __BIT(5) /* HW Autonomous Speed Disabl */ |
1049 | #define PCIE_LCSR2_SEL_DEEMP __BIT(6) /* Selectable De-emphasis */ |
1050 | #define PCIE_LCSR2_TX_MARGIN __BITS(9, 7) /* Transmit Margin */ |
1051 | #define PCIE_LCSR2_EN_MCOMP __BIT(10) /* Enter Modified Compliance */ |
1052 | #define PCIE_LCSR2_COMP_SOS __BIT(11) /* Compliance SOS */ |
1053 | #define PCIE_LCSR2_COMP_DEEMP __BITS(15, 12) /* Compliance Present/De-emph */ |
1054 | #define PCIE_LCSR2_DEEMP_LVL __BIT(0 + 16) /* Current De-emphasis Level */ |
1055 | #define PCIE_LCSR2_EQ_COMPL __BIT(1 + 16) /* Equalization Complete */ |
1056 | #define PCIE_LCSR2_EQP1_SUC __BIT(2 + 16) /* Equaliz Phase 1 Successful */ |
1057 | #define PCIE_LCSR2_EQP2_SUC __BIT(3 + 16) /* Equaliz Phase 2 Successful */ |
1058 | #define PCIE_LCSR2_EQP3_SUC __BIT(4 + 16) /* Equaliz Phase 3 Successful */ |
1059 | #define PCIE_LCSR2_LNKEQ_REQ __BIT(5 + 16) /* Link Equalization Request */ |
1060 | #define PCIE_LCSR2_RETIMERPD __BIT(6 + 16) /* Retimer Presence Detected */ |
1061 | #define PCIE_LCSR2_DSCOMPN __BITS(30, 28) /* Downstream Component Pres. */ |
1062 | #define PCIE_DSCOMPN_DOWN_NOTDETERM 0x00 /* LD: Presence Not Determin.*/ |
1063 | #define PCIE_DSCOMPN_DOWN_NOTPRES 0x01 /* LD: Component Not Present */ |
1064 | #define PCIE_DSCOMPN_DOWN_PRES 0x02 /* LD: Component Present */ |
1065 | /* 0x03 is reserved */ |
1066 | #define PCIE_DSCOMPN_UP_PRES 0x04 /* LU: Component Present */ |
1067 | #define PCIE_DSCOMPN_UP_PRES_DRS 0x05 /* LU: Comp Pres and DRS RCV */ |
1068 | #define PCIE_LCSR2_DRSRCV __BIT(15 + 16) /* DRS Message Received */ |
1069 | |
1070 | #define PCIE_SLCAP2 0x34 /* Slot Capabilities 2 Register */ |
1071 | #define PCIE_SLCSR2 0x38 /* Slot Control & Status 2 Register */ |
1072 | |
1073 | /* |
1074 | * Capability ID: 0x11 |
1075 | * MSIX |
1076 | */ |
1077 | |
1078 | #define PCI_MSIX_CTL 0x00 |
1079 | #define PCI_MSIX_CTL_ENABLE 0x80000000 |
1080 | #define PCI_MSIX_CTL_FUNCMASK 0x40000000 |
1081 | #define PCI_MSIX_CTL_TBLSIZE_MASK 0x07ff0000 |
1082 | #define PCI_MSIX_CTL_TBLSIZE_SHIFT 16 |
1083 | #define PCI_MSIX_CTL_TBLSIZE(ofs) ((((ofs) & PCI_MSIX_CTL_TBLSIZE_MASK) \ |
1084 | >> PCI_MSIX_CTL_TBLSIZE_SHIFT) + 1) |
1085 | /* |
1086 | * 2nd DWORD is the Table Offset |
1087 | */ |
1088 | #define PCI_MSIX_TBLOFFSET 0x04 |
1089 | #define PCI_MSIX_TBLOFFSET_MASK __BITS(31, 3) |
1090 | #define PCI_MSIX_TBLBIR_MASK __BITS(2, 0) |
1091 | /* |
1092 | * 3rd DWORD is the Pending Bitmap Array Offset |
1093 | */ |
1094 | #define PCI_MSIX_PBAOFFSET 0x08 |
1095 | #define PCI_MSIX_PBAOFFSET_MASK __BITS(31, 3) |
1096 | #define PCI_MSIX_PBABIR_MASK __BITS(2, 0) |
1097 | |
1098 | #define PCI_MSIX_TABLE_ENTRY_SIZE 16 |
1099 | #define PCI_MSIX_TABLE_ENTRY_ADDR_LO 0x0 |
1100 | #define PCI_MSIX_TABLE_ENTRY_ADDR_HI 0x4 |
1101 | #define PCI_MSIX_TABLE_ENTRY_DATA 0x8 |
1102 | #define PCI_MSIX_TABLE_ENTRY_VECTCTL 0xc |
1103 | struct pci_msix_table_entry { |
1104 | uint32_t pci_msix_addr_lo; |
1105 | uint32_t pci_msix_addr_hi; |
1106 | uint32_t pci_msix_value; |
1107 | uint32_t pci_msix_vector_control; |
1108 | }; |
1109 | #define PCI_MSIX_VECTCTL_MASK __BIT(0) |
1110 | #define PCI_MSIX_VECTCTL_STLO __BITS(23, 16) |
1111 | #define PCI_MSIX_VECTCTL_STUP __BITS(31, 24) |
1112 | |
1113 | /* Max number of MSI-X vectors. See PCI-SIG specification. */ |
1114 | #define PCI_MSIX_MAX_VECTORS 2048 |
1115 | |
1116 | /* |
1117 | * Capability ID: 0x12 |
1118 | * SATA |
1119 | */ |
1120 | #define PCI_SATA_REV 0x00 /* Revision Register */ |
1121 | #define PCI_SATA_REV_MINOR __BITS(19, 16) /* Minor Revision */ |
1122 | #define PCI_SATA_REV_MAJOR __BITS(23, 20) /* Major Revision */ |
1123 | #define PCI_SATA_BAR 0x04 /* BAR Register */ |
1124 | #define PCI_SATA_BAR_SPEC __BITS(3, 0) /* BAR Specifier */ |
1125 | #define PCI_SATA_BAR_INCONF __BITS(3, 0) /* All 1 = in config space */ |
1126 | #define PCI_SATA_BAR_NUM(x) (__SHIFTOUT((x), PCI_SATA_BAR_SPEC) - 4) |
1127 | #define PCI_SATA_BAR_OFFSET __BITS(23, 4) /* BAR Offset */ |
1128 | |
1129 | /* |
1130 | * Capability ID: 0x13 |
1131 | * Advanced Feature |
1132 | */ |
1133 | #define PCI_AFCAPR 0x00 /* Capabilities */ |
1134 | #define PCI_AFCAPR_MASK __BITS(31, 24) |
1135 | #define PCI_AF_LENGTH __BITS(23, 16) /* Structure Length */ |
1136 | #define PCI_AF_TP_CAP __BIT(24) /* Transaction Pending */ |
1137 | #define PCI_AF_FLR_CAP __BIT(25) /* Function Level Reset */ |
1138 | #define PCI_AFCSR 0x04 /* Control & Status register */ |
1139 | #define PCI_AFCR_INITIATE_FLR __BIT(0) /* Initiate Function LVL RST */ |
1140 | #define PCI_AFSR_TP __BIT(8) /* Transaction Pending */ |
1141 | |
1142 | |
1143 | /* |
1144 | * Interrupt Configuration Register; contains interrupt pin and line. |
1145 | */ |
1146 | #define PCI_INTERRUPT_REG 0x3c |
1147 | |
1148 | typedef u_int8_t pci_intr_latency_t; |
1149 | typedef u_int8_t pci_intr_grant_t; |
1150 | typedef u_int8_t pci_intr_pin_t; |
1151 | typedef u_int8_t pci_intr_line_t; |
1152 | |
1153 | #define PCI_MAX_LAT_SHIFT 24 |
1154 | #define PCI_MAX_LAT_MASK 0xff |
1155 | #define PCI_MAX_LAT(icr) \ |
1156 | (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) |
1157 | |
1158 | #define PCI_MIN_GNT_SHIFT 16 |
1159 | #define PCI_MIN_GNT_MASK 0xff |
1160 | #define PCI_MIN_GNT(icr) \ |
1161 | (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) |
1162 | |
1163 | #define PCI_INTERRUPT_GRANT_SHIFT 24 |
1164 | #define PCI_INTERRUPT_GRANT_MASK 0xff |
1165 | #define PCI_INTERRUPT_GRANT(icr) \ |
1166 | (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) |
1167 | |
1168 | #define PCI_INTERRUPT_LATENCY_SHIFT 16 |
1169 | #define PCI_INTERRUPT_LATENCY_MASK 0xff |
1170 | #define PCI_INTERRUPT_LATENCY(icr) \ |
1171 | (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) |
1172 | |
1173 | #define PCI_INTERRUPT_PIN_SHIFT 8 |
1174 | #define PCI_INTERRUPT_PIN_MASK 0xff |
1175 | #define PCI_INTERRUPT_PIN(icr) \ |
1176 | (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) |
1177 | |
1178 | #define PCI_INTERRUPT_LINE_SHIFT 0 |
1179 | #define PCI_INTERRUPT_LINE_MASK 0xff |
1180 | #define PCI_INTERRUPT_LINE(icr) \ |
1181 | (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) |
1182 | |
1183 | #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ |
1184 | ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ |
1185 | (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ |
1186 | (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ |
1187 | (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) |
1188 | |
1189 | #define PCI_INTERRUPT_PIN_NONE 0x00 |
1190 | #define PCI_INTERRUPT_PIN_A 0x01 |
1191 | #define PCI_INTERRUPT_PIN_B 0x02 |
1192 | #define PCI_INTERRUPT_PIN_C 0x03 |
1193 | #define PCI_INTERRUPT_PIN_D 0x04 |
1194 | #define PCI_INTERRUPT_PIN_MAX 0x04 |
1195 | |
1196 | /* Header Type 1 (Bridge) configuration registers */ |
1197 | #define PCI_BRIDGE_BUS_REG 0x18 |
1198 | #define PCI_BRIDGE_BUS_EACH_MASK 0xff |
1199 | #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 |
1200 | #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 |
1201 | #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 |
1202 | #define PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT 24 |
1203 | #define PCI_BRIDGE_BUS_PRIMARY(reg) \ |
1204 | (((reg) >> PCI_BRIDGE_BUS_PRIMARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK) |
1205 | #define PCI_BRIDGE_BUS_SECONDARY(reg) \ |
1206 | (((reg) >> PCI_BRIDGE_BUS_SECONDARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK) |
1207 | #define PCI_BRIDGE_BUS_SUBORDINATE(reg) \ |
1208 | (((reg) >> PCI_BRIDGE_BUS_SUBORDINATE_SHIFT) &PCI_BRIDGE_BUS_EACH_MASK) |
1209 | #define PCI_BRIDGE_BUS_SEC_LATTIMER(reg) \ |
1210 | (((reg) >> PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT)&PCI_BRIDGE_BUS_EACH_MASK) |
1211 | |
1212 | |
1213 | #define PCI_BRIDGE_STATIO_REG 0x1C |
1214 | #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 |
1215 | #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 |
1216 | #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 |
1217 | #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 |
1218 | #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 |
1219 | #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff |
1220 | #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) |
1221 | |
1222 | #define PCI_BRIDGE_MEMORY_REG 0x20 |
1223 | #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 |
1224 | #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 |
1225 | #define PCI_BRIDGE_MEMORY_BASE_MASK 0x0fff |
1226 | #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0x0fff |
1227 | |
1228 | #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 |
1229 | #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 |
1230 | #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 |
1231 | #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0x0fff |
1232 | #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0x0fff |
1233 | #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) |
1234 | |
1235 | #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 |
1236 | #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C |
1237 | |
1238 | #define PCI_BRIDGE_IOHIGH_REG 0x30 |
1239 | #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 |
1240 | #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 |
1241 | #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff |
1242 | #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff |
1243 | |
1244 | #define PCI_BRIDGE_CONTROL_REG 0x3C |
1245 | #define PCI_BRIDGE_CONTROL_SHIFT 16 |
1246 | #define PCI_BRIDGE_CONTROL_MASK 0xffff |
1247 | #define PCI_BRIDGE_CONTROL_PERE (1 << 0) |
1248 | #define PCI_BRIDGE_CONTROL_SERR (1 << 1) |
1249 | #define PCI_BRIDGE_CONTROL_ISA (1 << 2) |
1250 | #define PCI_BRIDGE_CONTROL_VGA (1 << 3) |
1251 | /* Reserved (1 << 4) */ |
1252 | #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) |
1253 | #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) |
1254 | #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) |
1255 | #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) |
1256 | #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) |
1257 | #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) |
1258 | #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) |
1259 | /* Reserved (1 << 12) - (1 << 15) */ |
1260 | |
1261 | /* |
1262 | * Vital Product Data resource tags. |
1263 | */ |
1264 | struct pci_vpd_smallres { |
1265 | uint8_t vpdres_byte0; /* length of data + tag */ |
1266 | /* Actual data. */ |
1267 | } __packed; |
1268 | |
1269 | struct pci_vpd_largeres { |
1270 | uint8_t vpdres_byte0; |
1271 | uint8_t vpdres_len_lsb; /* length of data only */ |
1272 | uint8_t vpdres_len_msb; |
1273 | /* Actual data. */ |
1274 | } __packed; |
1275 | |
1276 | #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) |
1277 | |
1278 | #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) |
1279 | #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) |
1280 | |
1281 | #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) |
1282 | |
1283 | #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ |
1284 | #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ |
1285 | #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ |
1286 | |
1287 | #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ |
1288 | #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ |
1289 | |
1290 | struct pci_vpd { |
1291 | uint8_t vpd_key0; |
1292 | uint8_t vpd_key1; |
1293 | uint8_t vpd_len; /* length of data only */ |
1294 | /* Actual data. */ |
1295 | } __packed; |
1296 | |
1297 | /* |
1298 | * Recommended VPD fields: |
1299 | * |
1300 | * PN Part number of assembly |
1301 | * FN FRU part number |
1302 | * EC EC level of assembly |
1303 | * MN Manufacture ID |
1304 | * SN Serial Number |
1305 | * |
1306 | * Conditionally recommended VPD fields: |
1307 | * |
1308 | * LI Load ID |
1309 | * RL ROM Level |
1310 | * RM Alterable ROM Level |
1311 | * NA Network Address |
1312 | * DD Device Driver Level |
1313 | * DG Diagnostic Level |
1314 | * LL Loadable Microcode Level |
1315 | * VI Vendor ID/Device ID |
1316 | * FU Function Number |
1317 | * SI Subsystem Vendor ID/Subsystem ID |
1318 | * |
1319 | * Additional VPD fields: |
1320 | * |
1321 | * Z0-ZZ User/Product Specific |
1322 | */ |
1323 | |
1324 | /* |
1325 | * PCI Expansion Rom |
1326 | */ |
1327 | |
1328 | struct { |
1329 | uint16_t ; /* 0xAA55 little endian */ |
1330 | uint8_t [22]; |
1331 | uint16_t ; /* pointer to pci_rom struct */ |
1332 | } __packed; |
1333 | |
1334 | #define 0xAA55 /* little endian */ |
1335 | |
1336 | struct pci_rom { |
1337 | uint32_t rom_signature; |
1338 | pci_vendor_id_t rom_vendor; |
1339 | pci_product_id_t rom_product; |
1340 | uint16_t rom_vpd_ptr; /* reserved in PCI 2.2 */ |
1341 | uint16_t rom_data_len; |
1342 | uint8_t rom_data_rev; |
1343 | pci_interface_t rom_interface; /* the class reg is 24-bits */ |
1344 | pci_subclass_t rom_subclass; /* in little endian */ |
1345 | pci_class_t rom_class; |
1346 | uint16_t rom_len; /* code length / 512 byte */ |
1347 | uint16_t rom_rev; /* code revision level */ |
1348 | uint8_t rom_code_type; /* type of code */ |
1349 | uint8_t rom_indicator; |
1350 | uint16_t rom_reserved; |
1351 | /* Actual data. */ |
1352 | } __packed; |
1353 | |
1354 | #define PCI_ROM_SIGNATURE 0x52494350 /* "PCIR", endian reversed */ |
1355 | #define PCI_ROM_CODE_TYPE_X86 0 /* Intel x86 BIOS */ |
1356 | #define PCI_ROM_CODE_TYPE_OFW 1 /* Open Firmware */ |
1357 | #define PCI_ROM_CODE_TYPE_HPPA 2 /* HP PA/RISC */ |
1358 | #define PCI_ROM_CODE_TYPE_EFI 3 /* EFI Image */ |
1359 | |
1360 | #define PCI_ROM_INDICATOR_LAST 0x80 |
1361 | |
1362 | /* |
1363 | * Threshold below which 32bit PCI DMA needs bouncing. |
1364 | */ |
1365 | #define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL |
1366 | |
1367 | /* |
1368 | * PCI-X 2.0/ PCI-express Extended Capability List |
1369 | */ |
1370 | |
1371 | #define PCI_EXTCAPLIST_BASE 0x100 |
1372 | |
1373 | #define PCI_EXTCAPLIST_CAP(ecr) ((ecr) & 0xffff) |
1374 | #define PCI_EXTCAPLIST_VERSION(ecr) (((ecr) >> 16) & 0xf) |
1375 | #define PCI_EXTCAPLIST_NEXT(ecr) (((ecr) >> 20) & 0xfff) |
1376 | |
1377 | /* Extended Capability Identification Numbers */ |
1378 | |
1379 | #define PCI_EXTCAP_AER 0x0001 /* Advanced Error Reporting */ |
1380 | #define PCI_EXTCAP_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ |
1381 | #define PCI_EXTCAP_SERNUM 0x0003 /* Device Serial Number */ |
1382 | #define PCI_EXTCAP_PWRBDGT 0x0004 /* Power Budgeting */ |
1383 | #define PCI_EXTCAP_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ |
1384 | #define PCI_EXTCAP_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ |
1385 | #define PCI_EXTCAP_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ |
1386 | #define PCI_EXTCAP_MFVC 0x0008 /* Multi-Function Virtual Channel */ |
1387 | #define PCI_EXTCAP_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ |
1388 | #define PCI_EXTCAP_RCRB 0x000a /* RCRB Header */ |
1389 | #define PCI_EXTCAP_VENDOR 0x000b /* Vendor Unique */ |
1390 | #define PCI_EXTCAP_CAC 0x000c /* Configuration Access Correction -- obsolete */ |
1391 | #define PCI_EXTCAP_ACS 0x000d /* Access Control Services */ |
1392 | #define PCI_EXTCAP_ARI 0x000e /* Alternative Routing-ID Interpretation */ |
1393 | #define PCI_EXTCAP_ATS 0x000f /* Address Translation Services */ |
1394 | #define PCI_EXTCAP_SRIOV 0x0010 /* Single Root IO Virtualization */ |
1395 | #define PCI_EXTCAP_MRIOV 0x0011 /* Multiple Root IO Virtualization */ |
1396 | #define PCI_EXTCAP_MCAST 0x0012 /* Multicast */ |
1397 | #define PCI_EXTCAP_PAGE_REQ 0x0013 /* Page Request */ |
1398 | #define PCI_EXTCAP_AMD 0x0014 /* Reserved for AMD */ |
1399 | #define PCI_EXTCAP_RESIZBAR 0x0015 /* Resizable BAR */ |
1400 | #define PCI_EXTCAP_DPA 0x0016 /* Dynamic Power Allocation */ |
1401 | #define PCI_EXTCAP_TPH_REQ 0x0017 /* TPH Requester */ |
1402 | #define PCI_EXTCAP_LTR 0x0018 /* Latency Tolerance Reporting */ |
1403 | #define PCI_EXTCAP_SEC_PCIE 0x0019 /* Secondary PCI Express */ |
1404 | #define PCI_EXTCAP_PMUX 0x001a /* Protocol Multiplexing */ |
1405 | #define PCI_EXTCAP_PASID 0x001b /* Process Address Space ID */ |
1406 | #define PCI_EXTCAP_LN_REQ 0x001c /* LN Requester */ |
1407 | #define PCI_EXTCAP_DPC 0x001d /* Downstream Port Containment */ |
1408 | #define PCI_EXTCAP_L1PM 0x001e /* L1 PM Substates */ |
1409 | #define PCI_EXTCAP_PTM 0x001f /* Precision Time Management */ |
1410 | #define PCI_EXTCAP_MPCIE 0x0020 /* M-PCIe */ |
1411 | #define PCI_EXTCAP_FRSQ 0x0021 /* Function Reading Status Queueing */ |
1412 | #define PCI_EXTCAP_RTR 0x0022 /* Readiness Time Reporting */ |
1413 | #define PCI_EXTCAP_DESIGVNDSP 0x0023 /* Designated Vendor-Specific */ |
1414 | #define PCI_EXTCAP_VF_RESIZBAR 0x0024 /* VF Resizable BAR */ |
1415 | |
1416 | /* |
1417 | * Extended capability ID: 0x0001 |
1418 | * Advanced Error Reporting |
1419 | */ |
1420 | #define PCI_AER_UC_STATUS 0x04 /* Uncorrectable Error Status Reg. */ |
1421 | #define PCI_AER_UC_UNDEFINED __BIT(0) |
1422 | #define PCI_AER_UC_DL_PROTOCOL_ERROR __BIT(4) |
1423 | #define PCI_AER_UC_SURPRISE_DOWN_ERROR __BIT(5) |
1424 | #define PCI_AER_UC_POISONED_TLP __BIT(12) |
1425 | #define PCI_AER_UC_FC_PROTOCOL_ERROR __BIT(13) |
1426 | #define PCI_AER_UC_COMPLETION_TIMEOUT __BIT(14) |
1427 | #define PCI_AER_UC_COMPLETER_ABORT __BIT(15) |
1428 | #define PCI_AER_UC_UNEXPECTED_COMPLETION __BIT(16) |
1429 | #define PCI_AER_UC_RECEIVER_OVERFLOW __BIT(17) |
1430 | #define PCI_AER_UC_MALFORMED_TLP __BIT(18) |
1431 | #define PCI_AER_UC_ECRC_ERROR __BIT(19) |
1432 | #define PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR __BIT(20) |
1433 | #define PCI_AER_UC_ACS_VIOLATION __BIT(21) |
1434 | #define PCI_AER_UC_INTERNAL_ERROR __BIT(22) |
1435 | #define PCI_AER_UC_MC_BLOCKED_TLP __BIT(23) |
1436 | #define PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED __BIT(24) |
1437 | #define PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR __BIT(25) |
1438 | #define PCI_AER_UC_POISONTLP_EGRESS_BLOCKED __BIT(26) |
1439 | #define PCI_AER_UC_MASK 0x08 /* Uncorrectable Error Mask Register */ |
1440 | /* Shares bits with UC_STATUS */ |
1441 | #define PCI_AER_UC_SEVERITY 0x0c /* Uncorrectable Error Severity Reg. */ |
1442 | /* Shares bits with UC_STATUS */ |
1443 | #define PCI_AER_COR_STATUS 0x10 /* Correctable Error Status Register */ |
1444 | #define PCI_AER_COR_RECEIVER_ERROR __BIT(0) |
1445 | #define PCI_AER_COR_BAD_TLP __BIT(6) |
1446 | #define PCI_AER_COR_BAD_DLLP __BIT(7) |
1447 | #define PCI_AER_COR_REPLAY_NUM_ROLLOVER __BIT(8) |
1448 | #define PCI_AER_COR_REPLAY_TIMER_TIMEOUT __BIT(12) |
1449 | #define PCI_AER_COR_ADVISORY_NF_ERROR __BIT(13) |
1450 | #define PCI_AER_COR_INTERNAL_ERROR __BIT(14) |
1451 | #define __BIT(15) |
1452 | #define PCI_AER_COR_MASK 0x14 /* Correctable Error Mask Register */ |
1453 | /* Shares bits with COR_STATUS */ |
1454 | #define PCI_AER_CAP_CONTROL 0x18 /* AE Capabilities and Control Reg. */ |
1455 | #define PCI_AER_FIRST_ERROR_PTR __BITS(4, 0) |
1456 | #define PCI_AER_FIRST_ERROR_PTR_S 0 |
1457 | #define PCI_AER_FIRST_ERROR_PTR_M 0x1f |
1458 | #define PCI_AER_ECRC_GEN_CAPABLE __BIT(5) |
1459 | #define PCI_AER_ECRC_GEN_ENABLE __BIT(6) |
1460 | #define PCI_AER_ECRC_CHECK_CAPABLE __BIT(7) |
1461 | #define PCI_AER_ECRC_CHECK_ENABLE __BIT(8) |
1462 | #define PCI_AER_MULT_HDR_CAPABLE __BIT(9) |
1463 | #define PCI_AER_MULT_HDR_ENABLE __BIT(10) |
1464 | #define PCI_AER_TLP_PREFIX_LOG_PRESENT __BIT(11) |
1465 | #define PCI_AER_COMPTOUTPRFXHDRLOG_CAP __BIT(12) |
1466 | #define 0x1c /* Header Log Register */ |
1467 | #define PCI_AER_ROOTERR_CMD 0x2c /* Root Error Command Register */ |
1468 | /* Only for root complex ports */ |
1469 | #define PCI_AER_ROOTERR_COR_ENABLE __BIT(0) |
1470 | #define PCI_AER_ROOTERR_NF_ENABLE __BIT(1) |
1471 | #define PCI_AER_ROOTERR_F_ENABLE __BIT(2) |
1472 | #define PCI_AER_ROOTERR_STATUS 0x30 /* Root Error Status Register */ |
1473 | /* Only for root complex ports */ |
1474 | #define PCI_AER_ROOTERR_COR_ERR __BIT(0) |
1475 | #define PCI_AER_ROOTERR_MULTI_COR_ERR __BIT(1) |
1476 | #define PCI_AER_ROOTERR_UC_ERR __BIT(2) |
1477 | #define PCI_AER_ROOTERR_MULTI_UC_ERR __BIT(3) |
1478 | #define PCI_AER_ROOTERR_FIRST_UC_FATAL __BIT(4) |
1479 | #define PCI_AER_ROOTERR_NF_ERR __BIT(5) |
1480 | #define PCI_AER_ROOTERR_F_ERR __BIT(6) |
1481 | #define PCI_AER_ROOTERR_INT_MESSAGE __BITS(31, 27) |
1482 | #define PCI_AER_ROOTERR_INT_MESSAGE_S 27 |
1483 | #define PCI_AER_ROOTERR_INT_MESSAGE_M 0x1f |
1484 | #define PCI_AER_ERRSRC_ID 0x34 /* Error Source Identification Reg. */ |
1485 | #define PCI_AER_ERRSRC_ID_ERR_COR __BITS(15, 0) |
1486 | #define PCI_AER_ERRSRC_ID_ERR_COR_S 0 |
1487 | #define PCI_AER_ERRSRC_ID_ERR_COR_M 0xffff |
1488 | #define PCI_AER_ERRSRC_ID_ERR_UC __BITS(31, 16) |
1489 | #define PCI_AER_ERRSRC_ID_ERR_UC_S 16 |
1490 | #define PCI_AER_ERRSRC_ID_ERR_UC_M 0xffff |
1491 | /* Only for root complex ports */ |
1492 | #define PCI_AER_TLP_PREFIX_LOG 0x38 /*TLP Prefix Log Register */ |
1493 | /* Only for TLP prefix functions */ |
1494 | |
1495 | /* |
1496 | * Extended capability ID: 0x0002, 0x0009 |
1497 | * Virtual Channel |
1498 | */ |
1499 | #define PCI_VC_CAP1 0x04 /* Port VC Capability Register 1 */ |
1500 | #define PCI_VC_CAP1_EXT_COUNT __BITS(2, 0) |
1501 | #define PCI_VC_CAP1_EXT_COUNT_S 0 |
1502 | #define PCI_VC_CAP1_EXT_COUNT_M 0x7 |
1503 | #define PCI_VC_CAP1_LOWPRI_EXT_COUNT __BITS(6, 4) |
1504 | #define PCI_VC_CAP1_LOWPRI_EXT_COUNT_S 4 |
1505 | #define PCI_VC_CAP1_LOWPRI_EXT_COUNT_M 0x7 |
1506 | #define PCI_VC_CAP1_REFCLK __BITS(9, 8) |
1507 | #define PCI_VC_CAP1_REFCLK_S 8 |
1508 | #define PCI_VC_CAP1_REFCLK_M 0x3 |
1509 | #define PCI_VC_CAP1_REFCLK_100NS 0x0 |
1510 | #define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE __BITS(11, 10) |
1511 | #define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_S 10 |
1512 | #define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_M 0x3 |
1513 | #define PCI_VC_CAP2 0x08 /* Port VC Capability Register 2 */ |
1514 | #define PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME __BIT(0) |
1515 | #define PCI_VC_CAP2_ARB_CAP_WRR_32 __BIT(1) |
1516 | #define PCI_VC_CAP2_ARB_CAP_WRR_64 __BIT(2) |
1517 | #define PCI_VC_CAP2_ARB_CAP_WRR_128 __BIT(3) |
1518 | #define PCI_VC_CAP2_ARB_TABLE_OFFSET __BITS(31, 24) |
1519 | #define PCI_VC_CAP2_ARB_TABLE_OFFSET_S 24 |
1520 | #define PCI_VC_CAP2_ARB_TABLE_OFFSET_M 0xff |
1521 | #define PCI_VC_CONTROL 0x0c /* Port VC Control Register (16bit) */ |
1522 | #define PCI_VC_CONTROL_LOAD_VC_ARB_TABLE __BIT(0) |
1523 | #define PCI_VC_CONTROL_VC_ARB_SELECT __BITS(3, 1) |
1524 | #define PCI_VC_CONTROL_VC_ARB_SELECT_S 1 |
1525 | #define PCI_VC_CONTROL_VC_ARB_SELECT_M 0x7 |
1526 | #define PCI_VC_STATUS 0x0e /* Port VC Status Register (16bit) */ |
1527 | #define PCI_VC_STATUS_LOAD_VC_ARB_TABLE __BIT(0) |
1528 | #define PCI_VC_RESOURCE_CAP(n) (0x10 + ((n) * 0x0c)) /* VC Resource Capability Register */ |
1529 | #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME __BIT(0) |
1530 | #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32 __BIT(1) |
1531 | #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64 __BIT(2) |
1532 | #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128 __BIT(3) |
1533 | #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128 __BIT(4) |
1534 | #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256 __BIT(5) |
1535 | #define PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH __BIT(14) |
1536 | #define PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS __BIT(15) |
1537 | #define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS __BITS(22, 16) |
1538 | #define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_S 16 |
1539 | #define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_M 0x7f |
1540 | #define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET __BITS(31, 24) |
1541 | #define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S 24 |
1542 | #define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_M 0xff |
1543 | #define PCI_VC_RESOURCE_CTL(n) (0x14 + ((n) * 0x0c)) /* VC Resource Control Register */ |
1544 | #define PCI_VC_RESOURCE_CTL_TCVC_MAP __BITS(7, 0) |
1545 | #define PCI_VC_RESOURCE_CTL_TCVC_MAP_S 0 |
1546 | #define PCI_VC_RESOURCE_CTL_TCVC_MAP_M 0xff |
1547 | #define PCI_VC_RESOURCE_CTL_LOAD_PORT_ARB_TABLE __BIT(16) |
1548 | #define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT __BITS(19, 17) |
1549 | #define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_S 17 |
1550 | #define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_M 0x7 |
1551 | #define PCI_VC_RESOURCE_CTL_VC_ID __BITS(26, 24) |
1552 | #define PCI_VC_RESOURCE_CTL_VC_ID_S 24 |
1553 | #define PCI_VC_RESOURCE_CTL_VC_ID_M 0x7 |
1554 | #define PCI_VC_RESOURCE_CTL_VC_ENABLE __BIT(31) |
1555 | #define PCI_VC_RESOURCE_STA(n) (0x18 + ((n) * 0x0c)) /* VC Resource Status Register */ |
1556 | #define PCI_VC_RESOURCE_STA_PORT_ARB_TABLE __BIT(0) |
1557 | #define PCI_VC_RESOURCE_STA_VC_NEG_PENDING __BIT(1) |
1558 | |
1559 | /* |
1560 | * Extended capability ID: 0x0003 |
1561 | * Serial Number |
1562 | */ |
1563 | #define PCI_SERIAL_LOW 0x04 |
1564 | #define PCI_SERIAL_HIGH 0x08 |
1565 | |
1566 | /* |
1567 | * Extended capability ID: 0x0004 |
1568 | * Power Budgeting |
1569 | */ |
1570 | #define PCI_PWRBDGT_DSEL 0x04 /* Data Select */ |
1571 | #define PCI_PWRBDGT_DATA 0x08 /* Data */ |
1572 | #define PCI_PWRBDGT_DATA_BASEPWR __BITS(7, 0) /* Base Power */ |
1573 | #define PCI_PWRBDGT_DATA_SCALE __BITS(9, 8) /* Data Scale */ |
1574 | #define PCI_PWRBDGT_PM_SUBSTAT __BITS(12, 10) /* PM Sub State */ |
1575 | #define PCI_PWRBDGT_PM_STAT __BITS(14, 13) /* PM State */ |
1576 | #define PCI_PWRBDGT_TYPE __BITS(17, 15) /* Type */ |
1577 | #define PCI_PWRBDGT_PWRRAIL __BITS(20, 18) /* Power Rail */ |
1578 | #define PCI_PWRBDGT_CAP 0x0c /* Capability */ |
1579 | #define PCI_PWRBDGT_CAP_SYSALLOC __BIT(0) /* System Allocated */ |
1580 | |
1581 | /* |
1582 | * Extended capability ID: 0x0005 |
1583 | * Root Complex Link Declaration |
1584 | */ |
1585 | #define PCI_RCLINK_DCL_ESDESC 0x04 /* Element Self Description */ |
1586 | #define PCI_RCLINK_DCL_ESDESC_ELMTYPE __BITS(3, 0) /* Element Type */ |
1587 | #define PCI_RCLINK_DCL_ESDESC_NUMLINKENT __BITS(15, 8) /* Num of Link Entries*/ |
1588 | #define PCI_RCLINK_DCL_ESDESC_COMPID __BITS(23, 16) /* Component ID */ |
1589 | #define PCI_RCLINK_DCL_ESDESC_PORTNUM __BITS(31, 24) /* Port Number */ |
1590 | #define PCI_RCLINK_DCL_LINKENTS 0x10 /* Link Entries */ |
1591 | #define PCI_RCLINK_DCL_LINKDESC(x) /* Link Description */ \ |
1592 | (PCI_RCLINK_DCL_LINKENTS + ((x) * 16)) |
1593 | #define PCI_RCLINK_DCL_LINKDESC_LVALID __BIT(0) /* Link Valid */ |
1594 | #define PCI_RCLINK_DCL_LINKDESC_LTYPE __BIT(1) /* Link Type */ |
1595 | #define PCI_RCLINK_DCL_LINKDESC_ARCRBH __BIT(2) /* Associate RCRB Header */ |
1596 | #define PCI_RCLINK_DCL_LINKDESC_TCOMPID __BITS(23, 16) /* Target Component ID*/ |
1597 | #define PCI_RCLINK_DCL_LINKDESC_TPNUM __BITS(31, 24) /* Target Port Number */ |
1598 | #define PCI_RCLINK_DCL_LINKADDR_LT0_LO(x) /* LT0: Link Address Low */ \ |
1599 | (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x08) |
1600 | #define PCI_RCLINK_DCL_LINKADDR_LT0_HI(x) /* LT0: Link Address High */ \ |
1601 | (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x0c) |
1602 | #define PCI_RCLINK_DCL_LINKADDR_LT1_LO(x) /* LT1: Config Space (low) */ \ |
1603 | (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x08) |
1604 | #define PCI_RCLINK_DCL_LINKADDR_LT1_N __BITS(2, 0) /* N */ |
1605 | #define PCI_RCLINK_DCL_LINKADDR_LT1_FUNC __BITS(14, 12) /* Function Number */ |
1606 | #define PCI_RCLINK_DCL_LINKADDR_LT1_DEV __BITS(19, 15) /* Device Number */ |
1607 | #define PCI_RCLINK_DCL_LINKADDR_LT1_BUS(N) __BITS(19 + (N), 20) /* Bus Number*/ |
1608 | #define PCI_RCLINK_DCL_LINKADDR_LT1_BAL(N) __BITS(31, 20 + (N)) /* BAddr(L) */ |
1609 | #define PCI_RCLINK_DCL_LINKADDR_LT1_HI(x) /* LT1: Config Space Base Addr(H) */\ |
1610 | (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x0c) |
1611 | |
1612 | /* |
1613 | * Extended capability ID: 0x0006 |
1614 | * Root Complex Internal Link Control |
1615 | */ |
1616 | |
1617 | /* |
1618 | * Extended capability ID: 0x0007 |
1619 | * Root Complex Event Collector Association |
1620 | */ |
1621 | #define PCI_RCEC_ASSOC_ASSOCBITMAP 0x04 |
1622 | |
1623 | /* |
1624 | * Extended capability ID: 0x0008 |
1625 | * Multi-Function Virtual Channel |
1626 | */ |
1627 | |
1628 | /* |
1629 | * Extended capability ID: 0x0009 |
1630 | * Virtual Channel if MFVC Ext Cap set |
1631 | */ |
1632 | |
1633 | /* |
1634 | * Extended capability ID: 0x000a |
1635 | * RCRB Header |
1636 | */ |
1637 | |
1638 | /* |
1639 | * Extended capability ID: 0x000b |
1640 | * Vendor Unique |
1641 | */ |
1642 | |
1643 | /* |
1644 | * Extended capability ID: 0x000c |
1645 | * Configuration Access Correction |
1646 | */ |
1647 | |
1648 | /* |
1649 | * Extended capability ID: 0x000d |
1650 | * Access Control Services |
1651 | */ |
1652 | #define PCI_ACS_CAP 0x04 /* Capability Register */ |
1653 | #define PCI_ACS_CAP_V __BIT(0) /* Source Validation */ |
1654 | #define PCI_ACS_CAP_B __BIT(1) /* Transaction Blocking */ |
1655 | #define PCI_ACS_CAP_R __BIT(2) /* P2P Request Redirect */ |
1656 | #define PCI_ACS_CAP_C __BIT(3) /* P2P Completion Redirect */ |
1657 | #define PCI_ACS_CAP_U __BIT(4) /* Upstream Forwarding */ |
1658 | #define PCI_ACS_CAP_E __BIT(5) /* Egress Control */ |
1659 | #define PCI_ACS_CAP_T __BIT(6) /* Direct Translated P2P */ |
1660 | #define PCI_ACS_CAP_ECVSIZE __BITS(15, 8) /* Egress Control Vector Size */ |
1661 | #define PCI_ACS_CTL 0x04 /* Control Register */ |
1662 | #define PCI_ACS_CTL_V __BIT(0 + 16) /* Source Validation Enable */ |
1663 | #define PCI_ACS_CTL_B __BIT(1 + 16) /* Transaction Blocking Enable */ |
1664 | #define PCI_ACS_CTL_R __BIT(2 + 16) /* P2P Request Redirect Enable */ |
1665 | #define PCI_ACS_CTL_C __BIT(3 + 16) /* P2P Completion Redirect Enable */ |
1666 | #define PCI_ACS_CTL_U __BIT(4 + 16) /* Upstream Forwarding Enable */ |
1667 | #define PCI_ACS_CTL_E __BIT(5 + 16) /* Egress Control Enable */ |
1668 | #define PCI_ACS_CTL_T __BIT(6 + 16) /* Direct Translated P2P Enable */ |
1669 | #define PCI_ACS_ECV 0x08 /* Egress Control Vector */ |
1670 | |
1671 | /* |
1672 | * Extended capability ID: 0x000e |
1673 | * ARI |
1674 | */ |
1675 | #define PCI_ARI_CAP 0x04 /* Capability Register */ |
1676 | #define PCI_ARI_CAP_M __BIT(0) /* MFVC Function Groups Cap. */ |
1677 | #define PCI_ARI_CAP_A __BIT(1) /* ACS Function Groups Cap. */ |
1678 | #define PCI_ARI_CAP_NXTFN __BITS(15, 8) /* Next Function Number */ |
1679 | #define PCI_ARI_CTL 0x04 /* Control Register */ |
1680 | #define PCI_ARI_CTL_M __BIT(16) /* MFVC Function Groups Ena. */ |
1681 | #define PCI_ARI_CTL_A __BIT(17) /* ACS Function Groups Ena. */ |
1682 | #define PCI_ARI_CTL_FUNCGRP __BITS(22, 20) /* Function Group */ |
1683 | |
1684 | /* |
1685 | * Extended capability ID: 0x000f |
1686 | * Address Translation Services |
1687 | */ |
1688 | #define PCI_ATS_CAP 0x04 /* Capability Register */ |
1689 | #define PCI_ATS_CAP_INVQDEPTH __BITS(4, 0) /* Invalidate Queue Depth */ |
1690 | #define PCI_ATS_CAP_PALIGNREQ __BIT(5) /* Page Aligned Request */ |
1691 | #define PCI_ATS_CAP_GLOBALINVL __BIT(6) /* Global Invalidate Support */ |
1692 | #define PCI_ATS_CTL 0x04 /* Control Register */ |
1693 | #define PCI_ATS_CTL_STU __BITS(20, 16) /* Smallest Translation Unit */ |
1694 | #define PCI_ATS_CTL_EN __BIT(31) /* Enable */ |
1695 | |
1696 | /* |
1697 | * Extended capability ID: 0x0010 |
1698 | * SR-IOV |
1699 | */ |
1700 | #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ |
1701 | #define PCI_SRIOV_CAP_VF_MIGRATION __BIT(0) |
1702 | #define PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED __BIT(1) |
1703 | #define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N __BITS(31, 21) |
1704 | #define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_S 21 |
1705 | #define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_M 0x7ff |
1706 | #define PCI_SRIOV_CTL 0x08 /* SR-IOV Control (16bit) */ |
1707 | #define PCI_SRIOV_CTL_VF_ENABLE __BIT(0) |
1708 | #define PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT __BIT(1) |
1709 | #define PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE __BIT(2) |
1710 | #define PCI_SRIOV_CTL_VF_MSE __BIT(3) |
1711 | #define PCI_SRIOV_CTL_ARI_CAP_HIER __BIT(4) |
1712 | #define PCI_SRIOV_STA 0x0a /* SR-IOV Status (16bit) */ |
1713 | #define PCI_SRIOV_STA_VF_MIGRATION __BIT(0) |
1714 | #define PCI_SRIOV_INITIAL_VFS 0x0c /* InitialVFs (16bit) */ |
1715 | #define PCI_SRIOV_TOTAL_VFS 0x0e /* TotalVFs (16bit) */ |
1716 | #define PCI_SRIOV_NUM_VFS 0x10 /* NumVFs (16bit) */ |
1717 | #define PCI_SRIOV_FUNC_DEP_LINK 0x12 /* Function Dependency Link (16bit) */ |
1718 | #define PCI_SRIOV_VF_OFF 0x14 /* First VF Offset (16bit) */ |
1719 | #define PCI_SRIOV_VF_STRIDE 0x16 /* VF Stride (16bit) */ |
1720 | #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID (16bit) */ |
1721 | #define PCI_SRIOV_PAGE_CAP 0x1c /* Supported Page Sizes */ |
1722 | #define PCI_SRIOV_PAGE_SIZE 0x20 /* System Page Size */ |
1723 | #define PCI_SRIOV_BASE_PAGE_SHIFT 12 |
1724 | #define PCI_SRIOV_BARS 0x24 /* VF BAR0-5 */ |
1725 | #define PCI_SRIOV_BAR(x) (PCI_SRIOV_BARS + ((x) * 4)) |
1726 | #define PCI_SRIOV_VF_MIG_STA_AR 0x3c /* VF Migration State Array Offset */ |
1727 | #define PCI_SRIOV_VF_MIG_STA_OFFSET __BITS(31, 3) |
1728 | #define PCI_SRIOV_VF_MIG_STA_OFFSET_S 3 |
1729 | #define PCI_SRIOV_VF_MIG_STA_OFFSET_M 0x1fffffff |
1730 | #define PCI_SRIOV_VF_MIG_STA_BIR __BITS(2, 0) |
1731 | #define PCI_SRIOV_VF_MIG_STA_BIR_S 0 |
1732 | #define PCI_SRIOV_VF_MIG_STA_BIR_M 0x7 |
1733 | |
1734 | /* |
1735 | * Extended capability ID: 0x0011 |
1736 | * Multiple Root IO Virtualization |
1737 | */ |
1738 | |
1739 | /* |
1740 | * Extended capability ID: 0x0012 |
1741 | * Multicast |
1742 | */ |
1743 | #define PCI_MCAST_CAP 0x04 /* Capability Register */ |
1744 | #define PCI_MCAST_CAP_MAXGRP __BITS(5, 0) /* Max Group */ |
1745 | #define PCI_MCAST_CAP_WINSIZEREQ __BITS(13, 8) /* Window Size Requested */ |
1746 | #define PCI_MCAST_CAP_ECRCREGEN __BIT(15) /* ECRC Regen. Supported */ |
1747 | #define PCI_MCAST_CTL 0x04 /* Control Register */ |
1748 | #define PCI_MCAST_CTL_NUMGRP __BITS(5+16, 16) /* Num Group */ |
1749 | #define PCI_MCAST_CTL_ENA __BIT(15+16) /* Enable */ |
1750 | #define PCI_MCAST_BARL 0x08 /* Base Address Register (low) */ |
1751 | #define PCI_MCAST_BARL_INDPOS __BITS(5, 0) /* Index Position */ |
1752 | #define PCI_MCAST_BARL_ADDR __BITS(31, 12) /* Base Address Register(low)*/ |
1753 | #define PCI_MCAST_BARH 0x0c /* Base Address Register (high) */ |
1754 | #define PCI_MCAST_RECVL 0x10 /* Receive Register (low) */ |
1755 | #define PCI_MCAST_RECVH 0x14 /* Receive Register (high) */ |
1756 | #define PCI_MCAST_BLOCKALLL 0x18 /* Block All Register (low) */ |
1757 | #define PCI_MCAST_BLOCKALLH 0x1c /* Block All Register (high) */ |
1758 | #define PCI_MCAST_BLOCKUNTRNSL 0x20 /* Block Untranslated Register (low) */ |
1759 | #define PCI_MCAST_BLOCKUNTRNSH 0x24 /* Block Untranslated Register (high) */ |
1760 | #define PCI_MCAST_OVERLAYL 0x28 /* Overlay BAR (low) */ |
1761 | #define PCI_MCAST_OVERLAYL_SIZE __BITS(5, 0) /* Overlay Size */ |
1762 | #define PCI_MCAST_OVERLAYL_ADDR __BITS(31, 6) /* Overlay BAR (low) */ |
1763 | #define PCI_MCAST_OVERLAYH 0x2c /* Overlay BAR (high) */ |
1764 | |
1765 | /* |
1766 | * Extended capability ID: 0x0013 |
1767 | * Page Request |
1768 | */ |
1769 | #define PCI_PAGE_REQ_CTL 0x04 /* Control Register */ |
1770 | #define PCI_PAGE_REQ_CTL_E __BIT(0) /* Enalbe */ |
1771 | #define PCI_PAGE_REQ_CTL_R __BIT(1) /* Reset */ |
1772 | #define PCI_PAGE_REQ_STA 0x04 /* Status Register */ |
1773 | #define PCI_PAGE_REQ_STA_RF __BIT(0+16) /* Response Failure */ |
1774 | #define PCI_PAGE_REQ_STA_UPRGI __BIT(1+16) /* Unexpected Page Req Grp Idx */ |
1775 | #define PCI_PAGE_REQ_STA_S __BIT(8+16) /* Stopped */ |
1776 | #define PCI_PAGE_REQ_STA_PASIDR __BIT(15+16) /* PRG Response PASID Required */ |
1777 | #define PCI_PAGE_REQ_OUTSTCAPA 0x08 /* Outstanding Page Request Capacity */ |
1778 | #define PCI_PAGE_REQ_OUTSTALLOC 0x0c /* Outstanding Page Request Allocation */ |
1779 | |
1780 | /* |
1781 | * Extended capability ID: 0x0014 |
1782 | * (Reserved for AMD) |
1783 | */ |
1784 | |
1785 | /* |
1786 | * Extended capability ID: 0x0015 |
1787 | * Resizable BAR |
1788 | */ |
1789 | #define PCI_RESIZBAR_CAP0 0x04 /* Capability Register(0) */ |
1790 | #define PCI_RESIZBAR_CAP(x) (PCI_RESIZBAR_CAP0 + ((x) * 8)) |
1791 | #define PCI_RESIZBAR_CAP_SIZEMASK __BITS(23, 4) /* BAR size bitmask */ |
1792 | #define PCI_RESIZBAR_CTL0 0x08 /* Control Register(0) */ |
1793 | #define PCI_RESIZBAR_CTL(x) (PCI_RESIZBAR_CTL0 + ((x) * 8)) |
1794 | #define PCI_RESIZBAR_CTL_BARIDX __BITS(2, 0) |
1795 | #define PCI_RESIZBAR_CTL_NUMBAR __BITS(7, 5) |
1796 | #define PCI_RESIZBAR_CTL_BARSIZ __BITS(12, 8) |
1797 | |
1798 | /* |
1799 | * Extended capability ID: 0x0016 |
1800 | * Dynamic Power Allocation |
1801 | */ |
1802 | #define PCI_DPA_CAP 0x04 /* Capability */ |
1803 | #define PCI_DPA_CAP_SUBSTMAX __BITS(4, 0) /* Substate Max */ |
1804 | #define PCI_DPA_CAP_TLUINT __BITS(9, 8) /* Transition Latency Unit */ |
1805 | #define PCI_DPA_CAP_PAS __BITS(13, 12) /* Power Allocation Scale */ |
1806 | #define PCI_DPA_CAP_XLCY0 __BITS(23, 16) /* Transition Latency Value0 */ |
1807 | #define PCI_DPA_CAP_XLCY1 __BITS(31, 24) /* Transition Latency Value1 */ |
1808 | #define PCI_DPA_LATIND 0x08 /* Latency Indicator */ |
1809 | #define PCI_DPA_CS 0x0c /* Control and Status */ |
1810 | #define PCI_DPA_CS_SUBSTSTAT __BITS(4, 0) /* Substate Status */ |
1811 | #define PCI_DPA_CS_SUBSTCTLEN __BIT(8) /* Substate Control Enabled */ |
1812 | #define PCI_DPA_CS_SUBSTCTL __BITS(20, 16) /* Substate Control */ |
1813 | #define PCI_DPA_PWRALLOC 0x10 /* Start address of Power Allocation Array */ |
1814 | #define PCI_DPA_SUBST_MAXNUM 32 /* Max number of Substates (0 to 31) */ |
1815 | |
1816 | /* |
1817 | * Extended capability ID: 0x0017 |
1818 | * TPH Requester |
1819 | */ |
1820 | #define PCI_TPH_REQ_CAP 0x04 /* TPH Requester Capability */ |
1821 | #define PCI_TPH_REQ_CAP_NOST __BIT(0) /* No ST Mode Supported */ |
1822 | #define PCI_TPH_REQ_CAP_INTVEC __BIT(1) /* Intr Vec Mode Supported */ |
1823 | #define PCI_TPH_REQ_CAP_DEVSPEC __BIT(2) /* Device Specific Mode Supported */ |
1824 | #define PCI_TPH_REQ_CAP_XTPHREQ __BIT(8) /* Extend TPH Reqester Supported */ |
1825 | #define PCI_TPH_REQ_CAP_STTBLLOC __BITS(10, 9) /* ST Table Location */ |
1826 | #define PCI_TPH_REQ_CAP_STTBLSIZ __BITS(26, 16) /* ST Table Size */ |
1827 | #define PCI_TPH_REQ_CTL 0x08 /* TPH Requester Control */ |
1828 | #define PCI_TPH_REQ_CTL_STSEL _BITS(2, 0) /* ST Mode Select */ |
1829 | #define PCI_TPH_REQ_CTL_TPHREQEN _BITS(9, 8) /* TPH Requester Enable */ |
1830 | #define PCI_TPH_REQ_STTBL 0x0c /* TPH ST Table */ |
1831 | |
1832 | /* |
1833 | * Extended capability ID: 0x0018 |
1834 | * Latency Tolerance Reporting |
1835 | */ |
1836 | #define PCI_LTR_MAXSNOOPLAT 0x04 /* Max Snoop Latency */ |
1837 | #define PCI_LTR_MAXSNOOPLAT_VAL __BITS(9, 0) /* Max Snoop LatencyValue */ |
1838 | #define PCI_LTR_MAXSNOOPLAT_SCALE __BITS(12, 10) /* Max Snoop LatencyScale */ |
1839 | #define PCI_LTR_MAXNOSNOOPLAT 0x04 /* Max No-Snoop Latency */ |
1840 | #define PCI_LTR_MAXNOSNOOPLAT_VAL __BITS(25, 16) /* Max No-Snoop LatencyValue*/ |
1841 | #define PCI_LTR_MAXNOSNOOPLAT_SCALE __BITS(28, 26) /*Max NoSnoop LatencyScale*/ |
1842 | #define PCI_LTR_SCALETONS(x) ((32 << (x)) / 32) |
1843 | |
1844 | /* |
1845 | * Extended capability ID: 0x0019 |
1846 | * Seconday PCI Express Extended Capability |
1847 | */ |
1848 | #define PCI_SECPCIE_LCTL3 0x04 /* Link Control 3 */ |
1849 | #define PCI_SECPCIE_LCTL3_PERFEQ __BIT(0) /* Perform Equalization */ |
1850 | #define PCI_SECPCIE_LCTL3_LINKEQREQ_IE __BIT(1) /* Link Eq. Req. Int. Ena. */ |
1851 | #define PCI_SECPCIE_LCTL3_ELSKPOSGENV __BITS(15, 9) /* En. Lo. SKP OS Gen V*/ |
1852 | #define PCI_SECPCIE_LANEERR_STA 0x08 /* Lane Error Status */ |
1853 | #define PCI_SECPCIE_EQCTLS 0x0c /* Equalization Control [0-maxlane] */ |
1854 | #define PCI_SECPCIE_EQCTL(x) (PCI_SECPCIE_EQCTLS + ((x) * 2)) |
1855 | #define PCI_SECPCIE_EQCTL_DP_XMIT_PRESET __BITS(3, 0) /* DwnStPort Xmit Pres */ |
1856 | #define PCI_SECPCIE_EQCTL_DP_RCV_HINT __BITS(6, 4) /* DwnStPort Rcv PreHnt */ |
1857 | #define PCI_SECPCIE_EQCTL_UP_XMIT_PRESET __BITS(11, 8) /* UpStPort Xmit Pres */ |
1858 | #define PCI_SECPCIE_EQCTL_UP_RCV_HINT __BITS(14, 12) /* UpStPort Rcv PreHnt*/ |
1859 | |
1860 | /* |
1861 | * Extended capability ID: 0x001a |
1862 | * Protocol Multiplexing |
1863 | */ |
1864 | |
1865 | /* |
1866 | * Extended capability ID: 0x001b |
1867 | * Process Address Space ID |
1868 | */ |
1869 | #define PCI_PASID_CAP 0x04 /* Capability Register */ |
1870 | #define PCI_PASID_CAP_XPERM __BIT(1) /* Execute Permission Supported */ |
1871 | #define PCI_PASID_CAP_PRIVMODE __BIT(2) /* Privileged Mode Supported */ |
1872 | #define PCI_PASID_CAP_MAXPASIDW __BITS(12, 8) /* Max PASID Width */ |
1873 | #define PCI_PASID_CTL 0x04 /* Control Register */ |
1874 | #define PCI_PASID_CTL_PASID_EN __BIT(0) /* PASID Enable */ |
1875 | #define PCI_PASID_CTL_XPERM_EN __BIT(1) /* Execute Permission Enable */ |
1876 | #define PCI_PASID_CTL_PRIVMODE_EN __BIT(2) /* Privileged Mode Enable */ |
1877 | |
1878 | /* |
1879 | * Extended capability ID: 0x001c |
1880 | * LN Requester |
1881 | */ |
1882 | #define PCI_LNR_CAP 0x04 /* Capability Register */ |
1883 | #define PCI_LNR_CAP_64 __BIT(0) /* LNR-64 Supported */ |
1884 | #define PCI_LNR_CAP_128 __BIT(1) /* LNR-128 Supported */ |
1885 | #define PCI_LNR_CAP_REGISTMAX __BITS(12, 8) /* LNR Registration MAX */ |
1886 | #define PCI_LNR_CTL 0x04 /* Control Register */ |
1887 | #define PCI_LNR_CTL_EN __BIT(0+16) /* LNR Enable */ |
1888 | #define PCI_LNR_CTL_CLS __BIT(1+16) /* LNR CLS */ |
1889 | #define PCI_LNR_CTL_REGISTLIM __BITS(28, 24) /* LNR Registration Limit */ |
1890 | |
1891 | /* |
1892 | * Extended capability ID: 0x001d |
1893 | * Downstream Port Containment |
1894 | */ |
1895 | |
1896 | /* |
1897 | * Extended capability ID: 0x001e |
1898 | * L1 PM Substates |
1899 | */ |
1900 | #define PCI_L1PM_CAP 0x04 /* Capabilities Register */ |
1901 | #define PCI_L1PM_CAP_PCIPM12 __BIT(0) /* PCI-PM L1.2 Supported */ |
1902 | #define PCI_L1PM_CAP_PCIPM11 __BIT(1) /* PCI-PM L1.1 Supported */ |
1903 | #define PCI_L1PM_CAP_ASPM12 __BIT(2) /* ASPM L1.2 Supported */ |
1904 | #define PCI_L1PM_CAP_ASPM11 __BIT(3) /* ASPM L1.1 Supported */ |
1905 | #define PCI_L1PM_CAP_L1PM __BIT(4) /* L1 PM Substates Supported */ |
1906 | #define PCI_L1PM_CAP_PCMRT __BITS(15, 8) /*Port Common Mode Restore Time*/ |
1907 | #define PCI_L1PM_CAP_PTPOSCALE __BITS(17, 16) /* Port T_POWER_ON Scale */ |
1908 | #define PCI_L1PM_CAP_PTPOVAL __BITS(23, 19) /* Port T_POWER_ON Value */ |
1909 | #define PCI_L1PM_CTL1 0x08 /* Control Register 1 */ |
1910 | #define PCI_L1PM_CTL1_PCIPM12_EN __BIT(0) /* PCI-PM L1.2 Enable */ |
1911 | #define PCI_L1PM_CTL1_PCIPM11_EN __BIT(1) /* PCI-PM L1.1 Enable */ |
1912 | #define PCI_L1PM_CTL1_ASPM12_EN __BIT(2) /* ASPM L1.2 Enable */ |
1913 | #define PCI_L1PM_CTL1_ASPM11_EN __BIT(3) /* ASPM L1.1 Enable */ |
1914 | #define PCI_L1PM_CTL1_CMRT __BITS(15, 8) /* Common Mode Restore Time */ |
1915 | #define PCI_L1PM_CTL1_LTRTHVAL __BITS(25, 16) /* LTR L1.2 THRESHOLD Value */ |
1916 | #define PCI_L1PM_CTL1_LTRTHSCALE __BITS(31, 29) /* LTR L1.2 THRESHOLD Scale */ |
1917 | #define PCI_L1PM_CTL2 0x0c /* Control Register 2 */ |
1918 | #define PCI_L1PM_CTL2_TPOSCALE __BITS(1, 0) /* T_POWER_ON Scale */ |
1919 | #define PCI_L1PM_CTL2_TPOVAL __BITS(7, 3) /* T_POWER_ON Value */ |
1920 | |
1921 | /* |
1922 | * Extended capability ID: 0x001f |
1923 | * Precision Time Management |
1924 | */ |
1925 | #define PCI_PTM_CAP 0x04 /* Capabilities Register */ |
1926 | #define PCI_PTM_CAP_REQ __BIT(0) /* PTM Requester Capable */ |
1927 | #define PCI_PTM_CAP_RESP __BIT(1) /* PTM Responder Capable */ |
1928 | #define PCI_PTM_CAP_ROOT __BIT(2) /* PTM Root Capable */ |
1929 | #define PCI_PTM_CAP_LCLCLKGRNL __BITS(15, 8) /* Local Clock Granularity */ |
1930 | #define PCI_PTM_CTL 0x08 /* Control Register */ |
1931 | #define PCI_PTM_CTL_EN __BIT(0) /* PTM Enable */ |
1932 | #define PCI_PTM_CTL_ROOTSEL __BIT(1) /* Root Select */ |
1933 | #define PCI_PTM_CTL_EFCTGRNL __BITS(15, 8) /* Effective Granularity */ |
1934 | |
1935 | /* |
1936 | * Extended capability ID: 0x0020 |
1937 | * M-PCIe |
1938 | */ |
1939 | |
1940 | /* |
1941 | * Extended capability ID: 0x0021 |
1942 | * Function Reading Status Queueing |
1943 | */ |
1944 | |
1945 | /* |
1946 | * Extended capability ID: 0x0022 |
1947 | * Readiness Time Reporting |
1948 | */ |
1949 | |
1950 | /* |
1951 | * Extended capability ID: 0x0023 |
1952 | * Designated Vendor-Specific |
1953 | */ |
1954 | |
1955 | /* |
1956 | * Extended capability ID: 0x0024 |
1957 | * VF Resizable BAR |
1958 | */ |
1959 | |
1960 | #endif /* _DEV_PCI_PCIREG_H_ */ |
1961 | |