1 | /*- |
2 | * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting |
3 | * All rights reserved. |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
8 | * 1. Redistributions of source code must retain the above copyright |
9 | * notice, this list of conditions and the following disclaimer, |
10 | * without modification. |
11 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
12 | * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any |
13 | * redistribution must be conditioned upon including a substantially |
14 | * similar Disclaimer requirement for further binary redistribution. |
15 | * |
16 | * NO WARRANTY |
17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
18 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
19 | * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY |
20 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL |
21 | * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, |
22 | * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER |
25 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
26 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
27 | * THE POSSIBILITY OF SUCH DAMAGES. |
28 | * |
29 | * $Id: ah_osdep.h,v 1.2 2011/07/17 20:54:51 joerg Exp $ |
30 | */ |
31 | |
32 | #ifndef _ATH_AH_OSDEP_H_ |
33 | #define _ATH_AH_OSDEP_H_ |
34 | /* |
35 | * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. |
36 | */ |
37 | #include <sys/param.h> |
38 | #include <sys/systm.h> |
39 | #include <sys/endian.h> |
40 | #include <sys/bus.h> |
41 | |
42 | /* |
43 | * Delay n microseconds. |
44 | */ |
45 | extern void ath_hal_delay(int); |
46 | #define OS_DELAY(_n) ath_hal_delay(_n) |
47 | |
48 | #define OS_INLINE __inline |
49 | #define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n)) |
50 | extern void ath_hal_memzero(void *, size_t); |
51 | #define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n) |
52 | extern void *ath_hal_memcpy(void *, const void *, size_t); |
53 | |
54 | #define abs(_a) __builtin_abs(_a) |
55 | |
56 | struct ath_hal; |
57 | extern u_int32_t ath_hal_getuptime(struct ath_hal *); |
58 | #define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah) |
59 | |
60 | /* |
61 | * WiSoC boards overload the bus tag with information about the |
62 | * board layout. We must extract the bus space tag from that |
63 | * indirect structure. For everyone else the tag is passed in |
64 | * directly. |
65 | * XXX cache indirect ref privately |
66 | */ |
67 | #ifdef AH_SUPPORT_AR5312 |
68 | #define BUSTAG(ah) \ |
69 | ((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag) |
70 | #define BUSHANDLE(ah) ((bus_space_handle_t)((ah)->ah_sh)) |
71 | |
72 | #elif defined(AH_REGOPS_FUNC) |
73 | #define BUSTAG(ah) (*(bus_space_tag_t *) (ah)->ah_st) |
74 | #define BUSHANDLE(ah) (*(bus_space_handle_t *)((ah)->ah_sh)) |
75 | #define HALTAG(t) (HAL_BUS_TAG) &(t) |
76 | #define HALHANDLE(h) (HAL_BUS_HANDLE) &(h) |
77 | #else |
78 | #define BUSTAG(ah) ((bus_space_tag_t) (ah)->ah_st) |
79 | #define BUSHANDLE(ah) ((bus_space_handle_t) ((ah)->ah_sh)) |
80 | #define HALTAG(t) (HAL_BUS_TAG) (t) |
81 | #define HALHANDLE(h) (HAL_BUS_HANDLE) (h) |
82 | #endif |
83 | |
84 | /* |
85 | * Register read/write; we assume the registers will always |
86 | * be memory-mapped. Note that register accesses are done |
87 | * using target-specific functions when debugging is enabled |
88 | * (ATHHAL_DEBUG) or we are explicitly configured this way. The |
89 | * latter is used on some platforms where the full i/o space |
90 | * cannot be directly mapped. |
91 | */ |
92 | #if defined(ATHHAL_DEBUG) || defined(AH_REGOPS_FUNC) || defined(ATHHAL_DEBUG_ALQ) |
93 | #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) |
94 | #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) |
95 | |
96 | extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); |
97 | extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); |
98 | #else |
99 | /* |
100 | * The hardware registers are native little-endian byte order. |
101 | * Big-endian hosts are handled by enabling hardware byte-swap |
102 | * of register reads and writes at reset. But the PCI clock |
103 | * domain registers are not byte swapped! Thus, on big-endian |
104 | * platforms we have to byte-swap thoese registers specifically. |
105 | * Most of this code is collapsed at compile time because the |
106 | * register values are constants. |
107 | */ |
108 | #define AH_LITTLE_ENDIAN 1234 |
109 | #define AH_BIG_ENDIAN 4321 |
110 | |
111 | #if _BYTE_ORDER == _BIG_ENDIAN |
112 | #define OS_REG_WRITE(_ah, _reg, _val) do { \ |
113 | if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \ |
114 | bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \ |
115 | (_reg), (_val)); \ |
116 | else \ |
117 | bus_space_write_stream_4((_ah)->ah_st, (_ah)->ah_sh, \ |
118 | (_reg), (_val)); \ |
119 | } while (0) |
120 | #define OS_REG_READ(_ah, _reg) \ |
121 | (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \ |
122 | bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)) : \ |
123 | bus_space_read_stream_4((_ah)->ah_st, (_ah)->ah_sh, (_reg))) |
124 | #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ |
125 | #define OS_REG_WRITE(_ah, _reg, _val) \ |
126 | bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val)) |
127 | #define OS_REG_READ(_ah, _reg) \ |
128 | ((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg))) |
129 | #endif /* _BYTE_ORDER */ |
130 | #endif /* ATHHAL_DEBUG || AH_REGFUNC || ATHHAL_DEBUG_ALQ */ |
131 | |
132 | #ifdef ATHHAL_DEBUG_ALQ |
133 | extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); |
134 | #else |
135 | #define OS_MARK(_ah, _id, _v) |
136 | #endif |
137 | |
138 | typedef void * HAL_SOFTC; /* pointer to driver/OS state */ |
139 | typedef bus_space_tag_t HAL_BUS_TAG; /* opaque bus i/o id tag */ |
140 | typedef bus_space_handle_t HAL_BUS_HANDLE; /* opaque bus i/o handle */ |
141 | |
142 | #define OS_SET_DECLARE(set, ptype) __link_set_decl(set, ptype) |
143 | #define OS_DATA_SET(set, sym) __link_set_add_rodata(set, sym) |
144 | #define OS_SET_FOREACH(pvar, set) __link_set_foreach(pvar, set) |
145 | |
146 | #define __bswap16(x) bswap16(x) |
147 | #define __bswap32(x) bswap32(x) |
148 | |
149 | #endif /* _ATH_AH_OSDEP_H_ */ |
150 | |