1 | /* $NetBSD: isareg.h,v 1.9 2005/12/11 12:22:02 christos Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 1990 The Regents of the University of California. |
5 | * All rights reserved. |
6 | * |
7 | * This code is derived from software contributed to Berkeley by |
8 | * William Jolitz. |
9 | * |
10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions |
12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. |
15 | * 2. Redistributions in binary form must reproduce the above copyright |
16 | * notice, this list of conditions and the following disclaimer in the |
17 | * documentation and/or other materials provided with the distribution. |
18 | * 3. Neither the name of the University nor the names of its contributors |
19 | * may be used to endorse or promote products derived from this software |
20 | * without specific prior written permission. |
21 | * |
22 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
28 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
29 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
30 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
31 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
32 | * SUCH DAMAGE. |
33 | * |
34 | * @(#)isa.h 5.7 (Berkeley) 5/9/91 |
35 | */ |
36 | |
37 | /* |
38 | * ISA Bus conventions |
39 | */ |
40 | |
41 | /* |
42 | * Input / Output Port Assignments |
43 | */ |
44 | |
45 | #ifndef IO_ISABEGIN |
46 | #define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ |
47 | |
48 | /* CPU Board */ |
49 | #define IO_DMA1 0x000 /* 8237A DMA Controller #1 */ |
50 | #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ |
51 | #define IO_PMP1 0x026 /* 82347 Power Management Peripheral */ |
52 | #define IO_TIMER1 0x040 /* 8253 Timer #1 */ |
53 | #define IO_TIMER2 0x048 /* 8253 Timer #2 (EISA only) */ |
54 | #define IO_KBD 0x060 /* 8042 Keyboard */ |
55 | #define IO_PPI 0x061 /* Programmable Peripheral Interface */ |
56 | #define IO_RTC 0x070 /* RTC */ |
57 | #define IO_NMI IO_RTC /* NMI Control */ |
58 | #define IO_DMAPG 0x080 /* DMA Page Registers */ |
59 | #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ |
60 | #define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */ |
61 | #define IO_NPX 0x0F0 /* Numeric Coprocessor */ |
62 | |
63 | /* Cards */ |
64 | /* 0x100 - 0x16F Open */ |
65 | |
66 | #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */ |
67 | #define IO_PMP2 0x178 /* 82347 Power Management Peripheral */ |
68 | |
69 | /* 0x17A - 0x1EF Open */ |
70 | |
71 | #define IO_WD1 0x1f0 /* Primary Fixed Disk Controller */ |
72 | #define IO_GAME 0x200 /* Game Controller */ |
73 | |
74 | /* 0x208 - 0x237 Open */ |
75 | |
76 | #define IO_BMS2 0x238 /* secondary InPort Bus Mouse */ |
77 | #define IO_BMS1 0x23c /* primary InPort Bus Mouse */ |
78 | |
79 | /* 0x240 - 0x277 Open */ |
80 | |
81 | #define IO_LPT2 0x278 /* Parallel Port #2 */ |
82 | |
83 | /* 0x280 - 0x2E7 Open */ |
84 | |
85 | #define IO_COM4 0x2e8 /* COM4 i/o address */ |
86 | |
87 | /* 0x2F0 - 0x2F7 Open */ |
88 | |
89 | #define IO_COM2 0x2f8 /* COM2 i/o address */ |
90 | |
91 | /* 0x300 - 0x32F Open */ |
92 | |
93 | #define IO_BT0 0x330 /* bustek 742a default addr. */ |
94 | #define IO_AHA0 0x330 /* adaptec 1542 default addr. */ |
95 | #define IO_UHA0 0x330 /* ultrastore 14f default addr. */ |
96 | #define IO_BT1 0x334 /* bustek 742a default addr. */ |
97 | #define IO_AHA1 0x334 /* adaptec 1542 default addr. */ |
98 | |
99 | /* 0x338 - 0x34F Open */ |
100 | |
101 | #define IO_WDS 0x350 /* WD7000 scsi */ |
102 | |
103 | /* 0x354 - 0x36F Open */ |
104 | |
105 | #define IO_FD2 0x370 /* secondary base i/o address */ |
106 | #define IO_LPT1 0x378 /* Parallel Port #1 */ |
107 | |
108 | /* 0x380 - 0x3AF Open */ |
109 | |
110 | #define IO_MDA 0x3B0 /* Monochome Adapter */ |
111 | #define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */ |
112 | #define IO_VGA 0x3C0 /* E/VGA Ports */ |
113 | #define IO_CGA 0x3D0 /* CGA Ports */ |
114 | |
115 | /* 0x3E0 - 0x3E7 Open */ |
116 | |
117 | #define IO_COM3 0x3e8 /* COM3 i/o address */ |
118 | #define IO_FD1 0x3f0 /* primary base i/o address */ |
119 | #define IO_COM1 0x3f8 /* COM1 i/o address */ |
120 | |
121 | #define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */ |
122 | #endif /* !IO_ISABEGIN */ |
123 | |
124 | /* |
125 | * Input / Output Port Sizes - these are from several sources, and tend |
126 | * to be the larger of what was found, ie COM ports can be 4, but some |
127 | * boards do not fully decode the address, thus 8 ports are used. |
128 | */ |
129 | |
130 | #ifndef IO_ISASIZES |
131 | #define IO_ISASIZES |
132 | |
133 | #define IO_COMSIZE 8 /* 8250, 16X50 com controllers */ |
134 | #define IO_CGASIZE 16 /* CGA controllers */ |
135 | #define IO_DMASIZE 16 /* 8237 DMA controllers */ |
136 | #define IO_DPGSIZE 32 /* 74LS612 DMA page reisters */ |
137 | #define IO_FDCSIZE 8 /* Nec765 floppy controllers */ |
138 | #define IO_WDCSIZE 8 /* WD compatible disk controller */ |
139 | #define IO_GAMSIZE 16 /* AT compatible game controller */ |
140 | #define IO_ICUSIZE 16 /* 8259A interrupt controllers */ |
141 | #define IO_KBDSIZE 5 /* 8042 Keyboard controllers */ |
142 | #define IO_LPTSIZE 8 /* LPT controllers, some use onl */ |
143 | #define IO_MDASIZE 16 /* Monochrome display controller */ |
144 | #define IO_RTCSIZE 16 /* CMOS real time clock, NMI con */ |
145 | #define IO_TMRSIZE 16 /* 8253 programmable timers */ |
146 | #define IO_NPXSIZE 16 /* 80387/80487 NPX registers */ |
147 | #define IO_VGASIZE 16 /* VGA controllers */ |
148 | #define IO_PMPSIZE 2 /* 82347 Power Management Peripheral */ |
149 | #endif /* !IO_ISASIZES */ |
150 | |
151 | /* |
152 | * Input / Output Memory Physical Addresses |
153 | */ |
154 | |
155 | #ifndef IOM_BEGIN |
156 | #define IOM_BEGIN 0x0a0000 /* Start of I/O Memory "hole" */ |
157 | #define IOM_END 0x100000 /* End of I/O Memory "hole" */ |
158 | #define IOM_SIZE (IOM_END - IOM_BEGIN) |
159 | |
160 | /* |
161 | * ISA DMA works < 16M (24 address lines). |
162 | */ |
163 | #define ISA_DMA_BOUNCE_THRESHOLD (16 * 1024 * 1024) |
164 | |
165 | #endif /* !IOM_BEGIN */ |
166 | |