1/* $NetBSD: isadmavar.h,v 1.26 2012/04/29 21:13:56 dsl Exp $ */
2
3/*-
4 * Copyright (c) 1997, 1998, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef _DEV_ISA_ISADMAVAR_H_
34#define _DEV_ISA_ISADMAVAR_H_
35
36#define DMAMODE_WRITE 0x00
37#define DMAMODE_READ 0x01
38#define DMAMODE_SINGLE 0x00
39#define DMAMODE_DEMAND 0x02
40#define DMAMODE_LOOP 0x04
41#define DMAMODE_LOOPDEMAND (DMAMODE_LOOP | DMAMODE_DEMAND)
42
43/*
44 * ISA DMA state. This structure is provided by the ISA chipset
45 * DMA entry points to the generic back-end functions that actually
46 * frob the controller.
47 */
48struct isa_dma_state {
49 device_t ids_dev; /* associated device (for dv_xname) */
50 bus_space_tag_t ids_bst; /* bus space tag for DMA controller */
51 bus_space_handle_t ids_dma1h; /* handle for DMA controller #1 */
52 bus_space_handle_t ids_dma2h; /* handle for DMA controller #2 */
53 bus_space_handle_t ids_dmapgh; /* handle for DMA page registers */
54 bus_dma_tag_t ids_dmat; /* DMA tag for DMA controller */
55 bus_dmamap_t ids_dmamaps[8]; /* DMA maps for each channel */
56 bus_size_t ids_dmalength[8]; /* size of DMA transfer per channel */
57 bus_size_t ids_maxsize[8]; /* max size per channel */
58 int ids_drqmap; /* available DRQs (bitmap) */
59 int ids_dmareads; /* state for isa_dmadone() (bitmap) */
60 int ids_dmafinished; /* DMA completion state (bitmap) */
61 int ids_masked; /* masked channels (bitmap) */
62 int ids_frozen; /* `frozen' count */
63 int ids_initialized; /* only initialize once... */
64};
65
66#define ISA_DMA_DRQ_ISFREE(state, drq) \
67 (((state)->ids_drqmap & (1 << (drq))) == 0)
68
69#define ISA_DMA_DRQ_ALLOC(state, drq) \
70 (state)->ids_drqmap |= (1 << (drq))
71
72#define ISA_DMA_DRQ_FREE(state, drq) \
73 (state)->ids_drqmap &= ~(1 << (drq))
74
75#define ISA_DMA_MASK_SET(state, drq) \
76 (state)->ids_masked |= (1 << (drq))
77
78#define ISA_DMA_MASK_CLR(state, drq) \
79 (state)->ids_masked &= ~(1 << (drq))
80
81/*
82 * Memory list used by _isa_malloc().
83 */
84struct isa_mem {
85 struct isa_dma_state *ids;
86 int chan;
87 bus_size_t size;
88 bus_addr_t addr;
89 void *kva;
90 struct isa_mem *next;
91};
92
93#ifdef _KERNEL
94struct proc;
95
96void _isa_dmainit(struct isa_dma_state *, bus_space_tag_t,
97 bus_dma_tag_t, device_t);
98
99void _isa_dmadestroy(struct isa_dma_state *);
100
101int _isa_dmacascade(struct isa_dma_state *, int);
102int _isa_dmacascade_stop(struct isa_dma_state *, int);
103
104bus_size_t _isa_dmamaxsize(struct isa_dma_state *, int);
105
106int _isa_dmamap_create(struct isa_dma_state *, int, bus_size_t, int);
107void _isa_dmamap_destroy(struct isa_dma_state *, int);
108
109int _isa_dmastart(struct isa_dma_state *, int, void *, bus_size_t,
110 struct proc *, int, int);
111void _isa_dmaabort(struct isa_dma_state *, int);
112bus_size_t _isa_dmacount(struct isa_dma_state *, int);
113int _isa_dmafinished(struct isa_dma_state *, int);
114void _isa_dmadone(struct isa_dma_state *, int);
115
116void _isa_dmafreeze(struct isa_dma_state *);
117void _isa_dmathaw(struct isa_dma_state *);
118
119int _isa_dmamem_alloc(struct isa_dma_state *, int, bus_size_t,
120 bus_addr_t *, int);
121void _isa_dmamem_free(struct isa_dma_state *, int, bus_addr_t,
122 bus_size_t);
123int _isa_dmamem_map(struct isa_dma_state *, int, bus_addr_t,
124 bus_size_t, void **, int);
125void _isa_dmamem_unmap(struct isa_dma_state *, int, void *,
126 size_t);
127paddr_t _isa_dmamem_mmap(struct isa_dma_state *, int, bus_addr_t,
128 bus_size_t, off_t, int, int);
129
130int _isa_drq_alloc(struct isa_dma_state *, int);
131int _isa_drq_free(struct isa_dma_state *, int);
132int _isa_drq_isfree(struct isa_dma_state *, int);
133
134#define _isa_malloc(dma_state, c, s, p, f) \
135 _isa_malloc(dma_state, c, s, f)
136#define _isa_free(v, p) _isa_free(v)
137
138void *_isa_malloc(struct isa_dma_state *, int, size_t,
139 struct malloc_type *, int);
140void _isa_free(void *, struct malloc_type *);
141paddr_t _isa_mappage(void *, off_t, int);
142#endif /* _KERNEL */
143
144#endif /* _DEV_ISA_ISADMAVAR_H_ */
145