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/tmp/gdb-13.1/gdb/mips-linux-nat.c
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1/* Native-dependent code for GNU/Linux on MIPS processors.
2
3 Copyright (C) 2001-2023 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "command.h"
22#include "gdbcmd.h"
23#include "inferior.h"
24#include "mips-tdep.h"
25#include "target.h"
26#include "regcache.h"
27#include "linux-nat-trad.h"
28#include "mips-linux-tdep.h"
29#include "target-descriptions.h"
30
31#include "gdb_proc_service.h"
32#include "gregset.h"
33
34#include <sgidefs.h>
35#include "nat/gdb_ptrace.h"
36#include <asm/ptrace.h>
37#include "inf-ptrace.h"
38
40
41#ifndef PTRACE_GET_THREAD_AREA
42#define PTRACE_GET_THREAD_AREA 25
43#endif
44
46{
47public:
48 /* Add our register access methods. */
49 void fetch_registers (struct regcache *, int) override;
50 void store_registers (struct regcache *, int) override;
51
52 void close () override;
53
54 int can_use_hw_breakpoint (enum bptype, int, int) override;
55
56 int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
57 struct expression *) override;
58
59 int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
60 struct expression *) override;
61
62 bool stopped_by_watchpoint () override;
63
64 bool stopped_data_address (CORE_ADDR *) override;
65
66 int region_ok_for_hw_watchpoint (CORE_ADDR, int) override;
67
68 const struct target_desc *read_description () override;
69
70protected:
71 /* Override linux_nat_trad_target methods. */
72 CORE_ADDR register_u_offset (struct gdbarch *gdbarch,
73 int regno, int store_p) override;
74
75 /* Override linux_nat_target low methods. */
76 void low_new_thread (struct lwp_info *lp) override;
77
78private:
79 /* Helpers. See definitions. */
81 int regno);
83 int regno);
84};
85
87
88/* Assume that we have PTRACE_GETREGS et al. support. If we do not,
89 we'll clear this and use PTRACE_PEEKUSER instead. */
90static int have_ptrace_regsets = 1;
91
92/* Map gdb internal register number to ptrace ``address''.
93 These ``addresses'' are normally defined in <asm/ptrace.h>.
94
95 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
96 and there's no point in reading or setting MIPS_ZERO_REGNUM.
97 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
98
99static CORE_ADDR
100mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
101{
102 CORE_ADDR regaddr;
103
104 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
105 error (_("Bogon register number %d."), regno);
106
107 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
108 regaddr = regno;
109 else if ((regno >= mips_regnum (gdbarch)->fp0)
110 && (regno < mips_regnum (gdbarch)->fp0 + 32))
111 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
112 else if (regno == mips_regnum (gdbarch)->pc)
113 regaddr = PC;
114 else if (regno == mips_regnum (gdbarch)->cause)
115 regaddr = store? (CORE_ADDR) -1 : CAUSE;
116 else if (regno == mips_regnum (gdbarch)->badvaddr)
117 regaddr = store? (CORE_ADDR) -1 : BADVADDR;
118 else if (regno == mips_regnum (gdbarch)->lo)
119 regaddr = MMLO;
120 else if (regno == mips_regnum (gdbarch)->hi)
121 regaddr = MMHI;
122 else if (regno == mips_regnum (gdbarch)->fp_control_status)
123 regaddr = FPC_CSR;
125 regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
126 else if (mips_regnum (gdbarch)->dspacc != -1
127 && regno >= mips_regnum (gdbarch)->dspacc
128 && regno < mips_regnum (gdbarch)->dspacc + 6)
129 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
130 else if (regno == mips_regnum (gdbarch)->dspctl)
131 regaddr = DSP_CONTROL;
133 regaddr = 0;
134 else
135 regaddr = (CORE_ADDR) -1;
136
137 return regaddr;
138}
139
140static CORE_ADDR
141mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
142{
143 CORE_ADDR regaddr;
144
145 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
146 error (_("Bogon register number %d."), regno);
147
148 /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR
149 or PTRACE_POKEUSR. */
150 if (register_size (gdbarch, regno) > sizeof (PTRACE_TYPE_RET))
151 return (CORE_ADDR) -1;
152
153 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
154 regaddr = regno;
155 else if ((regno >= mips_regnum (gdbarch)->fp0)
156 && (regno < mips_regnum (gdbarch)->fp0 + 32))
157 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
158 else if (regno == mips_regnum (gdbarch)->pc)
159 regaddr = MIPS64_PC;
160 else if (regno == mips_regnum (gdbarch)->cause)
161 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
162 else if (regno == mips_regnum (gdbarch)->badvaddr)
163 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
164 else if (regno == mips_regnum (gdbarch)->lo)
165 regaddr = MIPS64_MMLO;
166 else if (regno == mips_regnum (gdbarch)->hi)
167 regaddr = MIPS64_MMHI;
168 else if (regno == mips_regnum (gdbarch)->fp_control_status)
169 regaddr = MIPS64_FPC_CSR;
171 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
172 else if (mips_regnum (gdbarch)->dspacc != -1
173 && regno >= mips_regnum (gdbarch)->dspacc
174 && regno < mips_regnum (gdbarch)->dspacc + 6)
175 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
176 else if (regno == mips_regnum (gdbarch)->dspctl)
177 regaddr = DSP_CONTROL;
179 regaddr = 0;
180 else
181 regaddr = (CORE_ADDR) -1;
182
183 return regaddr;
184}
185
186/* Fetch the thread-local storage pointer for libthread_db. */
187
188ps_err_e
190 lwpid_t lwpid, int idx, void **base)
191{
192 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
193 return PS_ERR;
194
195 /* IDX is the bias from the thread pointer to the beginning of the
196 thread descriptor. It has to be subtracted due to implementation
197 quirks in libthread_db. */
198 *base = (void *) ((char *)*base - idx);
199
200 return PS_OK;
201}
202
203/* Wrapper functions. These are only used by libthread_db. */
204
205void
207{
208 if (mips_isa_regsize (regcache->arch ()) == 4)
209 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
210 else
212}
213
214void
216 gdb_gregset_t *gregsetp, int regno)
217{
218 if (mips_isa_regsize (regcache->arch ()) == 4)
219 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
220 else
222}
223
224void
226{
228}
229
230void
232 gdb_fpregset_t *fpregsetp, int regno)
233{
235}
236
237
238/* Fetch REGNO (or all registers if REGNO == -1) from the target
239 using PTRACE_GETREGS et al. */
240
241void
243 (struct regcache *regcache, int regno)
244{
245 struct gdbarch *gdbarch = regcache->arch ();
246 int is_fp, is_dsp;
247 int have_dsp;
248 int regi;
249 int tid;
250
251 if (regno >= mips_regnum (gdbarch)->fp0
252 && regno <= mips_regnum (gdbarch)->fp0 + 32)
253 is_fp = 1;
254 else if (regno == mips_regnum (gdbarch)->fp_control_status)
255 is_fp = 1;
256 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
257 is_fp = 1;
258 else
259 is_fp = 0;
260
261 /* DSP registers are optional and not a part of any set. */
262 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
263 if (!have_dsp)
264 is_dsp = 0;
265 else if (regno >= mips_regnum (gdbarch)->dspacc
266 && regno < mips_regnum (gdbarch)->dspacc + 6)
267 is_dsp = 1;
268 else if (regno == mips_regnum (gdbarch)->dspctl)
269 is_dsp = 1;
270 else
271 is_dsp = 0;
272
273 tid = get_ptrace_pid (regcache->ptid ());
274
275 if (regno == -1 || (!is_fp && !is_dsp))
276 {
278
279 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
280 {
281 if (errno == EIO)
282 {
284 return;
285 }
286 perror_with_name (_("Couldn't get registers"));
287 }
288
290 (const mips64_elf_gregset_t *) &regs);
291 }
292
293 if (regno == -1 || is_fp)
294 {
295 mips64_elf_fpregset_t fp_regs;
296
297 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
298 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
299 {
300 if (errno == EIO)
301 {
303 return;
304 }
305 perror_with_name (_("Couldn't get FP registers"));
306 }
307
309 (const mips64_elf_fpregset_t *) &fp_regs);
310 }
311
312 if (is_dsp)
314 else if (regno == -1 && have_dsp)
315 {
316 for (regi = mips_regnum (gdbarch)->dspacc;
317 regi < mips_regnum (gdbarch)->dspacc + 6;
318 regi++)
321 mips_regnum (gdbarch)->dspctl);
322 }
323}
324
325/* Store REGNO (or all registers if REGNO == -1) to the target
326 using PTRACE_SETREGS et al. */
327
328void
330 (struct regcache *regcache, int regno)
331{
332 struct gdbarch *gdbarch = regcache->arch ();
333 int is_fp, is_dsp;
334 int have_dsp;
335 int regi;
336 int tid;
337
338 if (regno >= mips_regnum (gdbarch)->fp0
339 && regno <= mips_regnum (gdbarch)->fp0 + 32)
340 is_fp = 1;
341 else if (regno == mips_regnum (gdbarch)->fp_control_status)
342 is_fp = 1;
343 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
344 is_fp = 1;
345 else
346 is_fp = 0;
347
348 /* DSP registers are optional and not a part of any set. */
349 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
350 if (!have_dsp)
351 is_dsp = 0;
352 else if (regno >= mips_regnum (gdbarch)->dspacc
353 && regno < mips_regnum (gdbarch)->dspacc + 6)
354 is_dsp = 1;
355 else if (regno == mips_regnum (gdbarch)->dspctl)
356 is_dsp = 1;
357 else
358 is_dsp = 0;
359
360 tid = get_ptrace_pid (regcache->ptid ());
361
362 if (regno == -1 || (!is_fp && !is_dsp))
363 {
365
366 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
367 perror_with_name (_("Couldn't get registers"));
368
369 mips64_fill_gregset (regcache, &regs, regno);
370
371 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
372 perror_with_name (_("Couldn't set registers"));
373 }
374
375 if (regno == -1 || is_fp)
376 {
377 mips64_elf_fpregset_t fp_regs;
378
379 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
380 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
381 perror_with_name (_("Couldn't get FP registers"));
382
383 mips64_fill_fpregset (regcache, &fp_regs, regno);
384
385 if (ptrace (PTRACE_SETFPREGS, tid, 0L,
386 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
387 perror_with_name (_("Couldn't set FP registers"));
388 }
389
390 if (is_dsp)
392 else if (regno == -1 && have_dsp)
393 {
394 for (regi = mips_regnum (gdbarch)->dspacc;
395 regi < mips_regnum (gdbarch)->dspacc + 6;
396 regi++)
399 mips_regnum (gdbarch)->dspctl);
400 }
401}
402
403/* Fetch REGNO (or all registers if REGNO == -1) from the target
404 using any working method. */
405
406void
408{
409 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
412
413 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
414 back to PTRACE_PEEKUSER. */
416 {
418
419 /* Fill the inaccessible zero register with zero. */
420 if (regnum == MIPS_ZERO_REGNUM || regnum == -1)
422 }
423}
424
425/* Store REGNO (or all registers if REGNO == -1) to the target
426 using any working method. */
427
428void
430{
431 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
434
435 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
436 back to PTRACE_PEEKUSER. */
439}
440
441/* Return the address in the core dump or inferior of register
442 REGNO. */
443
444CORE_ADDR
446 int regno, int store_p)
447{
448 if (mips_abi_regsize (gdbarch) == 8)
449 return mips64_linux_register_addr (gdbarch, regno, store_p);
450 else
451 return mips_linux_register_addr (gdbarch, regno, store_p);
452}
453
454const struct target_desc *
456{
457 static int have_dsp = -1;
458
459 if (have_dsp < 0)
460 {
461 int tid = get_ptrace_pid (inferior_ptid);
462
463 errno = 0;
464 ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
465 switch (errno)
466 {
467 case 0:
468 have_dsp = 1;
469 break;
470 case EIO:
471 have_dsp = 0;
472 break;
473 default:
474 perror_with_name (_("Couldn't check DSP support"));
475 break;
476 }
477 }
478
479 /* Report that target registers are a size we know for sure
480 that we can get from ptrace. */
481 if (_MIPS_SIM == _ABIO32)
482 return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
483 else
484 return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
485}
486
487/* -1 if the kernel and/or CPU do not support watch registers.
488 1 if watch_readback is valid and we can read style, num_valid
489 and the masks.
490 0 if we need to read the watch_readback. */
491
493
494/* Cached watch register read values. */
495
497
499
500/* The current set of watch register values for writing the
501 registers. */
502
504
505static void
506mips_show_dr (const char *func, CORE_ADDR addr,
507 int len, enum target_hw_bp_type type)
508{
509 int i;
510
512 if (addr || len)
514 " (addr=%s, len=%d, type=%s)",
515 paddress (target_gdbarch (), addr), len,
516 type == hw_write ? "data-write"
517 : (type == hw_read ? "data-read"
518 : (type == hw_access ? "data-read/write"
519 : (type == hw_execute ? "instruction-execute"
520 : "??unknown??"))));
521 gdb_puts (":\n", gdb_stdlog);
522
523 for (i = 0; i < MAX_DEBUG_REGISTER; i++)
524 gdb_printf (gdb_stdlog, "\tDR%d: lo=%s, hi=%s\n", i,
527 i)),
530 i)));
531}
532
533/* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
534 handle the specified watch type. */
535
536int
538 int cnt, int ot)
539{
540 int i;
541 uint32_t wanted_mask, irw_mask;
542
546 return 0;
547
548 switch (type)
549 {
551 wanted_mask = W_MASK;
552 break;
554 wanted_mask = R_MASK;
555 break;
557 wanted_mask = R_MASK | W_MASK;
558 break;
559 default:
560 return 0;
561 }
562
563 for (i = 0;
565 i++)
566 {
568 if ((irw_mask & wanted_mask) == wanted_mask)
569 cnt--;
570 }
571 return (cnt == 0) ? 1 : 0;
572}
573
574/* Target to_stopped_by_watchpoint implementation. Return 1 if
575 stopped by watchpoint. The watchhi R and W bits indicate the watch
576 register triggered. */
577
578bool
580{
581 int n;
582 int num_valid;
583
587 return false;
588
590
591 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
593 return true;
594
595 return false;
596}
597
598/* Target to_stopped_data_address implementation. Set the address
599 where the watch triggered (if known). Return 1 if the address was
600 known. */
601
602bool
604{
605 /* On mips we don't know the low order 3 bits of the data address,
606 so we must return false. */
607 return false;
608}
609
610/* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
611 the specified region can be covered by the watch registers. */
612
613int
615{
616 struct pt_watch_regs dummy_regs;
617 int i;
618
622 return 0;
623
624 dummy_regs = watch_readback;
625 /* Clear them out. */
626 for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
627 mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
628 return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
629}
630
631/* Write the mirrored watch register values for each thread. */
632
633static int
635{
636 for (const lwp_info *lp : all_lwps ())
637 {
638 int tid = lp->ptid.lwp ();
639 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
640 perror_with_name (_("Couldn't write debug register"));
641 }
642 return 0;
643}
644
645/* linux_nat_target::low_new_thread implementation. Write the
646 mirrored watch register values for the new thread. */
647
648void
650{
651 long tid = lp->ptid.lwp ();
652
656 return;
657
658 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
659 perror_with_name (_("Couldn't write debug register"));
660}
661
662/* Target to_insert_watchpoint implementation. Try to insert a new
663 watch. Return zero on success. */
664
665int
667 enum target_hw_bp_type type,
668 struct expression *cond)
669{
670 struct pt_watch_regs regs;
671 struct mips_watchpoint *new_watch;
672 struct mips_watchpoint **pw;
673
674 int retval;
675
679 return -1;
680
681 if (len <= 0)
682 return -1;
683
684 regs = watch_readback;
685 /* Add the current watches. */
687
688 /* Now try to add the new watch. */
689 if (!mips_linux_watch_try_one_watch (&regs, addr, len,
691 return -1;
692
693 /* It fit. Stick it on the end of the list. */
694 new_watch = XNEW (struct mips_watchpoint);
695 new_watch->addr = addr;
696 new_watch->len = len;
697 new_watch->type = type;
698 new_watch->next = NULL;
699
700 pw = &current_watches;
701 while (*pw != NULL)
702 pw = &(*pw)->next;
703 *pw = new_watch;
704
705 watch_mirror = regs;
706 retval = write_watchpoint_regs ();
707
708 if (show_debug_regs)
709 mips_show_dr ("insert_watchpoint", addr, len, type);
710
711 return retval;
712}
713
714/* Target to_remove_watchpoint implementation. Try to remove a watch.
715 Return zero on success. */
716
717int
719 enum target_hw_bp_type type,
720 struct expression *cond)
721{
722 int retval;
723 int deleted_one;
724
725 struct mips_watchpoint **pw;
726 struct mips_watchpoint *w;
727
728 /* Search for a known watch that matches. Then unlink and free
729 it. */
730 deleted_one = 0;
731 pw = &current_watches;
732 while ((w = *pw))
733 {
734 if (w->addr == addr && w->len == len && w->type == type)
735 {
736 *pw = w->next;
737 xfree (w);
738 deleted_one = 1;
739 break;
740 }
741 pw = &(w->next);
742 }
743
744 if (!deleted_one)
745 return -1; /* We don't know about it, fail doing nothing. */
746
747 /* At this point watch_readback is known to be valid because we
748 could not have added the watch without reading it. */
749 gdb_assert (watch_readback_valid == 1);
750
753
754 retval = write_watchpoint_regs ();
755
756 if (show_debug_regs)
757 mips_show_dr ("remove_watchpoint", addr, len, type);
758
759 return retval;
760}
761
762/* Target to_close implementation. Free any watches and call the
763 super implementation. */
764
765void
767{
768 struct mips_watchpoint *w;
769 struct mips_watchpoint *nw;
770
771 /* Clean out the current_watches list. */
772 w = current_watches;
773 while (w)
774 {
775 nw = w->next;
776 xfree (w);
777 w = nw;
778 }
779 current_watches = NULL;
780
782}
783
785void
787{
788 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
789 &show_debug_regs, _("\
790Set whether to show variables that mirror the mips debug registers."), _("\
791Show whether to show variables that mirror the mips debug registers."), _("\
792Use \"on\" to enable, \"off\" to disable.\n\
793If enabled, the debug registers values are shown when GDB inserts\n\
794or removes a hardware breakpoint or watchpoint, and when the inferior\n\
795triggers a breakpoint or watchpoint."),
796 NULL,
797 NULL,
800
803}
int regnum
Definition: aarch64-tdep.c:68
void xfree(void *)
struct gdbarch * target_gdbarch(void)
Definition: arch-utils.c:1453
bptype
Definition: breakpoint.h:84
@ bp_read_watchpoint
Definition: breakpoint.h:93
@ bp_access_watchpoint
Definition: breakpoint.h:94
@ bp_hardware_watchpoint
Definition: breakpoint.h:92
void close() override
Definition: inf-child.c:183
void fetch_registers(struct regcache *, int) override
void store_registers(struct regcache *, int) override
int region_ok_for_hw_watchpoint(CORE_ADDR, int) override
void store_registers(struct regcache *, int) override
int can_use_hw_breakpoint(enum bptype, int, int) override
bool stopped_data_address(CORE_ADDR *) override
int remove_watchpoint(CORE_ADDR, int, enum target_hw_bp_type, struct expression *) override
bool stopped_by_watchpoint() override
void low_new_thread(struct lwp_info *lp) override
const struct target_desc * read_description() override
void close() override
void mips64_regsets_store_registers(struct regcache *regcache, int regno)
void fetch_registers(struct regcache *, int) override
int insert_watchpoint(CORE_ADDR, int, enum target_hw_bp_type, struct expression *) override
void mips64_regsets_fetch_registers(struct regcache *regcache, int regno)
CORE_ADDR register_u_offset(struct gdbarch *gdbarch, int regno, int store_p) override
gdbarch * arch() const
Definition: regcache.c:230
void raw_supply_zeroed(int regnum)
Definition: regcache.c:1101
ptid_t ptid() const
Definition: regcache.h:407
struct cmd_list_element * maintenance_show_cmdlist
Definition: maint.c:752
struct cmd_list_element * maintenance_set_cmdlist
Definition: maint.c:751
set_show_commands add_setshow_boolean_cmd(const char *name, enum command_class theclass, bool *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:739
@ class_maintenance
Definition: command.h:65
#define PTRACE_TYPE_ARG3
Definition: config.h:663
#define PTRACE_TYPE_RET
Definition: config.h:672
#define ptrace(request, pid, addr, data)
Definition: gdb_ptrace.h:141
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1899
int gdbarch_fp0_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:2057
GDB_FPREGSET_T gdb_fpregset_t
Definition: gregset.h:35
GDB_GREGSET_T gdb_gregset_t
Definition: gregset.h:34
@ L
Definition: ia64-tdep.c:85
void add_inf_child_target(inf_child_target *target)
Definition: inf-child.c:418
pid_t get_ptrace_pid(ptid_t ptid)
Definition: inf-ptrace.c:238
ptid_t inferior_ptid
Definition: infcmd.c:91
lwp_info_range all_lwps()
Definition: linux-nat.c:626
struct linux_nat_target * linux_target
Definition: linux-nat.c:190
const struct target_desc * tdesc_mips_dsp_linux
Definition: mips-dsp-linux.c:8
#define PTRACE_GET_THREAD_AREA
static mips_linux_nat_target the_mips_linux_nat_target
void supply_gregset(struct regcache *regcache, const gdb_gregset_t *gregsetp)
static CORE_ADDR mips_linux_register_addr(struct gdbarch *gdbarch, int regno, int store)
void fill_gregset(const struct regcache *regcache, gdb_gregset_t *gregsetp, int regno)
static struct mips_watchpoint * current_watches
void _initialize_mips_linux_nat()
void supply_fpregset(struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
ps_err_e ps_get_thread_area(struct ps_prochandle *ph, lwpid_t lwpid, int idx, void **base)
static int watch_readback_valid
static int write_watchpoint_regs(void)
static struct pt_watch_regs watch_readback
static struct pt_watch_regs watch_mirror
void fill_fpregset(const struct regcache *regcache, gdb_fpregset_t *fpregsetp, int regno)
static void mips_show_dr(const char *func, CORE_ADDR addr, int len, enum target_hw_bp_type type)
static CORE_ADDR mips64_linux_register_addr(struct gdbarch *gdbarch, int regno, int store)
static int have_ptrace_regsets
void mips_fill_gregset(const struct regcache *regcache, mips_elf_gregset_t *gregsetp, int regno)
void mips_supply_gregset(struct regcache *regcache, const mips_elf_gregset_t *gregsetp)
int mips_linux_restart_reg_p(struct gdbarch *gdbarch)
void mips64_fill_gregset(const struct regcache *regcache, mips64_elf_gregset_t *gregsetp, int regno)
void mips64_fill_fpregset(const struct regcache *regcache, mips64_elf_fpregset_t *fpregsetp, int regno)
void mips64_supply_fpregset(struct regcache *regcache, const mips64_elf_fpregset_t *fpregsetp)
void mips64_supply_gregset(struct regcache *regcache, const mips64_elf_gregset_t *gregsetp)
mips64_elf_greg_t mips64_elf_gregset_t[MIPS64_ELF_NGREG]
#define MIPS64_CAUSE
#define MIPS64_BADVADDR
#define DSP_CONTROL
#define MMLO
#define MMHI
#define MIPS64_MMLO
#define PC
#define FPC_CSR
#define MIPS64_FPC_CSR
mips_elf_greg_t mips_elf_gregset_t[ELF_NGREG]
#define MIPS64_FPC_EIR
#define CAUSE
#define DSP_BASE
#define BADVADDR
#define MIPS64_MMHI
#define MIPS64_FPR_BASE
#define MIPS64_PC
@ MIPS_RESTART_REGNUM
#define FPC_EIR
mips64_elf_fpreg_t mips64_elf_fpregset_t[MIPS64_ELF_NFPREG]
#define FPR_BASE
CORE_ADDR mips_linux_watch_get_watchlo(struct pt_watch_regs *regs, int n)
void mips_linux_watch_set_watchlo(struct pt_watch_regs *regs, int n, CORE_ADDR value)
uint32_t mips_linux_watch_get_irw_mask(struct pt_watch_regs *regs, int n)
uint32_t mips_linux_watch_get_num_valid(struct pt_watch_regs *regs)
uint32_t mips_linux_watch_type_to_irw(enum target_hw_bp_type type)
int mips_linux_watch_try_one_watch(struct pt_watch_regs *regs, CORE_ADDR addr, int len, uint32_t irw)
void mips_linux_watch_populate_regs(struct mips_watchpoint *current_watches, struct pt_watch_regs *regs)
int mips_linux_read_watch_registers(long lwpid, struct pt_watch_regs *watch_readback, int *watch_readback_valid, int force)
uint32_t mips_linux_watch_get_watchhi(struct pt_watch_regs *regs, int n)
#define R_MASK
uint32_t num_valid
#define MAX_DEBUG_REGISTER
#define W_MASK
#define PTRACE_SET_WATCH_REGS
const struct target_desc * tdesc_mips_linux
Definition: mips-linux.c:8
unsigned int mips_abi_regsize(struct gdbarch *gdbarch)
Definition: mips-tdep.c:309
int mips_isa_regsize(struct gdbarch *gdbarch)
Definition: mips-tdep.c:290
@ MIPS_ZERO_REGNUM
Definition: mips-tdep.h:135
const struct target_desc * tdesc_mips64_dsp_linux
const struct target_desc * tdesc_mips64_linux
Definition: mips64-linux.c:8
#define PTRACE_GETREGS
#define PTRACE_GETFPREGS
#define PTRACE_SETREGS
#define PTRACE_SETFPREGS
int register_size(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:170
void(* func)(remote_target *remote, char *)
ptid_t ptid
Definition: linux-nat.h:211
int dspacc
Definition: mips-tdep.h:80
int dspctl
Definition: mips-tdep.h:81
int badvaddr
Definition: mips-tdep.h:76
int fp_implementation_revision
Definition: mips-tdep.h:74
int fp_control_status
Definition: mips-tdep.h:75
enum target_hw_bp_type type
struct mips_watchpoint * next
Definition: gdbtypes.h:922
void perror_with_name(const char *string)
Definition: utils.c:643
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: utils.c:3114
void gdb_printf(struct ui_file *stream, const char *format,...)
Definition: utils.c:1865
void gdb_puts(const char *linebuffer, struct ui_file *stream)
Definition: utils.c:1788
#define gdb_stdlog
Definition: utils.h:196