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Classes | |
struct | aarch64_register |
struct | aarch64_memory_operand |
struct | aarch64_insn_data |
struct | aarch64_insn_visitor |
Macros | |
#define | aarch64_debug_printf(fmt, ...) debug_prefixed_printf_cond (aarch64_debug, "aarch64", fmt, ##__VA_ARGS__) |
#define | submask(x) ((1L << ((x) + 1)) - 1) |
#define | bits(obj, st, fn) (((obj) >> (st)) & submask ((fn) - (st))) |
#define | bit(obj, st) (((obj) >> (st)) & 1) |
#define | sbits(obj, st, fn) ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) |
#define | IS_BTI(instruction) ((instruction & 0xffffff3f) == 0xd503241f) |
#define | ENCODE(val, size, offset) ((uint32_t) ((val & ((1ULL << size) - 1)) << offset)) |
#define | can_encode_int32(val, bits) (((val) >> (bits)) == 0 || ((val) >> (bits)) == -1) |
#define | emit_b(buf, is_bl, offset) aarch64_emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0))) |
#define | emit_bcond(buf, cond, offset) |
#define | emit_cb(buf, is_cbnz, rt, offset) |
#define | emit_ldr(buf, rt, rn, operand) aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand) |
#define | emit_ldrsw(buf, rt, rn, operand) aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand) |
#define | emit_tb(buf, is_tbnz, bit, rt, offset) |
#define | emit_nop(buf) aarch64_emit_insn (buf, NOP) |
Enumerations | |
enum | aarch64_opcodes { B = 0x14000000 , BL = 0x80000000 | B , BCOND = 0x40000000 | B , CBZ = 0x20000000 | B , CBNZ = 0x21000000 | B , TBZ = 0x36000000 | B , TBNZ = 0x37000000 | B , BR = 0xd61f0000 , BLR = 0xd63f0000 , RET = 0xd65f0000 , STP = 0x28000000 , LDP = 0x28400000 , STP_SIMD_VFP = 0x04000000 | STP , LDP_SIMD_VFP = 0x04000000 | LDP , STR = 0x38000000 , LDR = 0x00400000 | STR , LDRSW = 0x80800000 | STR , LDAXR = 0x085ffc00 , STXR = 0x08007c00 , STLR = 0x089ffc00 , MOV = 0x52800000 , MOVK = 0x20000000 | MOV , ADD = 0x01000000 , SUB = 0x40000000 | ADD , SUBS = 0x20000000 | SUB , AND = 0x0a000000 , ORR = 0x20000000 | AND , ORN = 0x00200000 | ORR , EOR = 0x40000000 | AND , LSLV = 0x1ac02000 , LSRV = 0x00000400 | LSLV , ASRV = 0x00000800 | LSLV , SBFM = 0x13000000 , UBFM = 0x40000000 | SBFM , CSINC = 0x9a800400 , MUL = 0x1b007c00 , MSR = 0xd5100000 , MRS = 0x00200000 | MSR , HINT = 0xd503201f , SEVL = (5 << 5) | HINT , WFE = (2 << 5) | HINT , NOP = (0 << 5) | HINT } |
enum | aarch64_masks { CLEAR_Rn_MASK = 0xfffffc1f } |
enum | aarch64_memory_operand_type { MEMORY_OPERAND_OFFSET , MEMORY_OPERAND_PREINDEX , MEMORY_OPERAND_POSTINDEX } |
Functions | |
int | aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp, unsigned *rd, int32_t *offset) |
int | aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset) |
int | aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset) |
int | aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz, unsigned *rn, int32_t *offset) |
int | aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit, unsigned *rt, int32_t *imm) |
int | aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w, int *is64, unsigned *rt, int32_t *offset) |
void | aarch64_relocate_instruction (uint32_t insn, const struct aarch64_insn_visitor *visitor, struct aarch64_insn_data *data) |
int | aarch64_emit_insn (uint32_t *buf, uint32_t insn) |
int | aarch64_emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode, struct aarch64_register rt, struct aarch64_register rn, struct aarch64_memory_operand operand) |
Variables | |
bool | aarch64_debug |
#define aarch64_debug_printf | ( | fmt, | |
... | |||
) | debug_prefixed_printf_cond (aarch64_debug, "aarch64", fmt, ##__VA_ARGS__) |
Definition at line 26 of file aarch64-insn.h.
#define bit | ( | obj, | |
st | |||
) | (((obj) >> (st)) & 1) |
Definition at line 38 of file aarch64-insn.h.
#define bits | ( | obj, | |
st, | |||
fn | |||
) | (((obj) >> (st)) & submask ((fn) - (st))) |
Definition at line 35 of file aarch64-insn.h.
Definition at line 250 of file aarch64-insn.h.
#define emit_b | ( | buf, | |
is_bl, | |||
offset | |||
) | aarch64_emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0))) |
Definition at line 263 of file aarch64-insn.h.
#define emit_bcond | ( | buf, | |
cond, | |||
offset | |||
) |
Definition at line 275 of file aarch64-insn.h.
#define emit_cb | ( | buf, | |
is_cbnz, | |||
rt, | |||
offset | |||
) |
Definition at line 291 of file aarch64-insn.h.
#define emit_ldr | ( | buf, | |
rt, | |||
rn, | |||
operand | |||
) | aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand) |
Definition at line 309 of file aarch64-insn.h.
#define emit_ldrsw | ( | buf, | |
rt, | |||
rn, | |||
operand | |||
) | aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand) |
Definition at line 323 of file aarch64-insn.h.
#define emit_nop | ( | buf | ) | aarch64_emit_insn (buf, NOP) |
Definition at line 349 of file aarch64-insn.h.
#define emit_tb | ( | buf, | |
is_tbnz, | |||
bit, | |||
rt, | |||
offset | |||
) |
Definition at line 339 of file aarch64-insn.h.
Definition at line 182 of file aarch64-insn.h.
#define IS_BTI | ( | instruction | ) | ((instruction & 0xffffff3f) == 0xd503241f) |
Definition at line 48 of file aarch64-insn.h.
#define sbits | ( | obj, | |
st, | |||
fn | |||
) | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) |
Definition at line 42 of file aarch64-insn.h.
#define submask | ( | x | ) | ((1L << ((x) + 1)) - 1) |
Definition at line 32 of file aarch64-insn.h.
enum aarch64_masks |
Enumerator | |
---|---|
CLEAR_Rn_MASK |
Definition at line 139 of file aarch64-insn.h.
Enumerator | |
---|---|
MEMORY_OPERAND_OFFSET | |
MEMORY_OPERAND_PREINDEX | |
MEMORY_OPERAND_POSTINDEX |
Definition at line 155 of file aarch64-insn.h.
enum aarch64_opcodes |
Definition at line 53 of file aarch64-insn.h.
int aarch64_decode_adr | ( | CORE_ADDR | addr, |
uint32_t | insn, | ||
int * | is_adrp, | ||
unsigned * | rd, | ||
int32_t * | offset | ||
) |
Definition at line 50 of file aarch64-insn.c.
References aarch64_debug_printf, decode_masked_match(), and sbits.
Referenced by aarch64_relocate_instruction().
int aarch64_decode_b | ( | CORE_ADDR | addr, |
uint32_t | insn, | ||
int * | is_bl, | ||
int32_t * | offset | ||
) |
Definition at line 91 of file aarch64-insn.c.
References aarch64_debug, decode_masked_match(), and sbits.
Referenced by aarch64_relocate_instruction().
int aarch64_decode_bcond | ( | CORE_ADDR | addr, |
uint32_t | insn, | ||
unsigned * | cond, | ||
int32_t * | offset | ||
) |
Definition at line 125 of file aarch64-insn.c.
References aarch64_debug, decode_masked_match(), and sbits.
Referenced by aarch64_relocate_instruction().
int aarch64_decode_cb | ( | CORE_ADDR | addr, |
uint32_t | insn, | ||
int * | is64, | ||
int * | is_cbnz, | ||
unsigned * | rn, | ||
int32_t * | offset | ||
) |
Definition at line 157 of file aarch64-insn.c.
References aarch64_debug, decode_masked_match(), and sbits.
Referenced by aarch64_relocate_instruction().
int aarch64_decode_ldr_literal | ( | CORE_ADDR | addr, |
uint32_t | insn, | ||
int * | is_w, | ||
int * | is64, | ||
unsigned * | rt, | ||
int32_t * | offset | ||
) |
Definition at line 230 of file aarch64-insn.c.
References aarch64_debug, and sbits.
Referenced by aarch64_relocate_instruction().
int aarch64_decode_tb | ( | CORE_ADDR | addr, |
uint32_t | insn, | ||
int * | is_tbnz, | ||
unsigned * | bit, | ||
unsigned * | rt, | ||
int32_t * | imm | ||
) |
Definition at line 193 of file aarch64-insn.c.
References aarch64_debug, bit, decode_masked_match(), and sbits.
Referenced by aarch64_relocate_instruction().
int aarch64_emit_insn | ( | uint32_t * | buf, |
uint32_t | insn | ||
) |
Definition at line 314 of file aarch64-insn.c.
Referenced by aarch64_displaced_step_others(), and aarch64_emit_load_store().
int aarch64_emit_load_store | ( | uint32_t * | buf, |
uint32_t | size, | ||
enum aarch64_opcodes | opcode, | ||
struct aarch64_register | rt, | ||
struct aarch64_register | rn, | ||
struct aarch64_memory_operand | operand | ||
) |
Definition at line 323 of file aarch64-insn.c.
References aarch64_emit_insn(), ENCODE, aarch64_memory_operand::index, MEMORY_OPERAND_OFFSET, MEMORY_OPERAND_POSTINDEX, MEMORY_OPERAND_PREINDEX, aarch64_register::num, size, and aarch64_memory_operand::type.
void aarch64_relocate_instruction | ( | uint32_t | insn, |
const struct aarch64_insn_visitor * | visitor, | ||
struct aarch64_insn_data * | data | ||
) |
Definition at line 274 of file aarch64-insn.c.
References aarch64_decode_adr(), aarch64_decode_b(), aarch64_decode_bcond(), aarch64_decode_cb(), aarch64_decode_ldr_literal(), aarch64_decode_tb(), aarch64_insn_visitor::adr, aarch64_insn_visitor::b, aarch64_insn_visitor::b_cond, bit, aarch64_insn_visitor::cb, aarch64_insn_visitor::ldr_literal, aarch64_insn_visitor::others, aarch64_insn_visitor::tb, and visitor.
Referenced by aarch64_displaced_step_copy_insn().
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extern |
Definition at line 23 of file aarch64-insn.c.
Referenced by _initialize_aarch64_tdep(), aarch64_decode_b(), aarch64_decode_bcond(), aarch64_decode_cb(), aarch64_decode_ldr_literal(), and aarch64_decode_tb().