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aarch64.h
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1/* Common target-dependent functionality for AArch64.
2
3 Copyright (C) 2017-2023 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#ifndef ARCH_AARCH64_H
21#define ARCH_AARCH64_H
22
23#include "gdbsupport/tdesc.h"
24
25/* Holds information on what architectural features are available. This is
26 used to select register sets. */
28{
29 /* A non zero VQ value indicates both the presence of SVE and the
30 Vector Quotient - the number of 128bit chunks in an SVE Z
31 register. */
32 uint64_t vq = 0;
33
34 bool pauth = false;
35 bool mte = false;
36
37 /* A positive TLS value indicates the number of TLS registers available. */
38 uint8_t tls = 0;
39};
40
41inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs)
42{
43 return lhs.vq == rhs.vq
44 && lhs.pauth == rhs.pauth
45 && lhs.mte == rhs.mte
46 && lhs.tls == rhs.tls;
47}
48
49namespace std
50{
51 template<>
52 struct hash<aarch64_features>
53 {
54 std::size_t operator()(const aarch64_features &features) const noexcept
55 {
56 std::size_t h;
57
58 h = features.vq;
59 h = h << 1 | features.pauth;
60 h = h << 1 | features.mte;
61 /* Shift by two bits for now. We may need to increase this in the future
62 if more TLS registers get added. */
63 h = h << 2 | features.tls;
64 return h;
65 }
66 };
67}
68
69/* Create the aarch64 target description. */
70
73
74/* Given a pointer value POINTER and a MASK of non-address bits, remove the
75 non-address bits from the pointer and sign-extend the result if required.
76 The sign-extension is required so we can handle kernel addresses
77 correctly. */
78CORE_ADDR aarch64_remove_top_bits (CORE_ADDR pointer, CORE_ADDR mask);
79
80/* Given CMASK and DMASK the two PAC mask registers, return the correct PAC
81 mask to use for removing non-address bits from a pointer. */
82CORE_ADDR
83aarch64_mask_from_pac_registers (const CORE_ADDR cmask, const CORE_ADDR dmask);
84
85/* Register numbers of various important registers.
86 Note that on SVE, the Z registers reuse the V register numbers and the V
87 registers become pseudo registers. */
89{
90 AARCH64_X0_REGNUM, /* First integer register. */
91 AARCH64_FP_REGNUM = AARCH64_X0_REGNUM + 29, /* Frame register, if used. */
92 AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30, /* Return address. */
93 AARCH64_SP_REGNUM, /* Stack pointer. */
94 AARCH64_PC_REGNUM, /* Program counter. */
95 AARCH64_CPSR_REGNUM, /* Current Program Status Register. */
96 AARCH64_V0_REGNUM, /* First fp/vec register. */
97 AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */
98 AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */
99 AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM, /* Last SVE Z register. */
100 AARCH64_FPSR_REGNUM, /* Floating Point Status Register. */
101 AARCH64_FPCR_REGNUM, /* Floating Point Control Register. */
102 AARCH64_SVE_P0_REGNUM, /* First SVE predicate register. */
103 AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15, /* Last SVE predicate
104 register. */
105 AARCH64_SVE_FFR_REGNUM, /* SVE First Fault Register. */
106 AARCH64_SVE_VG_REGNUM, /* SVE Vector Granule. */
107
108 /* Other useful registers. */
113
114/* Sizes of various AArch64 registers. */
115#define AARCH64_TLS_REGISTER_SIZE 8
116#define V_REGISTER_SIZE 16
117
118/* PAC-related constants. */
119/* Bit 55 is used to select between a kernel-space and user-space address. */
120#define VA_RANGE_SELECT_BIT_MASK 0x80000000000000ULL
121/* Mask with 1's in bits 55~63, used to remove the top byte of pointers
122 (Top Byte Ignore). */
123#define AARCH64_TOP_BITS_MASK 0xff80000000000000ULL
124
125/* Pseudo register base numbers. */
126#define AARCH64_Q0_REGNUM 0
127#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
128#define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
129#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
130#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
131#define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32)
132
133#define AARCH64_PAUTH_DMASK_REGNUM(pauth_reg_base) (pauth_reg_base)
134#define AARCH64_PAUTH_CMASK_REGNUM(pauth_reg_base) (pauth_reg_base + 1)
135#define AARCH64_PAUTH_REGS_SIZE (16)
136
137#define AARCH64_X_REGS_NUM 31
138#define AARCH64_V_REGS_NUM 32
139#define AARCH64_SVE_Z_REGS_NUM AARCH64_V_REGS_NUM
140#define AARCH64_SVE_P_REGS_NUM 16
141#define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1
142#define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1
143
144/* There are a number of ways of expressing the current SVE vector size:
145
146 VL : Vector Length.
147 The number of bytes in an SVE Z register.
148 VQ : Vector Quotient.
149 The number of 128bit chunks in an SVE Z register.
150 VG : Vector Granule.
151 The number of 64bit chunks in an SVE Z register. */
152
153#define sve_vg_from_vl(vl) ((vl) / 8)
154#define sve_vl_from_vg(vg) ((vg) * 8)
155#ifndef sve_vq_from_vl
156#define sve_vq_from_vl(vl) ((vl) / 0x10)
157#endif
158#ifndef sve_vl_from_vq
159#define sve_vl_from_vq(vq) ((vq) * 0x10)
160#endif
161#define sve_vq_from_vg(vg) (sve_vq_from_vl (sve_vl_from_vg (vg)))
162#define sve_vg_from_vq(vq) (sve_vg_from_vl (sve_vl_from_vq (vq)))
163
164
165/* Maximum supported VQ value. Increase if required. */
166#define AARCH64_MAX_SVE_VQ 16
167
168#endif /* ARCH_AARCH64_H */
aarch64_regnum
Definition: aarch64.h:89
@ AARCH64_SVE_FFR_REGNUM
Definition: aarch64.h:105
@ AARCH64_FP_REGNUM
Definition: aarch64.h:91
@ AARCH64_PC_REGNUM
Definition: aarch64.h:94
@ AARCH64_CPSR_REGNUM
Definition: aarch64.h:95
@ AARCH64_SP_REGNUM
Definition: aarch64.h:93
@ AARCH64_STRUCT_RETURN_REGNUM
Definition: aarch64.h:110
@ AARCH64_LAST_V_ARG_REGNUM
Definition: aarch64.h:111
@ AARCH64_SVE_VG_REGNUM
Definition: aarch64.h:106
@ AARCH64_SVE_Z0_REGNUM
Definition: aarch64.h:98
@ AARCH64_SVE_Z31_REGNUM
Definition: aarch64.h:99
@ AARCH64_V31_REGNUM
Definition: aarch64.h:97
@ AARCH64_FPSR_REGNUM
Definition: aarch64.h:100
@ AARCH64_SVE_P0_REGNUM
Definition: aarch64.h:102
@ AARCH64_FPCR_REGNUM
Definition: aarch64.h:101
@ AARCH64_LR_REGNUM
Definition: aarch64.h:92
@ AARCH64_X0_REGNUM
Definition: aarch64.h:90
@ AARCH64_SVE_P15_REGNUM
Definition: aarch64.h:103
@ AARCH64_V0_REGNUM
Definition: aarch64.h:96
@ AARCH64_LAST_X_ARG_REGNUM
Definition: aarch64.h:109
CORE_ADDR aarch64_remove_top_bits(CORE_ADDR pointer, CORE_ADDR mask)
Definition: aarch64.c:66
target_desc * aarch64_create_target_description(const aarch64_features &features)
Definition: aarch64.c:32
CORE_ADDR aarch64_mask_from_pac_registers(const CORE_ADDR cmask, const CORE_ADDR dmask)
Definition: aarch64.c:85
bool operator==(const aarch64_features &lhs, const aarch64_features &rhs)
Definition: aarch64.h:41
Definition: aarch64.h:50
uint64_t vq
Definition: aarch64.h:32
uint8_t tls
Definition: aarch64.h:38
std::size_t operator()(const aarch64_features &features) const noexcept
Definition: aarch64.h:54