GDB (xrefs)
Loading...
Searching...
No Matches
/tmp/gdb-13.1/gdb/i386-tdep.c
Go to the documentation of this file.
1/* Intel 386 target-dependent stuff.
2
3 Copyright (C) 1988-2023 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "opcode/i386.h"
22#include "arch-utils.h"
23#include "command.h"
24#include "dummy-frame.h"
25#include "dwarf2/frame.h"
26#include "frame.h"
27#include "frame-base.h"
28#include "frame-unwind.h"
29#include "inferior.h"
30#include "infrun.h"
31#include "gdbcmd.h"
32#include "gdbcore.h"
33#include "gdbtypes.h"
34#include "objfiles.h"
35#include "osabi.h"
36#include "regcache.h"
37#include "reggroups.h"
38#include "regset.h"
39#include "symfile.h"
40#include "symtab.h"
41#include "target.h"
42#include "target-float.h"
43#include "value.h"
44#include "dis-asm.h"
45#include "disasm.h"
46#include "remote.h"
47#include "i386-tdep.h"
48#include "i387-tdep.h"
49#include "gdbsupport/x86-xstate.h"
50#include "x86-tdep.h"
51#include "expop.h"
52
53#include "record.h"
54#include "record-full.h"
55#include "target-descriptions.h"
56#include "arch/i386.h"
57
58#include "ax.h"
59#include "ax-gdb.h"
60
61#include "stap-probe.h"
62#include "user-regs.h"
63#include "cli/cli-utils.h"
64#include "expression.h"
65#include "parser-defs.h"
66#include <ctype.h>
67#include <algorithm>
68#include <unordered_set>
69#include "producer.h"
70#include "infcall.h"
71#include "maint.h"
72
73/* Register names. */
74
75static const char * const i386_register_names[] =
76{
77 "eax", "ecx", "edx", "ebx",
78 "esp", "ebp", "esi", "edi",
79 "eip", "eflags", "cs", "ss",
80 "ds", "es", "fs", "gs",
81 "st0", "st1", "st2", "st3",
82 "st4", "st5", "st6", "st7",
83 "fctrl", "fstat", "ftag", "fiseg",
84 "fioff", "foseg", "fooff", "fop",
85 "xmm0", "xmm1", "xmm2", "xmm3",
86 "xmm4", "xmm5", "xmm6", "xmm7",
87 "mxcsr"
88};
89
90static const char * const i386_zmm_names[] =
91{
92 "zmm0", "zmm1", "zmm2", "zmm3",
93 "zmm4", "zmm5", "zmm6", "zmm7"
94};
95
96static const char * const i386_zmmh_names[] =
97{
98 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
99 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100};
101
102static const char * const i386_k_names[] =
103{
104 "k0", "k1", "k2", "k3",
105 "k4", "k5", "k6", "k7"
106};
107
108static const char * const i386_ymm_names[] =
109{
110 "ymm0", "ymm1", "ymm2", "ymm3",
111 "ymm4", "ymm5", "ymm6", "ymm7",
112};
113
114static const char * const i386_ymmh_names[] =
115{
116 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
117 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118};
119
120static const char * const i386_mpx_names[] =
121{
122 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123};
124
125static const char * const i386_pkeys_names[] =
126{
127 "pkru"
128};
129
130/* Register names for MPX pseudo-registers. */
131
132static const char * const i386_bnd_names[] =
133{
134 "bnd0", "bnd1", "bnd2", "bnd3"
135};
136
137/* Register names for MMX pseudo-registers. */
138
139static const char * const i386_mmx_names[] =
140{
141 "mm0", "mm1", "mm2", "mm3",
142 "mm4", "mm5", "mm6", "mm7"
143};
144
145/* Register names for byte pseudo-registers. */
146
147static const char * const i386_byte_names[] =
148{
149 "al", "cl", "dl", "bl",
150 "ah", "ch", "dh", "bh"
151};
152
153/* Register names for word pseudo-registers. */
154
155static const char * const i386_word_names[] =
156{
157 "ax", "cx", "dx", "bx",
158 "", "bp", "si", "di"
159};
160
161/* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
162 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
163 we have 16 upper ZMM regs that have to be handled differently. */
164
165const int num_lower_zmm_regs = 16;
166
167/* MMX register? */
168
169static int
171{
172 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
173 int mm0_regnum = tdep->mm0_regnum;
174
175 if (mm0_regnum < 0)
176 return 0;
177
178 regnum -= mm0_regnum;
179 return regnum >= 0 && regnum < tdep->num_mmx_regs;
180}
181
182/* Byte register? */
183
184int
186{
187 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
188
189 regnum -= tdep->al_regnum;
190 return regnum >= 0 && regnum < tdep->num_byte_regs;
191}
192
193/* Word register? */
194
195int
197{
198 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
199
200 regnum -= tdep->ax_regnum;
201 return regnum >= 0 && regnum < tdep->num_word_regs;
202}
203
204/* Dword register? */
205
206int
208{
209 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
210 int eax_regnum = tdep->eax_regnum;
211
212 if (eax_regnum < 0)
213 return 0;
214
215 regnum -= eax_regnum;
216 return regnum >= 0 && regnum < tdep->num_dword_regs;
217}
218
219/* AVX512 register? */
220
221int
223{
224 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
225 int zmm0h_regnum = tdep->zmm0h_regnum;
226
227 if (zmm0h_regnum < 0)
228 return 0;
229
230 regnum -= zmm0h_regnum;
231 return regnum >= 0 && regnum < tdep->num_zmm_regs;
232}
233
234int
236{
237 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
238 int zmm0_regnum = tdep->zmm0_regnum;
239
240 if (zmm0_regnum < 0)
241 return 0;
242
243 regnum -= zmm0_regnum;
244 return regnum >= 0 && regnum < tdep->num_zmm_regs;
245}
246
247int
249{
250 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
251 int k0_regnum = tdep->k0_regnum;
252
253 if (k0_regnum < 0)
254 return 0;
255
256 regnum -= k0_regnum;
257 return regnum >= 0 && regnum < I387_NUM_K_REGS;
258}
259
260static int
262{
263 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
264 int ymm0h_regnum = tdep->ymm0h_regnum;
265
266 if (ymm0h_regnum < 0)
267 return 0;
268
269 regnum -= ymm0h_regnum;
270 return regnum >= 0 && regnum < tdep->num_ymm_regs;
271}
272
273/* AVX register? */
274
275int
277{
278 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
279 int ymm0_regnum = tdep->ymm0_regnum;
280
281 if (ymm0_regnum < 0)
282 return 0;
283
284 regnum -= ymm0_regnum;
285 return regnum >= 0 && regnum < tdep->num_ymm_regs;
286}
287
288static int
290{
291 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
292 int ymm16h_regnum = tdep->ymm16h_regnum;
293
294 if (ymm16h_regnum < 0)
295 return 0;
296
297 regnum -= ymm16h_regnum;
298 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
299}
300
301int
303{
304 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
305 int ymm16_regnum = tdep->ymm16_regnum;
306
307 if (ymm16_regnum < 0)
308 return 0;
309
310 regnum -= ymm16_regnum;
311 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
312}
313
314/* BND register? */
315
316int
318{
319 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
320 int bnd0_regnum = tdep->bnd0_regnum;
321
322 if (bnd0_regnum < 0)
323 return 0;
324
325 regnum -= bnd0_regnum;
326 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
327}
328
329/* SSE register? */
330
331int
333{
334 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
335 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
336
337 if (num_xmm_regs == 0)
338 return 0;
339
340 regnum -= I387_XMM0_REGNUM (tdep);
341 return regnum >= 0 && regnum < num_xmm_regs;
342}
343
344/* XMM_512 register? */
345
346int
348{
349 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
350 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
351
352 if (num_xmm_avx512_regs == 0)
353 return 0;
354
355 regnum -= I387_XMM16_REGNUM (tdep);
356 return regnum >= 0 && regnum < num_xmm_avx512_regs;
357}
358
359static int
361{
362 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
363
364 if (I387_NUM_XMM_REGS (tdep) == 0)
365 return 0;
366
367 return (regnum == I387_MXCSR_REGNUM (tdep));
368}
369
370/* FP register? */
371
372int
374{
375 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
376
377 if (I387_ST0_REGNUM (tdep) < 0)
378 return 0;
379
380 return (I387_ST0_REGNUM (tdep) <= regnum
381 && regnum < I387_FCTRL_REGNUM (tdep));
382}
383
384int
386{
387 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
388
389 if (I387_ST0_REGNUM (tdep) < 0)
390 return 0;
391
392 return (I387_FCTRL_REGNUM (tdep) <= regnum
393 && regnum < I387_XMM0_REGNUM (tdep));
394}
395
396/* BNDr (raw) register? */
397
398static int
400{
401 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
402
403 if (I387_BND0R_REGNUM (tdep) < 0)
404 return 0;
405
406 regnum -= tdep->bnd0r_regnum;
407 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
408}
409
410/* BND control register? */
411
412static int
414{
415 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
416
417 if (I387_BNDCFGU_REGNUM (tdep) < 0)
418 return 0;
419
420 regnum -= I387_BNDCFGU_REGNUM (tdep);
421 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
422}
423
424/* PKRU register? */
425
426bool
428{
429 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
430 int pkru_regnum = tdep->pkru_regnum;
431
432 if (pkru_regnum < 0)
433 return false;
434
435 regnum -= pkru_regnum;
436 return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS;
437}
438
439/* Return the name of register REGNUM, or the empty string if it is
440 an anonymous register. */
441
442static const char *
444{
445 /* Hide the upper YMM registers. */
447 return "";
448
449 /* Hide the upper YMM16-31 registers. */
451 return "";
452
453 /* Hide the upper ZMM registers. */
455 return "";
456
458}
459
460/* Return the name of register REGNUM. */
461
462const char *
464{
465 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
467 return i386_bnd_names[regnum - tdep->bnd0_regnum];
469 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
470 else if (i386_ymm_regnum_p (gdbarch, regnum))
471 return i386_ymm_names[regnum - tdep->ymm0_regnum];
472 else if (i386_zmm_regnum_p (gdbarch, regnum))
473 return i386_zmm_names[regnum - tdep->zmm0_regnum];
475 return i386_byte_names[regnum - tdep->al_regnum];
477 return i386_word_names[regnum - tdep->ax_regnum];
478
479 internal_error (_("invalid regnum"));
480}
481
482/* Convert a dbx register number REG to the appropriate register
483 number used by GDB. */
484
485static int
487{
488 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
489
490 /* This implements what GCC calls the "default" register map
491 (dbx_register_map[]). */
492
493 if (reg >= 0 && reg <= 7)
494 {
495 /* General-purpose registers. The debug info calls %ebp
496 register 4, and %esp register 5. */
497 if (reg == 4)
498 return 5;
499 else if (reg == 5)
500 return 4;
501 else return reg;
502 }
503 else if (reg >= 12 && reg <= 19)
504 {
505 /* Floating-point registers. */
506 return reg - 12 + I387_ST0_REGNUM (tdep);
507 }
508 else if (reg >= 21 && reg <= 28)
509 {
510 /* SSE registers. */
511 int ymm0_regnum = tdep->ymm0_regnum;
512
513 if (ymm0_regnum >= 0
514 && i386_xmm_regnum_p (gdbarch, reg))
515 return reg - 21 + ymm0_regnum;
516 else
517 return reg - 21 + I387_XMM0_REGNUM (tdep);
518 }
519 else if (reg >= 29 && reg <= 36)
520 {
521 /* MMX registers. */
522 return reg - 29 + I387_MM0_REGNUM (tdep);
523 }
524
525 /* This will hopefully provoke a warning. */
527}
528
529/* Convert SVR4 DWARF register number REG to the appropriate register number
530 used by GDB. */
531
532static int
534{
535 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
536
537 /* This implements the GCC register map that tries to be compatible
538 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
539
540 /* The SVR4 register numbering includes %eip and %eflags, and
541 numbers the floating point registers differently. */
542 if (reg >= 0 && reg <= 9)
543 {
544 /* General-purpose registers. */
545 return reg;
546 }
547 else if (reg >= 11 && reg <= 18)
548 {
549 /* Floating-point registers. */
550 return reg - 11 + I387_ST0_REGNUM (tdep);
551 }
552 else if (reg >= 21 && reg <= 36)
553 {
554 /* The SSE and MMX registers have the same numbers as with dbx. */
555 return i386_dbx_reg_to_regnum (gdbarch, reg);
556 }
557
558 switch (reg)
559 {
560 case 37: return I387_FCTRL_REGNUM (tdep);
561 case 38: return I387_FSTAT_REGNUM (tdep);
562 case 39: return I387_MXCSR_REGNUM (tdep);
563 case 40: return I386_ES_REGNUM;
564 case 41: return I386_CS_REGNUM;
565 case 42: return I386_SS_REGNUM;
566 case 43: return I386_DS_REGNUM;
567 case 44: return I386_FS_REGNUM;
568 case 45: return I386_GS_REGNUM;
569 }
570
571 return -1;
572}
573
574/* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
575 num_regs + num_pseudo_regs for other debug formats. */
576
577int
579{
581
582 if (regnum == -1)
584 return regnum;
585}
586
587
588
589/* This is the variable that is set with "set disassembly-flavor", and
590 its legitimate values. */
591static const char att_flavor[] = "att";
592static const char intel_flavor[] = "intel";
593static const char *const valid_flavors[] =
594{
597 NULL
598};
599static const char *disassembly_flavor = att_flavor;
600
601
602/* Use the program counter to determine the contents and size of a
603 breakpoint instruction. Return a pointer to a string of bytes that
604 encode a breakpoint instruction, store the length of the string in
605 *LEN and optionally adjust *PC to point to the correct memory
606 location for inserting the breakpoint.
607
608 On the i386 we have a single breakpoint that fits in a single byte
609 and can be inserted anywhere.
610
611 This function is 64-bit safe. */
612
613constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */
614
615typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint;
616
617
618/* Displaced instruction handling. */
619
620/* Skip the legacy instruction prefixes in INSN.
621 Not all prefixes are valid for any particular insn
622 but we needn't care, the insn will fault if it's invalid.
623 The result is a pointer to the first opcode byte,
624 or NULL if we run off the end of the buffer. */
625
626static gdb_byte *
627i386_skip_prefixes (gdb_byte *insn, size_t max_len)
628{
629 gdb_byte *end = insn + max_len;
630
631 while (insn < end)
632 {
633 switch (*insn)
634 {
635 case DATA_PREFIX_OPCODE:
636 case ADDR_PREFIX_OPCODE:
637 case CS_PREFIX_OPCODE:
638 case DS_PREFIX_OPCODE:
639 case ES_PREFIX_OPCODE:
640 case FS_PREFIX_OPCODE:
641 case GS_PREFIX_OPCODE:
642 case SS_PREFIX_OPCODE:
643 case LOCK_PREFIX_OPCODE:
644 case REPE_PREFIX_OPCODE:
645 case REPNE_PREFIX_OPCODE:
646 ++insn;
647 continue;
648 default:
649 return insn;
650 }
651 }
652
653 return NULL;
654}
655
656static int
657i386_absolute_jmp_p (const gdb_byte *insn)
658{
659 /* jmp far (absolute address in operand). */
660 if (insn[0] == 0xea)
661 return 1;
662
663 if (insn[0] == 0xff)
664 {
665 /* jump near, absolute indirect (/4). */
666 if ((insn[1] & 0x38) == 0x20)
667 return 1;
668
669 /* jump far, absolute indirect (/5). */
670 if ((insn[1] & 0x38) == 0x28)
671 return 1;
672 }
673
674 return 0;
675}
676
677/* Return non-zero if INSN is a jump, zero otherwise. */
678
679static int
680i386_jmp_p (const gdb_byte *insn)
681{
682 /* jump short, relative. */
683 if (insn[0] == 0xeb)
684 return 1;
685
686 /* jump near, relative. */
687 if (insn[0] == 0xe9)
688 return 1;
689
690 return i386_absolute_jmp_p (insn);
691}
692
693static int
694i386_absolute_call_p (const gdb_byte *insn)
695{
696 /* call far, absolute. */
697 if (insn[0] == 0x9a)
698 return 1;
699
700 if (insn[0] == 0xff)
701 {
702 /* Call near, absolute indirect (/2). */
703 if ((insn[1] & 0x38) == 0x10)
704 return 1;
705
706 /* Call far, absolute indirect (/3). */
707 if ((insn[1] & 0x38) == 0x18)
708 return 1;
709 }
710
711 return 0;
712}
713
714static int
715i386_ret_p (const gdb_byte *insn)
716{
717 switch (insn[0])
718 {
719 case 0xc2: /* ret near, pop N bytes. */
720 case 0xc3: /* ret near */
721 case 0xca: /* ret far, pop N bytes. */
722 case 0xcb: /* ret far */
723 case 0xcf: /* iret */
724 return 1;
725
726 default:
727 return 0;
728 }
729}
730
731static int
732i386_call_p (const gdb_byte *insn)
733{
734 if (i386_absolute_call_p (insn))
735 return 1;
736
737 /* call near, relative. */
738 if (insn[0] == 0xe8)
739 return 1;
740
741 return 0;
742}
743
744/* Return non-zero if INSN is a system call, and set *LENGTHP to its
745 length in bytes. Otherwise, return zero. */
746
747static int
748i386_syscall_p (const gdb_byte *insn, int *lengthp)
749{
750 /* Is it 'int $0x80'? */
751 if ((insn[0] == 0xcd && insn[1] == 0x80)
752 /* Or is it 'sysenter'? */
753 || (insn[0] == 0x0f && insn[1] == 0x34)
754 /* Or is it 'syscall'? */
755 || (insn[0] == 0x0f && insn[1] == 0x05))
756 {
757 *lengthp = 2;
758 return 1;
759 }
760
761 return 0;
762}
763
764/* The gdbarch insn_is_call method. */
765
766static int
767i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
768{
769 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
770
771 read_code (addr, buf, I386_MAX_INSN_LEN);
772 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
773
774 return i386_call_p (insn);
775}
776
777/* The gdbarch insn_is_ret method. */
778
779static int
780i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
781{
782 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
783
784 read_code (addr, buf, I386_MAX_INSN_LEN);
785 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
786
787 return i386_ret_p (insn);
788}
789
790/* The gdbarch insn_is_jump method. */
791
792static int
793i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
794{
795 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
796
797 read_code (addr, buf, I386_MAX_INSN_LEN);
798 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
799
800 return i386_jmp_p (insn);
801}
802
803/* Some kernels may run one past a syscall insn, so we have to cope. */
804
807 CORE_ADDR from, CORE_ADDR to,
808 struct regcache *regs)
809{
810 size_t len = gdbarch_max_insn_length (gdbarch);
811 std::unique_ptr<i386_displaced_step_copy_insn_closure> closure
813 gdb_byte *buf = closure->buf.data ();
814
815 read_memory (from, buf, len);
816
817 /* GDB may get control back after the insn after the syscall.
818 Presumably this is a kernel bug.
819 If this is a syscall, make sure there's a nop afterwards. */
820 {
821 int syscall_length;
822 gdb_byte *insn;
823
824 insn = i386_skip_prefixes (buf, len);
825 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
826 insn[syscall_length] = NOP_OPCODE;
827 }
828
829 write_memory (to, buf, len);
830
831 displaced_debug_printf ("%s->%s: %s",
832 paddress (gdbarch, from), paddress (gdbarch, to),
833 displaced_step_dump_bytes (buf, len).c_str ());
834
835 /* This is a work around for a problem with g++ 4.8. */
836 return displaced_step_copy_insn_closure_up (closure.release ());
837}
838
839/* Fix up the state of registers and memory after having single-stepped
840 a displaced instruction. */
841
842void
844 struct displaced_step_copy_insn_closure *closure_,
845 CORE_ADDR from, CORE_ADDR to,
846 struct regcache *regs)
847{
848 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
849
850 /* The offset we applied to the instruction's address.
851 This could well be negative (when viewed as a signed 32-bit
852 value), but ULONGEST won't reflect that, so take care when
853 applying it. */
854 ULONGEST insn_offset = to - from;
855
858 gdb_byte *insn = closure->buf.data ();
859 /* The start of the insn, needed in case we see some prefixes. */
860 gdb_byte *insn_start = insn;
861
862 displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
863 paddress (gdbarch, from), paddress (gdbarch, to),
864 insn[0], insn[1]);
865
866 /* The list of issues to contend with here is taken from
867 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
868 Yay for Free Software! */
869
870 /* Relocate the %eip, if necessary. */
871
872 /* The instruction recognizers we use assume any leading prefixes
873 have been skipped. */
874 {
875 /* This is the size of the buffer in closure. */
876 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
877 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
878 /* If there are too many prefixes, just ignore the insn.
879 It will fault when run. */
880 if (opcode != NULL)
881 insn = opcode;
882 }
883
884 /* Except in the case of absolute or indirect jump or call
885 instructions, or a return instruction, the new eip is relative to
886 the displaced instruction; make it relative. Well, signal
887 handler returns don't need relocation either, but we use the
888 value of %eip to recognize those; see below. */
889 if (! i386_absolute_jmp_p (insn)
890 && ! i386_absolute_call_p (insn)
891 && ! i386_ret_p (insn))
892 {
893 ULONGEST orig_eip;
894 int insn_len;
895
897
898 /* A signal trampoline system call changes the %eip, resuming
899 execution of the main program after the signal handler has
900 returned. That makes them like 'return' instructions; we
901 shouldn't relocate %eip.
902
903 But most system calls don't, and we do need to relocate %eip.
904
905 Our heuristic for distinguishing these cases: if stepping
906 over the system call instruction left control directly after
907 the instruction, the we relocate --- control almost certainly
908 doesn't belong in the displaced copy. Otherwise, we assume
909 the instruction has put control where it belongs, and leave
910 it unrelocated. Goodness help us if there are PC-relative
911 system calls. */
912 if (i386_syscall_p (insn, &insn_len)
913 && orig_eip != to + (insn - insn_start) + insn_len
914 /* GDB can get control back after the insn after the syscall.
915 Presumably this is a kernel bug.
916 i386_displaced_step_copy_insn ensures its a nop,
917 we add one to the length for it. */
918 && orig_eip != to + (insn - insn_start) + insn_len + 1)
919 displaced_debug_printf ("syscall changed %%eip; not relocating");
920 else
921 {
922 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
923
924 /* If we just stepped over a breakpoint insn, we don't backup
925 the pc on purpose; this is to match behaviour without
926 stepping. */
927
929
930 displaced_debug_printf ("relocated %%eip from %s to %s",
931 paddress (gdbarch, orig_eip),
932 paddress (gdbarch, eip));
933 }
934 }
935
936 /* If the instruction was PUSHFL, then the TF bit will be set in the
937 pushed value, and should be cleared. We'll leave this for later,
938 since GDB already messes up the TF flag when stepping over a
939 pushfl. */
940
941 /* If the instruction was a call, the return address now atop the
942 stack is the address following the copied instruction. We need
943 to make it the address following the original instruction. */
944 if (i386_call_p (insn))
945 {
946 ULONGEST esp;
947 ULONGEST retaddr;
948 const ULONGEST retaddr_len = 4;
949
951 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
952 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
953 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
954
955 displaced_debug_printf ("relocated return addr at %s to %s",
956 paddress (gdbarch, esp),
957 paddress (gdbarch, retaddr));
958 }
959}
960
961static void
962append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
963{
964 target_write_memory (*to, buf, len);
965 *to += len;
966}
967
968static void
970 CORE_ADDR *to, CORE_ADDR oldloc)
971{
972 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
973 gdb_byte buf[I386_MAX_INSN_LEN];
974 int offset = 0, rel32, newrel;
975 int insn_length;
976 gdb_byte *insn = buf;
977
978 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
979
980 insn_length = gdb_buffered_insn_length (gdbarch, insn,
981 I386_MAX_INSN_LEN, oldloc);
982
983 /* Get past the prefixes. */
984 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
985
986 /* Adjust calls with 32-bit relative addresses as push/jump, with
987 the address pushed being the location where the original call in
988 the user program would return to. */
989 if (insn[0] == 0xe8)
990 {
991 gdb_byte push_buf[16];
992 unsigned int ret_addr;
993
994 /* Where "ret" in the original code will return to. */
995 ret_addr = oldloc + insn_length;
996 push_buf[0] = 0x68; /* pushq $... */
997 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
998 /* Push the push. */
999 append_insns (to, 5, push_buf);
1000
1001 /* Convert the relative call to a relative jump. */
1002 insn[0] = 0xe9;
1003
1004 /* Adjust the destination offset. */
1005 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1006 newrel = (oldloc - *to) + rel32;
1007 store_signed_integer (insn + 1, 4, byte_order, newrel);
1008
1009 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1010 hex_string (rel32), paddress (gdbarch, oldloc),
1011 hex_string (newrel), paddress (gdbarch, *to));
1012
1013 /* Write the adjusted jump into its displaced location. */
1014 append_insns (to, 5, insn);
1015 return;
1016 }
1017
1018 /* Adjust jumps with 32-bit relative addresses. Calls are already
1019 handled above. */
1020 if (insn[0] == 0xe9)
1021 offset = 1;
1022 /* Adjust conditional jumps. */
1023 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1024 offset = 2;
1025
1026 if (offset)
1027 {
1028 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1029 newrel = (oldloc - *to) + rel32;
1030 store_signed_integer (insn + offset, 4, byte_order, newrel);
1031 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1032 hex_string (rel32), paddress (gdbarch, oldloc),
1033 hex_string (newrel), paddress (gdbarch, *to));
1034 }
1035
1036 /* Write the adjusted instructions into their displaced
1037 location. */
1038 append_insns (to, insn_length, buf);
1039}
1040
1041
1042#ifdef I386_REGNO_TO_SYMMETRY
1043#error "The Sequent Symmetry is no longer supported."
1044#endif
1045
1046/* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1047 and %esp "belong" to the calling function. Therefore these
1048 registers should be saved if they're going to be modified. */
1049
1050/* The maximum number of saved registers. This should include all
1051 registers mentioned above, and %eip. */
1052#define I386_NUM_SAVED_REGS I386_NUM_GREGS
1053
1055{
1056 /* Base address. */
1057 CORE_ADDR base;
1059 LONGEST sp_offset;
1060 CORE_ADDR pc;
1061
1062 /* Saved registers. */
1064 CORE_ADDR saved_sp;
1067
1068 /* Stack space reserved for local variables. */
1070};
1071
1072/* Allocate and initialize a frame cache. */
1073
1074static struct i386_frame_cache *
1076{
1077 struct i386_frame_cache *cache;
1078 int i;
1079
1080 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1081
1082 /* Base address. */
1083 cache->base_p = 0;
1084 cache->base = 0;
1085 cache->sp_offset = -4;
1086 cache->pc = 0;
1087
1088 /* Saved registers. We initialize these to -1 since zero is a valid
1089 offset (that's where %ebp is supposed to be stored). */
1090 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1091 cache->saved_regs[i] = -1;
1092 cache->saved_sp = 0;
1093 cache->saved_sp_reg = -1;
1094 cache->pc_in_eax = 0;
1095
1096 /* Frameless until proven otherwise. */
1097 cache->locals = -1;
1098
1099 return cache;
1100}
1101
1102/* If the instruction at PC is a jump, return the address of its
1103 target. Otherwise, return PC. */
1104
1105static CORE_ADDR
1107{
1108 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1109 gdb_byte op;
1110 long delta = 0;
1111 int data16 = 0;
1112
1113 if (target_read_code (pc, &op, 1))
1114 return pc;
1115
1116 if (op == 0x66)
1117 {
1118 data16 = 1;
1119
1120 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1121 }
1122
1123 switch (op)
1124 {
1125 case 0xe9:
1126 /* Relative jump: if data16 == 0, disp32, else disp16. */
1127 if (data16)
1128 {
1129 delta = read_memory_integer (pc + 2, 2, byte_order);
1130
1131 /* Include the size of the jmp instruction (including the
1132 0x66 prefix). */
1133 delta += 4;
1134 }
1135 else
1136 {
1137 delta = read_memory_integer (pc + 1, 4, byte_order);
1138
1139 /* Include the size of the jmp instruction. */
1140 delta += 5;
1141 }
1142 break;
1143 case 0xeb:
1144 /* Relative jump, disp8 (ignore data16). */
1145 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1146
1147 delta += data16 + 2;
1148 break;
1149 }
1150
1151 return pc + delta;
1152}
1153
1154/* Check whether PC points at a prologue for a function returning a
1155 structure or union. If so, it updates CACHE and returns the
1156 address of the first instruction after the code sequence that
1157 removes the "hidden" argument from the stack or CURRENT_PC,
1158 whichever is smaller. Otherwise, return PC. */
1159
1160static CORE_ADDR
1161i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1162 struct i386_frame_cache *cache)
1163{
1164 /* Functions that return a structure or union start with:
1165
1166 popl %eax 0x58
1167 xchgl %eax, (%esp) 0x87 0x04 0x24
1168 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1169
1170 (the System V compiler puts out the second `xchg' instruction,
1171 and the assembler doesn't try to optimize it, so the 'sib' form
1172 gets generated). This sequence is used to get the address of the
1173 return buffer for a function that returns a structure. */
1174 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1175 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1176 gdb_byte buf[4];
1177 gdb_byte op;
1178
1179 if (current_pc <= pc)
1180 return pc;
1181
1182 if (target_read_code (pc, &op, 1))
1183 return pc;
1184
1185 if (op != 0x58) /* popl %eax */
1186 return pc;
1187
1188 if (target_read_code (pc + 1, buf, 4))
1189 return pc;
1190
1191 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1192 return pc;
1193
1194 if (current_pc == pc)
1195 {
1196 cache->sp_offset += 4;
1197 return current_pc;
1198 }
1199
1200 if (current_pc == pc + 1)
1201 {
1202 cache->pc_in_eax = 1;
1203 return current_pc;
1204 }
1205
1206 if (buf[1] == proto1[1])
1207 return pc + 4;
1208 else
1209 return pc + 5;
1210}
1211
1212static CORE_ADDR
1214{
1215 /* A function may start with
1216
1217 pushl constant
1218 call _probe
1219 addl $4, %esp
1220
1221 followed by
1222
1223 pushl %ebp
1224
1225 etc. */
1226 gdb_byte buf[8];
1227 gdb_byte op;
1228
1229 if (target_read_code (pc, &op, 1))
1230 return pc;
1231
1232 if (op == 0x68 || op == 0x6a)
1233 {
1234 int delta;
1235
1236 /* Skip past the `pushl' instruction; it has either a one-byte or a
1237 four-byte operand, depending on the opcode. */
1238 if (op == 0x68)
1239 delta = 5;
1240 else
1241 delta = 2;
1242
1243 /* Read the following 8 bytes, which should be `call _probe' (6
1244 bytes) followed by `addl $4,%esp' (2 bytes). */
1245 read_memory (pc + delta, buf, sizeof (buf));
1246 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1247 pc += delta + sizeof (buf);
1248 }
1249
1250 return pc;
1251}
1252
1253/* GCC 4.1 and later, can put code in the prologue to realign the
1254 stack pointer. Check whether PC points to such code, and update
1255 CACHE accordingly. Return the first instruction after the code
1256 sequence or CURRENT_PC, whichever is smaller. If we don't
1257 recognize the code, return PC. */
1258
1259static CORE_ADDR
1260i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1261 struct i386_frame_cache *cache)
1262{
1263 /* There are 2 code sequences to re-align stack before the frame
1264 gets set up:
1265
1266 1. Use a caller-saved saved register:
1267
1268 leal 4(%esp), %reg
1269 andl $-XXX, %esp
1270 pushl -4(%reg)
1271
1272 2. Use a callee-saved saved register:
1273
1274 pushl %reg
1275 leal 8(%esp), %reg
1276 andl $-XXX, %esp
1277 pushl -4(%reg)
1278
1279 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1280
1281 0x83 0xe4 0xf0 andl $-16, %esp
1282 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1283 */
1284
1285 gdb_byte buf[14];
1286 int reg;
1287 int offset, offset_and;
1288 static int regnums[8] = {
1289 I386_EAX_REGNUM, /* %eax */
1290 I386_ECX_REGNUM, /* %ecx */
1291 I386_EDX_REGNUM, /* %edx */
1292 I386_EBX_REGNUM, /* %ebx */
1293 I386_ESP_REGNUM, /* %esp */
1294 I386_EBP_REGNUM, /* %ebp */
1295 I386_ESI_REGNUM, /* %esi */
1296 I386_EDI_REGNUM /* %edi */
1297 };
1298
1299 if (target_read_code (pc, buf, sizeof buf))
1300 return pc;
1301
1302 /* Check caller-saved saved register. The first instruction has
1303 to be "leal 4(%esp), %reg". */
1304 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1305 {
1306 /* MOD must be binary 10 and R/M must be binary 100. */
1307 if ((buf[1] & 0xc7) != 0x44)
1308 return pc;
1309
1310 /* REG has register number. */
1311 reg = (buf[1] >> 3) & 7;
1312 offset = 4;
1313 }
1314 else
1315 {
1316 /* Check callee-saved saved register. The first instruction
1317 has to be "pushl %reg". */
1318 if ((buf[0] & 0xf8) != 0x50)
1319 return pc;
1320
1321 /* Get register. */
1322 reg = buf[0] & 0x7;
1323
1324 /* The next instruction has to be "leal 8(%esp), %reg". */
1325 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1326 return pc;
1327
1328 /* MOD must be binary 10 and R/M must be binary 100. */
1329 if ((buf[2] & 0xc7) != 0x44)
1330 return pc;
1331
1332 /* REG has register number. Registers in pushl and leal have to
1333 be the same. */
1334 if (reg != ((buf[2] >> 3) & 7))
1335 return pc;
1336
1337 offset = 5;
1338 }
1339
1340 /* Rigister can't be %esp nor %ebp. */
1341 if (reg == 4 || reg == 5)
1342 return pc;
1343
1344 /* The next instruction has to be "andl $-XXX, %esp". */
1345 if (buf[offset + 1] != 0xe4
1346 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1347 return pc;
1348
1349 offset_and = offset;
1350 offset += buf[offset] == 0x81 ? 6 : 3;
1351
1352 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1353 0xfc. REG must be binary 110 and MOD must be binary 01. */
1354 if (buf[offset] != 0xff
1355 || buf[offset + 2] != 0xfc
1356 || (buf[offset + 1] & 0xf8) != 0x70)
1357 return pc;
1358
1359 /* R/M has register. Registers in leal and pushl have to be the
1360 same. */
1361 if (reg != (buf[offset + 1] & 7))
1362 return pc;
1363
1364 if (current_pc > pc + offset_and)
1365 cache->saved_sp_reg = regnums[reg];
1366
1367 return std::min (pc + offset + 3, current_pc);
1368}
1369
1370/* Maximum instruction length we need to handle. */
1371#define I386_MAX_MATCHED_INSN_LEN 6
1372
1373/* Instruction description. */
1375{
1376 size_t len;
1379};
1380
1381/* Return whether instruction at PC matches PATTERN. */
1382
1383static int
1384i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1385{
1386 gdb_byte op;
1387
1388 if (target_read_code (pc, &op, 1))
1389 return 0;
1390
1391 if ((op & pattern.mask[0]) == pattern.insn[0])
1392 {
1393 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1394 int insn_matched = 1;
1395 size_t i;
1396
1397 gdb_assert (pattern.len > 1);
1398 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1399
1400 if (target_read_code (pc + 1, buf, pattern.len - 1))
1401 return 0;
1402
1403 for (i = 1; i < pattern.len; i++)
1404 {
1405 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1406 insn_matched = 0;
1407 }
1408 return insn_matched;
1409 }
1410 return 0;
1411}
1412
1413/* Search for the instruction at PC in the list INSN_PATTERNS. Return
1414 the first instruction description that matches. Otherwise, return
1415 NULL. */
1416
1417static struct i386_insn *
1418i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1419{
1420 struct i386_insn *pattern;
1421
1422 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1423 {
1424 if (i386_match_pattern (pc, *pattern))
1425 return pattern;
1426 }
1427
1428 return NULL;
1429}
1430
1431/* Return whether PC points inside a sequence of instructions that
1432 matches INSN_PATTERNS. */
1433
1434static int
1435i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1436{
1437 CORE_ADDR current_pc;
1438 int ix, i;
1439 struct i386_insn *insn;
1440
1441 insn = i386_match_insn (pc, insn_patterns);
1442 if (insn == NULL)
1443 return 0;
1444
1445 current_pc = pc;
1446 ix = insn - insn_patterns;
1447 for (i = ix - 1; i >= 0; i--)
1448 {
1449 current_pc -= insn_patterns[i].len;
1450
1451 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1452 return 0;
1453 }
1454
1455 current_pc = pc + insn->len;
1456 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1457 {
1458 if (!i386_match_pattern (current_pc, *insn))
1459 return 0;
1460
1461 current_pc += insn->len;
1462 }
1463
1464 return 1;
1465}
1466
1467/* Some special instructions that might be migrated by GCC into the
1468 part of the prologue that sets up the new stack frame. Because the
1469 stack frame hasn't been setup yet, no registers have been saved
1470 yet, and only the scratch registers %eax, %ecx and %edx can be
1471 touched. */
1472
1474{
1475 /* Check for `movb imm8, r' and `movl imm32, r'.
1476
1477 ??? Should we handle 16-bit operand-sizes here? */
1478
1479 /* `movb imm8, %al' and `movb imm8, %ah' */
1480 /* `movb imm8, %cl' and `movb imm8, %ch' */
1481 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1482 /* `movb imm8, %dl' and `movb imm8, %dh' */
1483 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1484 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1485 { 5, { 0xb8 }, { 0xfe } },
1486 /* `movl imm32, %edx' */
1487 { 5, { 0xba }, { 0xff } },
1488
1489 /* Check for `mov imm32, r32'. Note that there is an alternative
1490 encoding for `mov m32, %eax'.
1491
1492 ??? Should we handle SIB addressing here?
1493 ??? Should we handle 16-bit operand-sizes here? */
1494
1495 /* `movl m32, %eax' */
1496 { 5, { 0xa1 }, { 0xff } },
1497 /* `movl m32, %eax' and `mov; m32, %ecx' */
1498 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1499 /* `movl m32, %edx' */
1500 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1501
1502 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1503 Because of the symmetry, there are actually two ways to encode
1504 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1505 opcode bytes 0x31 and 0x33 for `xorl'. */
1506
1507 /* `subl %eax, %eax' */
1508 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1509 /* `subl %ecx, %ecx' */
1510 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1511 /* `subl %edx, %edx' */
1512 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1513 /* `xorl %eax, %eax' */
1514 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1515 /* `xorl %ecx, %ecx' */
1516 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1517 /* `xorl %edx, %edx' */
1518 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1519 { 0 }
1520};
1521
1522/* Check whether PC points to an endbr32 instruction. */
1523static CORE_ADDR
1524i386_skip_endbr (CORE_ADDR pc)
1525{
1526 static const gdb_byte endbr32[] = { 0xf3, 0x0f, 0x1e, 0xfb };
1527
1528 gdb_byte buf[sizeof (endbr32)];
1529
1530 /* Stop there if we can't read the code */
1531 if (target_read_code (pc, buf, sizeof (endbr32)))
1532 return pc;
1533
1534 /* If the instruction isn't an endbr32, stop */
1535 if (memcmp (buf, endbr32, sizeof (endbr32)) != 0)
1536 return pc;
1537
1538 return pc + sizeof (endbr32);
1539}
1540
1541/* Check whether PC points to a no-op instruction. */
1542static CORE_ADDR
1543i386_skip_noop (CORE_ADDR pc)
1544{
1545 gdb_byte op;
1546 int check = 1;
1547
1548 if (target_read_code (pc, &op, 1))
1549 return pc;
1550
1551 while (check)
1552 {
1553 check = 0;
1554 /* Ignore `nop' instruction. */
1555 if (op == 0x90)
1556 {
1557 pc += 1;
1558 if (target_read_code (pc, &op, 1))
1559 return pc;
1560 check = 1;
1561 }
1562 /* Ignore no-op instruction `mov %edi, %edi'.
1563 Microsoft system dlls often start with
1564 a `mov %edi,%edi' instruction.
1565 The 5 bytes before the function start are
1566 filled with `nop' instructions.
1567 This pattern can be used for hot-patching:
1568 The `mov %edi, %edi' instruction can be replaced by a
1569 near jump to the location of the 5 `nop' instructions
1570 which can be replaced by a 32-bit jump to anywhere
1571 in the 32-bit address space. */
1572
1573 else if (op == 0x8b)
1574 {
1575 if (target_read_code (pc + 1, &op, 1))
1576 return pc;
1577
1578 if (op == 0xff)
1579 {
1580 pc += 2;
1581 if (target_read_code (pc, &op, 1))
1582 return pc;
1583
1584 check = 1;
1585 }
1586 }
1587 }
1588 return pc;
1589}
1590
1591/* Check whether PC points at a code that sets up a new stack frame.
1592 If so, it updates CACHE and returns the address of the first
1593 instruction after the sequence that sets up the frame or LIMIT,
1594 whichever is smaller. If we don't recognize the code, return PC. */
1595
1596static CORE_ADDR
1598 CORE_ADDR pc, CORE_ADDR limit,
1599 struct i386_frame_cache *cache)
1600{
1601 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1602 struct i386_insn *insn;
1603 gdb_byte op;
1604 int skip = 0;
1605
1606 if (limit <= pc)
1607 return limit;
1608
1609 if (target_read_code (pc, &op, 1))
1610 return pc;
1611
1612 if (op == 0x55) /* pushl %ebp */
1613 {
1614 /* Take into account that we've executed the `pushl %ebp' that
1615 starts this instruction sequence. */
1616 cache->saved_regs[I386_EBP_REGNUM] = 0;
1617 cache->sp_offset += 4;
1618 pc++;
1619
1620 /* If that's all, return now. */
1621 if (limit <= pc)
1622 return limit;
1623
1624 /* Check for some special instructions that might be migrated by
1625 GCC into the prologue and skip them. At this point in the
1626 prologue, code should only touch the scratch registers %eax,
1627 %ecx and %edx, so while the number of possibilities is sheer,
1628 it is limited.
1629
1630 Make sure we only skip these instructions if we later see the
1631 `movl %esp, %ebp' that actually sets up the frame. */
1632 while (pc + skip < limit)
1633 {
1635 if (insn == NULL)
1636 break;
1637
1638 skip += insn->len;
1639 }
1640
1641 /* If that's all, return now. */
1642 if (limit <= pc + skip)
1643 return limit;
1644
1645 if (target_read_code (pc + skip, &op, 1))
1646 return pc + skip;
1647
1648 /* The i386 prologue looks like
1649
1650 push %ebp
1651 mov %esp,%ebp
1652 sub $0x10,%esp
1653
1654 and a different prologue can be generated for atom.
1655
1656 push %ebp
1657 lea (%esp),%ebp
1658 lea -0x10(%esp),%esp
1659
1660 We handle both of them here. */
1661
1662 switch (op)
1663 {
1664 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1665 case 0x8b:
1666 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1667 != 0xec)
1668 return pc;
1669 pc += (skip + 2);
1670 break;
1671 case 0x89:
1672 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1673 != 0xe5)
1674 return pc;
1675 pc += (skip + 2);
1676 break;
1677 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1678 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1679 != 0x242c)
1680 return pc;
1681 pc += (skip + 3);
1682 break;
1683 default:
1684 return pc;
1685 }
1686
1687 /* OK, we actually have a frame. We just don't know how large
1688 it is yet. Set its size to zero. We'll adjust it if
1689 necessary. We also now commit to skipping the special
1690 instructions mentioned before. */
1691 cache->locals = 0;
1692
1693 /* If that's all, return now. */
1694 if (limit <= pc)
1695 return limit;
1696
1697 /* Check for stack adjustment
1698
1699 subl $XXX, %esp
1700 or
1701 lea -XXX(%esp),%esp
1702
1703 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1704 reg, so we don't have to worry about a data16 prefix. */
1705 if (target_read_code (pc, &op, 1))
1706 return pc;
1707 if (op == 0x83)
1708 {
1709 /* `subl' with 8-bit immediate. */
1710 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1711 /* Some instruction starting with 0x83 other than `subl'. */
1712 return pc;
1713
1714 /* `subl' with signed 8-bit immediate (though it wouldn't
1715 make sense to be negative). */
1716 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1717 return pc + 3;
1718 }
1719 else if (op == 0x81)
1720 {
1721 /* Maybe it is `subl' with a 32-bit immediate. */
1722 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1723 /* Some instruction starting with 0x81 other than `subl'. */
1724 return pc;
1725
1726 /* It is `subl' with a 32-bit immediate. */
1727 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1728 return pc + 6;
1729 }
1730 else if (op == 0x8d)
1731 {
1732 /* The ModR/M byte is 0x64. */
1733 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1734 return pc;
1735 /* 'lea' with 8-bit displacement. */
1736 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1737 return pc + 4;
1738 }
1739 else
1740 {
1741 /* Some instruction other than `subl' nor 'lea'. */
1742 return pc;
1743 }
1744 }
1745 else if (op == 0xc8) /* enter */
1746 {
1747 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1748 return pc + 4;
1749 }
1750
1751 return pc;
1752}
1753
1754/* Check whether PC points at code that saves registers on the stack.
1755 If so, it updates CACHE and returns the address of the first
1756 instruction after the register saves or CURRENT_PC, whichever is
1757 smaller. Otherwise, return PC. */
1758
1759static CORE_ADDR
1760i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1761 struct i386_frame_cache *cache)
1762{
1763 CORE_ADDR offset = 0;
1764 gdb_byte op;
1765 int i;
1766
1767 if (cache->locals > 0)
1768 offset -= cache->locals;
1769 for (i = 0; i < 8 && pc < current_pc; i++)
1770 {
1771 if (target_read_code (pc, &op, 1))
1772 return pc;
1773 if (op < 0x50 || op > 0x57)
1774 break;
1775
1776 offset -= 4;
1777 cache->saved_regs[op - 0x50] = offset;
1778 cache->sp_offset += 4;
1779 pc++;
1780 }
1781
1782 return pc;
1783}
1784
1785/* Do a full analysis of the prologue at PC and update CACHE
1786 accordingly. Bail out early if CURRENT_PC is reached. Return the
1787 address where the analysis stopped.
1788
1789 We handle these cases:
1790
1791 The startup sequence can be at the start of the function, or the
1792 function can start with a branch to startup code at the end.
1793
1794 %ebp can be set up with either the 'enter' instruction, or "pushl
1795 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1796 once used in the System V compiler).
1797
1798 Local space is allocated just below the saved %ebp by either the
1799 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1800 16-bit unsigned argument for space to allocate, and the 'addl'
1801 instruction could have either a signed byte, or 32-bit immediate.
1802
1803 Next, the registers used by this function are pushed. With the
1804 System V compiler they will always be in the order: %edi, %esi,
1805 %ebx (and sometimes a harmless bug causes it to also save but not
1806 restore %eax); however, the code below is willing to see the pushes
1807 in any order, and will handle up to 8 of them.
1808
1809 If the setup sequence is at the end of the function, then the next
1810 instruction will be a branch back to the start. */
1811
1812static CORE_ADDR
1814 CORE_ADDR pc, CORE_ADDR current_pc,
1815 struct i386_frame_cache *cache)
1816{
1817 pc = i386_skip_endbr (pc);
1818 pc = i386_skip_noop (pc);
1819 pc = i386_follow_jump (gdbarch, pc);
1820 pc = i386_analyze_struct_return (pc, current_pc, cache);
1821 pc = i386_skip_probe (pc);
1822 pc = i386_analyze_stack_align (pc, current_pc, cache);
1823 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1824 return i386_analyze_register_saves (pc, current_pc, cache);
1825}
1826
1827/* Return PC of first real instruction. */
1828
1829static CORE_ADDR
1830i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1831{
1832 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1833
1834 static gdb_byte pic_pat[6] =
1835 {
1836 0xe8, 0, 0, 0, 0, /* call 0x0 */
1837 0x5b, /* popl %ebx */
1838 };
1839 struct i386_frame_cache cache;
1840 CORE_ADDR pc;
1841 gdb_byte op;
1842 int i;
1843 CORE_ADDR func_addr;
1844
1845 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1846 {
1847 CORE_ADDR post_prologue_pc
1848 = skip_prologue_using_sal (gdbarch, func_addr);
1849 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1850
1851 /* LLVM backend (Clang/Flang) always emits a line note before the
1852 prologue and another one after. We trust clang and newer Intel
1853 compilers to emit usable line notes. */
1854 if (post_prologue_pc
1855 && (cust != NULL
1856 && cust->producer () != NULL
1857 && (producer_is_llvm (cust->producer ())
1858 || producer_is_icc_ge_19 (cust->producer ()))))
1859 return std::max (start_pc, post_prologue_pc);
1860 }
1861
1862 cache.locals = -1;
1863 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1864 if (cache.locals < 0)
1865 return start_pc;
1866
1867 /* Found valid frame setup. */
1868
1869 /* The native cc on SVR4 in -K PIC mode inserts the following code
1870 to get the address of the global offset table (GOT) into register
1871 %ebx:
1872
1873 call 0x0
1874 popl %ebx
1875 movl %ebx,x(%ebp) (optional)
1876 addl y,%ebx
1877
1878 This code is with the rest of the prologue (at the end of the
1879 function), so we have to skip it to get to the first real
1880 instruction at the start of the function. */
1881
1882 for (i = 0; i < 6; i++)
1883 {
1884 if (target_read_code (pc + i, &op, 1))
1885 return pc;
1886
1887 if (pic_pat[i] != op)
1888 break;
1889 }
1890 if (i == 6)
1891 {
1892 int delta = 6;
1893
1894 if (target_read_code (pc + delta, &op, 1))
1895 return pc;
1896
1897 if (op == 0x89) /* movl %ebx, x(%ebp) */
1898 {
1899 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1900
1901 if (op == 0x5d) /* One byte offset from %ebp. */
1902 delta += 3;
1903 else if (op == 0x9d) /* Four byte offset from %ebp. */
1904 delta += 6;
1905 else /* Unexpected instruction. */
1906 delta = 0;
1907
1908 if (target_read_code (pc + delta, &op, 1))
1909 return pc;
1910 }
1911
1912 /* addl y,%ebx */
1913 if (delta > 0 && op == 0x81
1914 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1915 == 0xc3)
1916 {
1917 pc += delta + 6;
1918 }
1919 }
1920
1921 /* If the function starts with a branch (to startup code at the end)
1922 the last instruction should bring us back to the first
1923 instruction of the real code. */
1924 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1925 pc = i386_follow_jump (gdbarch, pc);
1926
1927 return pc;
1928}
1929
1930/* Check that the code pointed to by PC corresponds to a call to
1931 __main, skip it if so. Return PC otherwise. */
1932
1933CORE_ADDR
1935{
1936 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1937 gdb_byte op;
1938
1939 if (target_read_code (pc, &op, 1))
1940 return pc;
1941 if (op == 0xe8)
1942 {
1943 gdb_byte buf[4];
1944
1945 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1946 {
1947 /* Make sure address is computed correctly as a 32bit
1948 integer even if CORE_ADDR is 64 bit wide. */
1949 struct bound_minimal_symbol s;
1950 CORE_ADDR call_dest;
1951
1952 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1953 call_dest = call_dest & 0xffffffffU;
1954 s = lookup_minimal_symbol_by_pc (call_dest);
1955 if (s.minsym != NULL
1956 && s.minsym->linkage_name () != NULL
1957 && strcmp (s.minsym->linkage_name (), "__main") == 0)
1958 pc += 5;
1959 }
1960 }
1961
1962 return pc;
1963}
1964
1965/* This function is 64-bit safe. */
1966
1967static CORE_ADDR
1969{
1970 gdb_byte buf[8];
1971
1972 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1973 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1974}
1975
1976
1977/* Normal frames. */
1978
1979static void
1981 struct i386_frame_cache *cache)
1982{
1983 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1984 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1985 gdb_byte buf[4];
1986 int i;
1987
1988 cache->pc = get_frame_func (this_frame);
1989
1990 /* In principle, for normal frames, %ebp holds the frame pointer,
1991 which holds the base address for the current stack frame.
1992 However, for functions that don't need it, the frame pointer is
1993 optional. For these "frameless" functions the frame pointer is
1994 actually the frame pointer of the calling frame. Signal
1995 trampolines are just a special case of a "frameless" function.
1996 They (usually) share their frame pointer with the frame that was
1997 in progress when the signal occurred. */
1998
1999 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
2000 cache->base = extract_unsigned_integer (buf, 4, byte_order);
2001 if (cache->base == 0)
2002 {
2003 cache->base_p = 1;
2004 return;
2005 }
2006
2007 /* For normal frames, %eip is stored at 4(%ebp). */
2008 cache->saved_regs[I386_EIP_REGNUM] = 4;
2009
2010 if (cache->pc != 0)
2011 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2012 cache);
2013
2014 if (cache->locals < 0)
2015 {
2016 /* We didn't find a valid frame, which means that CACHE->base
2017 currently holds the frame pointer for our calling frame. If
2018 we're at the start of a function, or somewhere half-way its
2019 prologue, the function's frame probably hasn't been fully
2020 setup yet. Try to reconstruct the base address for the stack
2021 frame by looking at the stack pointer. For truly "frameless"
2022 functions this might work too. */
2023
2024 if (cache->saved_sp_reg != -1)
2025 {
2026 /* Saved stack pointer has been saved. */
2027 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2028 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2029
2030 /* We're halfway aligning the stack. */
2031 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2032 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2033
2034 /* This will be added back below. */
2035 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2036 }
2037 else if (cache->pc != 0
2038 || target_read_code (get_frame_pc (this_frame), buf, 1))
2039 {
2040 /* We're in a known function, but did not find a frame
2041 setup. Assume that the function does not use %ebp.
2042 Alternatively, we may have jumped to an invalid
2043 address; in that case there is definitely no new
2044 frame in %ebp. */
2045 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2046 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2047 + cache->sp_offset;
2048 }
2049 else
2050 /* We're in an unknown function. We could not find the start
2051 of the function to analyze the prologue; our best option is
2052 to assume a typical frame layout with the caller's %ebp
2053 saved. */
2054 cache->saved_regs[I386_EBP_REGNUM] = 0;
2055 }
2056
2057 if (cache->saved_sp_reg != -1)
2058 {
2059 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2060 register may be unavailable). */
2061 if (cache->saved_sp == 0
2062 && deprecated_frame_register_read (this_frame,
2063 cache->saved_sp_reg, buf))
2064 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2065 }
2066 /* Now that we have the base address for the stack frame we can
2067 calculate the value of %esp in the calling frame. */
2068 else if (cache->saved_sp == 0)
2069 cache->saved_sp = cache->base + 8;
2070
2071 /* Adjust all the saved registers such that they contain addresses
2072 instead of offsets. */
2073 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2074 if (cache->saved_regs[i] != -1)
2075 cache->saved_regs[i] += cache->base;
2076
2077 cache->base_p = 1;
2078}
2079
2080static struct i386_frame_cache *
2081i386_frame_cache (frame_info_ptr this_frame, void **this_cache)
2082{
2083 struct i386_frame_cache *cache;
2084
2085 if (*this_cache)
2086 return (struct i386_frame_cache *) *this_cache;
2087
2088 cache = i386_alloc_frame_cache ();
2089 *this_cache = cache;
2090
2091 try
2092 {
2093 i386_frame_cache_1 (this_frame, cache);
2094 }
2095 catch (const gdb_exception_error &ex)
2096 {
2097 if (ex.error != NOT_AVAILABLE_ERROR)
2098 throw;
2099 }
2100
2101 return cache;
2102}
2103
2104static void
2105i386_frame_this_id (frame_info_ptr this_frame, void **this_cache,
2106 struct frame_id *this_id)
2107{
2108 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2109
2110 if (!cache->base_p)
2111 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2112 else if (cache->base == 0)
2113 {
2114 /* This marks the outermost frame. */
2115 }
2116 else
2117 {
2118 /* See the end of i386_push_dummy_call. */
2119 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2120 }
2121}
2122
2123static enum unwind_stop_reason
2125 void **this_cache)
2126{
2127 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2128
2129 if (!cache->base_p)
2130 return UNWIND_UNAVAILABLE;
2131
2132 /* This marks the outermost frame. */
2133 if (cache->base == 0)
2134 return UNWIND_OUTERMOST;
2135
2136 return UNWIND_NO_REASON;
2137}
2138
2139static struct value *
2140i386_frame_prev_register (frame_info_ptr this_frame, void **this_cache,
2141 int regnum)
2142{
2143 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2144
2145 gdb_assert (regnum >= 0);
2146
2147 /* The System V ABI says that:
2148
2149 "The flags register contains the system flags, such as the
2150 direction flag and the carry flag. The direction flag must be
2151 set to the forward (that is, zero) direction before entry and
2152 upon exit from a function. Other user flags have no specified
2153 role in the standard calling sequence and are not preserved."
2154
2155 To guarantee the "upon exit" part of that statement we fake a
2156 saved flags register that has its direction flag cleared.
2157
2158 Note that GCC doesn't seem to rely on the fact that the direction
2159 flag is cleared after a function return; it always explicitly
2160 clears the flag before operations where it matters.
2161
2162 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2163 right thing to do. The way we fake the flags register here makes
2164 it impossible to change it. */
2165
2167 {
2168 ULONGEST val;
2169
2170 val = get_frame_register_unsigned (this_frame, regnum);
2171 val &= ~(1 << 10);
2172 return frame_unwind_got_constant (this_frame, regnum, val);
2173 }
2174
2175 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2176 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2177
2178 if (regnum == I386_ESP_REGNUM
2179 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2180 {
2181 /* If the SP has been saved, but we don't know where, then this
2182 means that SAVED_SP_REG register was found unavailable back
2183 when we built the cache. */
2184 if (cache->saved_sp == 0)
2185 return frame_unwind_got_register (this_frame, regnum,
2186 cache->saved_sp_reg);
2187 else
2188 return frame_unwind_got_constant (this_frame, regnum,
2189 cache->saved_sp);
2190 }
2191
2192 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2193 return frame_unwind_got_memory (this_frame, regnum,
2194 cache->saved_regs[regnum]);
2195
2196 return frame_unwind_got_register (this_frame, regnum, regnum);
2197}
2198
2199static const struct frame_unwind i386_frame_unwind =
2200{
2201 "i386 prologue",
2206 NULL,
2208};
2209
2210/* Normal frames, but in a function epilogue. */
2211
2212/* Implement the stack_frame_destroyed_p gdbarch method.
2213
2214 The epilogue is defined here as the 'ret' instruction, which will
2215 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2216 the function's stack frame. */
2217
2218static int
2220{
2221 gdb_byte insn;
2222 struct compunit_symtab *cust;
2223
2224 cust = find_pc_compunit_symtab (pc);
2225 if (cust != NULL && cust->epilogue_unwind_valid ())
2226 return 0;
2227
2228 if (target_read_memory (pc, &insn, 1))
2229 return 0; /* Can't read memory at pc. */
2230
2231 if (insn != 0xc3) /* 'ret' instruction. */
2232 return 0;
2233
2234 return 1;
2235}
2236
2237static int
2239 frame_info_ptr this_frame,
2240 void **this_prologue_cache)
2241{
2242 if (frame_relative_level (this_frame) == 0)
2243 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2244 get_frame_pc (this_frame));
2245 else
2246 return 0;
2247}
2248
2249static struct i386_frame_cache *
2250i386_epilogue_frame_cache (frame_info_ptr this_frame, void **this_cache)
2251{
2252 struct i386_frame_cache *cache;
2253 CORE_ADDR sp;
2254
2255 if (*this_cache)
2256 return (struct i386_frame_cache *) *this_cache;
2257
2258 cache = i386_alloc_frame_cache ();
2259 *this_cache = cache;
2260
2261 try
2262 {
2263 cache->pc = get_frame_func (this_frame);
2264
2265 /* At this point the stack looks as if we just entered the
2266 function, with the return address at the top of the
2267 stack. */
2269 cache->base = sp + cache->sp_offset;
2270 cache->saved_sp = cache->base + 8;
2271 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2272
2273 cache->base_p = 1;
2274 }
2275 catch (const gdb_exception_error &ex)
2276 {
2277 if (ex.error != NOT_AVAILABLE_ERROR)
2278 throw;
2279 }
2280
2281 return cache;
2282}
2283
2284static enum unwind_stop_reason
2286 void **this_cache)
2287{
2288 struct i386_frame_cache *cache =
2289 i386_epilogue_frame_cache (this_frame, this_cache);
2290
2291 if (!cache->base_p)
2292 return UNWIND_UNAVAILABLE;
2293
2294 return UNWIND_NO_REASON;
2295}
2296
2297static void
2299 void **this_cache,
2300 struct frame_id *this_id)
2301{
2302 struct i386_frame_cache *cache =
2303 i386_epilogue_frame_cache (this_frame, this_cache);
2304
2305 if (!cache->base_p)
2306 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2307 else
2308 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2309}
2310
2311static struct value *
2313 void **this_cache, int regnum)
2314{
2315 /* Make sure we've initialized the cache. */
2316 i386_epilogue_frame_cache (this_frame, this_cache);
2317
2318 return i386_frame_prev_register (this_frame, this_cache, regnum);
2319}
2320
2322{
2323 "i386 epilogue",
2328 NULL,
2330};
2331
2332
2333/* Stack-based trampolines. */
2334
2335/* These trampolines are used on cross x86 targets, when taking the
2336 address of a nested function. When executing these trampolines,
2337 no stack frame is set up, so we are in a similar situation as in
2338 epilogues and i386_epilogue_frame_this_id can be re-used. */
2339
2340/* Static chain passed in register. */
2341
2343{
2344 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2345 { 5, { 0xb8 }, { 0xfe } },
2346
2347 /* `jmp imm32' */
2348 { 5, { 0xe9 }, { 0xff } },
2349
2350 {0}
2351};
2352
2353/* Static chain passed on stack (when regparm=3). */
2354
2356{
2357 /* `push imm32' */
2358 { 5, { 0x68 }, { 0xff } },
2359
2360 /* `jmp imm32' */
2361 { 5, { 0xe9 }, { 0xff } },
2362
2363 {0}
2364};
2365
2366/* Return whether PC points inside a stack trampoline. */
2367
2368static int
2370{
2371 gdb_byte insn;
2372 const char *name;
2373
2374 /* A stack trampoline is detected if no name is associated
2375 to the current pc and if it points inside a trampoline
2376 sequence. */
2377
2378 find_pc_partial_function (pc, &name, NULL, NULL);
2379 if (name)
2380 return 0;
2381
2382 if (target_read_memory (pc, &insn, 1))
2383 return 0;
2384
2387 return 0;
2388
2389 return 1;
2390}
2391
2392static int
2394 frame_info_ptr this_frame,
2395 void **this_cache)
2396{
2397 if (frame_relative_level (this_frame) == 0)
2398 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2399 else
2400 return 0;
2401}
2402
2404{
2405 "i386 stack tramp",
2410 NULL,
2412};
2413
2414/* Generate a bytecode expression to get the value of the saved PC. */
2415
2416static void
2418 struct agent_expr *ax, struct axs_value *value,
2419 CORE_ADDR scope)
2420{
2421 /* The following sequence assumes the traditional use of the base
2422 register. */
2423 ax_reg (ax, I386_EBP_REGNUM);
2424 ax_const_l (ax, 4);
2425 ax_simple (ax, aop_add);
2427 value->kind = axs_lvalue_memory;
2428}
2429
2430
2431/* Signal trampolines. */
2432
2433static struct i386_frame_cache *
2434i386_sigtramp_frame_cache (frame_info_ptr this_frame, void **this_cache)
2435{
2436 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2437 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
2438 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2439 struct i386_frame_cache *cache;
2440 CORE_ADDR addr;
2441 gdb_byte buf[4];
2442
2443 if (*this_cache)
2444 return (struct i386_frame_cache *) *this_cache;
2445
2446 cache = i386_alloc_frame_cache ();
2447
2448 try
2449 {
2450 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2451 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2452
2453 addr = tdep->sigcontext_addr (this_frame);
2454 if (tdep->sc_reg_offset)
2455 {
2456 int i;
2457
2458 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2459
2460 for (i = 0; i < tdep->sc_num_regs; i++)
2461 if (tdep->sc_reg_offset[i] != -1)
2462 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2463 }
2464 else
2465 {
2466 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2467 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2468 }
2469
2470 cache->base_p = 1;
2471 }
2472 catch (const gdb_exception_error &ex)
2473 {
2474 if (ex.error != NOT_AVAILABLE_ERROR)
2475 throw;
2476 }
2477
2478 *this_cache = cache;
2479 return cache;
2480}
2481
2482static enum unwind_stop_reason
2484 void **this_cache)
2485{
2486 struct i386_frame_cache *cache =
2487 i386_sigtramp_frame_cache (this_frame, this_cache);
2488
2489 if (!cache->base_p)
2490 return UNWIND_UNAVAILABLE;
2491
2492 return UNWIND_NO_REASON;
2493}
2494
2495static void
2496i386_sigtramp_frame_this_id (frame_info_ptr this_frame, void **this_cache,
2497 struct frame_id *this_id)
2498{
2499 struct i386_frame_cache *cache =
2500 i386_sigtramp_frame_cache (this_frame, this_cache);
2501
2502 if (!cache->base_p)
2503 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2504 else
2505 {
2506 /* See the end of i386_push_dummy_call. */
2507 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2508 }
2509}
2510
2511static struct value *
2513 void **this_cache, int regnum)
2514{
2515 /* Make sure we've initialized the cache. */
2516 i386_sigtramp_frame_cache (this_frame, this_cache);
2517
2518 return i386_frame_prev_register (this_frame, this_cache, regnum);
2519}
2520
2521static int
2523 frame_info_ptr this_frame,
2524 void **this_prologue_cache)
2525{
2526 gdbarch *arch = get_frame_arch (this_frame);
2527 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
2528
2529 /* We shouldn't even bother if we don't have a sigcontext_addr
2530 handler. */
2531 if (tdep->sigcontext_addr == NULL)
2532 return 0;
2533
2534 if (tdep->sigtramp_p != NULL)
2535 {
2536 if (tdep->sigtramp_p (this_frame))
2537 return 1;
2538 }
2539
2540 if (tdep->sigtramp_start != 0)
2541 {
2542 CORE_ADDR pc = get_frame_pc (this_frame);
2543
2544 gdb_assert (tdep->sigtramp_end != 0);
2545 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2546 return 1;
2547 }
2548
2549 return 0;
2550}
2551
2553{
2554 "i386 sigtramp",
2559 NULL,
2561};
2562
2563
2564static CORE_ADDR
2565i386_frame_base_address (frame_info_ptr this_frame, void **this_cache)
2566{
2567 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2568
2569 return cache->base;
2570}
2571
2572static const struct frame_base i386_frame_base =
2573{
2578};
2579
2580static struct frame_id
2582{
2583 CORE_ADDR fp;
2584
2586
2587 /* See the end of i386_push_dummy_call. */
2588 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2589}
2590
2591/* _Decimal128 function return values need 16-byte alignment on the
2592 stack. */
2593
2594static CORE_ADDR
2595i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2596{
2597 return sp & -(CORE_ADDR)16;
2598}
2599
2600
2601/* Figure out where the longjmp will land. Slurp the args out of the
2602 stack. We expect the first arg to be a pointer to the jmp_buf
2603 structure from which we extract the address that we will land at.
2604 This address is copied into PC. This routine returns non-zero on
2605 success. */
2606
2607static int
2609{
2610 gdb_byte buf[4];
2611 CORE_ADDR sp, jb_addr;
2612 struct gdbarch *gdbarch = get_frame_arch (frame);
2613 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2614 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
2615 int jb_pc_offset = tdep->jb_pc_offset;
2616
2617 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2618 longjmp will land. */
2619 if (jb_pc_offset == -1)
2620 return 0;
2621
2622 get_frame_register (frame, I386_ESP_REGNUM, buf);
2623 sp = extract_unsigned_integer (buf, 4, byte_order);
2624 if (target_read_memory (sp + 4, buf, 4))
2625 return 0;
2626
2627 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2628 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2629 return 0;
2630
2631 *pc = extract_unsigned_integer (buf, 4, byte_order);
2632 return 1;
2633}
2634
2635
2636/* Check whether TYPE must be 16-byte-aligned when passed as a
2637 function argument. 16-byte vectors, _Decimal128 and structures or
2638 unions containing such types must be 16-byte-aligned; other
2639 arguments are 4-byte-aligned. */
2640
2641static int
2643{
2645 if ((type->code () == TYPE_CODE_DECFLOAT
2646 || (type->code () == TYPE_CODE_ARRAY && type->is_vector ()))
2647 && type->length () == 16)
2648 return 1;
2649 if (type->code () == TYPE_CODE_ARRAY)
2651 if (type->code () == TYPE_CODE_STRUCT
2652 || type->code () == TYPE_CODE_UNION)
2653 {
2654 int i;
2655 for (i = 0; i < type->num_fields (); i++)
2656 {
2657 if (field_is_static (&type->field (i)))
2658 continue;
2659 if (i386_16_byte_align_p (type->field (i).type ()))
2660 return 1;
2661 }
2662 }
2663 return 0;
2664}
2665
2666/* Implementation for set_gdbarch_push_dummy_code. */
2667
2668static CORE_ADDR
2669i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2670 struct value **args, int nargs, struct type *value_type,
2671 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2672 struct regcache *regcache)
2673{
2674 /* Use 0xcc breakpoint - 1 byte. */
2675 *bp_addr = sp - 1;
2676 *real_pc = funaddr;
2677
2678 /* Keep the stack aligned. */
2679 return sp - 16;
2680}
2681
2682/* The "push_dummy_call" gdbarch method, optionally with the thiscall
2683 calling convention. */
2684
2685CORE_ADDR
2687 struct regcache *regcache, CORE_ADDR bp_addr,
2688 int nargs, struct value **args, CORE_ADDR sp,
2689 function_call_return_method return_method,
2690 CORE_ADDR struct_addr, bool thiscall)
2691{
2692 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2693 gdb_byte buf[4];
2694 int i;
2695 int write_pass;
2696 int args_space = 0;
2697
2698 /* BND registers can be in arbitrary values at the moment of the
2699 inferior call. This can cause boundary violations that are not
2700 due to a real bug or even desired by the user. The best to be done
2701 is set the BND registers to allow access to the whole memory, INIT
2702 state, before pushing the inferior call. */
2704
2705 /* Determine the total space required for arguments and struct
2706 return address in a first pass (allowing for 16-byte-aligned
2707 arguments), then push arguments in a second pass. */
2708
2709 for (write_pass = 0; write_pass < 2; write_pass++)
2710 {
2711 int args_space_used = 0;
2712
2713 if (return_method == return_method_struct)
2714 {
2715 if (write_pass)
2716 {
2717 /* Push value address. */
2718 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2719 write_memory (sp, buf, 4);
2720 args_space_used += 4;
2721 }
2722 else
2723 args_space += 4;
2724 }
2725
2726 for (i = thiscall ? 1 : 0; i < nargs; i++)
2727 {
2728 int len = value_enclosing_type (args[i])->length ();
2729
2730 if (write_pass)
2731 {
2733 args_space_used = align_up (args_space_used, 16);
2734
2735 write_memory (sp + args_space_used,
2736 value_contents_all (args[i]).data (), len);
2737 /* The System V ABI says that:
2738
2739 "An argument's size is increased, if necessary, to make it a
2740 multiple of [32-bit] words. This may require tail padding,
2741 depending on the size of the argument."
2742
2743 This makes sure the stack stays word-aligned. */
2744 args_space_used += align_up (len, 4);
2745 }
2746 else
2747 {
2749 args_space = align_up (args_space, 16);
2750 args_space += align_up (len, 4);
2751 }
2752 }
2753
2754 if (!write_pass)
2755 {
2756 sp -= args_space;
2757
2758 /* The original System V ABI only requires word alignment,
2759 but modern incarnations need 16-byte alignment in order
2760 to support SSE. Since wasting a few bytes here isn't
2761 harmful we unconditionally enforce 16-byte alignment. */
2762 sp &= ~0xf;
2763 }
2764 }
2765
2766 /* Store return address. */
2767 sp -= 4;
2768 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2769 write_memory (sp, buf, 4);
2770
2771 /* Finally, update the stack pointer... */
2772 store_unsigned_integer (buf, 4, byte_order, sp);
2774
2775 /* ...and fake a frame pointer. */
2777
2778 /* The 'this' pointer needs to be in ECX. */
2779 if (thiscall)
2781 value_contents_all (args[0]).data ());
2782
2783 /* If the PLT is position-independent, the SYSTEM V ABI requires %ebx to be
2784 set to the address of the GOT when doing a call to a PLT address.
2785 Note that we do not try to determine whether the PLT is
2786 position-independent, we just set the register regardless. */
2787 CORE_ADDR func_addr = find_function_addr (function, nullptr, nullptr);
2788 if (in_plt_section (func_addr))
2789 {
2790 struct objfile *objf = nullptr;
2791 asection *asect = nullptr;
2792 obj_section *osect = nullptr;
2793
2794 /* Get object file containing func_addr. */
2795 obj_section *func_section = find_pc_section (func_addr);
2796 if (func_section != nullptr)
2797 objf = func_section->objfile;
2798
2799 if (objf != nullptr)
2800 {
2801 /* Get corresponding .got.plt or .got section. */
2802 asect = bfd_get_section_by_name (objf->obfd.get (), ".got.plt");
2803 if (asect == nullptr)
2804 asect = bfd_get_section_by_name (objf->obfd.get (), ".got");
2805 }
2806
2807 if (asect != nullptr)
2808 /* Translate asection to obj_section. */
2809 osect = maint_obj_section_from_bfd_section (objf->obfd.get (),
2810 asect, objf);
2811
2812 if (osect != nullptr)
2813 {
2814 /* Store the section address in %ebx. */
2815 store_unsigned_integer (buf, 4, byte_order, osect->addr ());
2817 }
2818 else
2819 {
2820 /* If we would only do this for a position-independent PLT, it would
2821 make sense to issue a warning here. */
2822 }
2823 }
2824
2825 /* MarkK wrote: This "+ 8" is all over the place:
2826 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2827 i386_dummy_id). It's there, since all frame unwinders for
2828 a given target have to agree (within a certain margin) on the
2829 definition of the stack address of a frame. Otherwise frame id
2830 comparison might not work correctly. Since DWARF2/GCC uses the
2831 stack address *before* the function call as a frame's CFA. On
2832 the i386, when %ebp is used as a frame pointer, the offset
2833 between the contents %ebp and the CFA as defined by GCC. */
2834 return sp + 8;
2835}
2836
2837/* Implement the "push_dummy_call" gdbarch method. */
2838
2839static CORE_ADDR
2840i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2841 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2842 struct value **args, CORE_ADDR sp,
2843 function_call_return_method return_method,
2844 CORE_ADDR struct_addr)
2845{
2846 return i386_thiscall_push_dummy_call (gdbarch, function, regcache, bp_addr,
2847 nargs, args, sp, return_method,
2848 struct_addr, false);
2849}
2850
2851/* These registers are used for returning integers (and on some
2852 targets also for returning `struct' and `union' values when their
2853 size and alignment match an integer type). */
2854#define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2855#define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2856
2857/* Read, for architecture GDBARCH, a function return value of TYPE
2858 from REGCACHE, and copy that into VALBUF. */
2859
2860static void
2862 struct regcache *regcache, gdb_byte *valbuf)
2863{
2864 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
2865 int len = type->length ();
2866 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2867
2868 /* _Float16 and _Float16 _Complex values are returned via xmm0. */
2869 if (((type->code () == TYPE_CODE_FLT) && len == 2)
2870 || ((type->code () == TYPE_CODE_COMPLEX) && len == 4))
2871 {
2872 regcache->raw_read (I387_XMM0_REGNUM (tdep), valbuf);
2873 return;
2874 }
2875 else if (type->code () == TYPE_CODE_FLT)
2876 {
2877 if (tdep->st0_regnum < 0)
2878 {
2879 warning (_("Cannot find floating-point return value."));
2880 memset (valbuf, 0, len);
2881 return;
2882 }
2883
2884 /* Floating-point return values can be found in %st(0). Convert
2885 its contents to the desired type. This is probably not
2886 exactly how it would happen on the target itself, but it is
2887 the best we can do. */
2890 }
2891 else
2892 {
2893 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2894 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2895
2896 if (len <= low_size)
2897 {
2899 memcpy (valbuf, buf, len);
2900 }
2901 else if (len <= (low_size + high_size))
2902 {
2904 memcpy (valbuf, buf, low_size);
2906 memcpy (valbuf + low_size, buf, len - low_size);
2907 }
2908 else
2909 internal_error (_("Cannot extract return value of %d bytes long."),
2910 len);
2911 }
2912}
2913
2914/* Write, for architecture GDBARCH, a function return value of TYPE
2915 from VALBUF into REGCACHE. */
2916
2917static void
2919 struct regcache *regcache, const gdb_byte *valbuf)
2920{
2921 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
2922 int len = type->length ();
2923
2924 if (type->code () == TYPE_CODE_FLT)
2925 {
2926 ULONGEST fstat;
2927 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2928
2929 if (tdep->st0_regnum < 0)
2930 {
2931 warning (_("Cannot set floating-point return value."));
2932 return;
2933 }
2934
2935 /* Returning floating-point values is a bit tricky. Apart from
2936 storing the return value in %st(0), we have to simulate the
2937 state of the FPU at function return point. */
2938
2939 /* Convert the value found in VALBUF to the extended
2940 floating-point format used by the FPU. This is probably
2941 not exactly how it would happen on the target itself, but
2942 it is the best we can do. */
2945
2946 /* Set the top of the floating-point register stack to 7. The
2947 actual value doesn't really matter, but 7 is what a normal
2948 function return would end up with if the program started out
2949 with a freshly initialized FPU. */
2951 fstat |= (7 << 11);
2953
2954 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2955 the floating-point register stack to 7, the appropriate value
2956 for the tag word is 0x3fff. */
2958 }
2959 else
2960 {
2961 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2962 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2963
2964 if (len <= low_size)
2965 regcache->raw_write_part (LOW_RETURN_REGNUM, 0, len, valbuf);
2966 else if (len <= (low_size + high_size))
2967 {
2969 regcache->raw_write_part (HIGH_RETURN_REGNUM, 0, len - low_size,
2970 valbuf + low_size);
2971 }
2972 else
2973 internal_error (_("Cannot store return value of %d bytes long."), len);
2974 }
2975}
2976
2977
2978/* This is the variable that is set with "set struct-convention", and
2979 its legitimate values. */
2980static const char default_struct_convention[] = "default";
2981static const char pcc_struct_convention[] = "pcc";
2982static const char reg_struct_convention[] = "reg";
2983static const char *const valid_conventions[] =
2984{
2988 NULL
2989};
2991
2992/* Return non-zero if TYPE, which is assumed to be a structure,
2993 a union type, or an array type, should be returned in registers
2994 for architecture GDBARCH. */
2995
2996static int
2998{
2999 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3000 enum type_code code = type->code ();
3001 int len = type->length ();
3002
3003 gdb_assert (code == TYPE_CODE_STRUCT
3004 || code == TYPE_CODE_UNION
3005 || code == TYPE_CODE_ARRAY);
3006
3009 && tdep->struct_return == pcc_struct_return))
3010 return 0;
3011
3012 /* Structures consisting of a single `float', `double' or 'long
3013 double' member are returned in %st(0). */
3014 if (code == TYPE_CODE_STRUCT && type->num_fields () == 1)
3015 {
3016 type = check_typedef (type->field (0).type ());
3017 if (type->code () == TYPE_CODE_FLT)
3018 return (len == 4 || len == 8 || len == 12);
3019 }
3020
3021 return (len == 1 || len == 2 || len == 4 || len == 8);
3022}
3023
3024/* Determine, for architecture GDBARCH, how a return value of TYPE
3025 should be returned. If it is supposed to be returned in registers,
3026 and READBUF is non-zero, read the appropriate value from REGCACHE,
3027 and copy it into READBUF. If WRITEBUF is non-zero, write the value
3028 from WRITEBUF into REGCACHE. */
3029
3030static enum return_value_convention
3031i386_return_value (struct gdbarch *gdbarch, struct value *function,
3032 struct type *type, struct regcache *regcache,
3033 gdb_byte *readbuf, const gdb_byte *writebuf)
3034{
3035 enum type_code code = type->code ();
3036
3037 if (((code == TYPE_CODE_STRUCT
3038 || code == TYPE_CODE_UNION
3039 || code == TYPE_CODE_ARRAY)
3041 /* Complex double and long double uses the struct return convention. */
3042 || (code == TYPE_CODE_COMPLEX && type->length () == 16)
3043 || (code == TYPE_CODE_COMPLEX && type->length () == 24)
3044 /* 128-bit decimal float uses the struct return convention. */
3045 || (code == TYPE_CODE_DECFLOAT && type->length () == 16))
3046 {
3047 /* The System V ABI says that:
3048
3049 "A function that returns a structure or union also sets %eax
3050 to the value of the original address of the caller's area
3051 before it returns. Thus when the caller receives control
3052 again, the address of the returned object resides in register
3053 %eax and can be used to access the object."
3054
3055 So the ABI guarantees that we can always find the return
3056 value just after the function has returned. */
3057
3058 /* Note that the ABI doesn't mention functions returning arrays,
3059 which is something possible in certain languages such as Ada.
3060 In this case, the value is returned as if it was wrapped in
3061 a record, so the convention applied to records also applies
3062 to arrays. */
3063
3064 if (readbuf)
3065 {
3066 ULONGEST addr;
3067
3069 read_memory (addr, readbuf, type->length ());
3070 }
3071
3073 }
3074
3075 /* This special case is for structures consisting of a single
3076 `float', `double' or 'long double' member. These structures are
3077 returned in %st(0). For these structures, we call ourselves
3078 recursively, changing TYPE into the type of the first member of
3079 the structure. Since that should work for all structures that
3080 have only one member, we don't bother to check the member's type
3081 here. */
3082 if (code == TYPE_CODE_STRUCT && type->num_fields () == 1)
3083 {
3084 type = check_typedef (type->field (0).type ());
3085 return i386_return_value (gdbarch, function, type, regcache,
3086 readbuf, writebuf);
3087 }
3088
3089 if (readbuf)
3091 if (writebuf)
3093
3095}
3096
3097
3098struct type *
3100{
3101 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3102
3103 if (!tdep->i387_ext_type)
3104 {
3105 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3106 gdb_assert (tdep->i387_ext_type != NULL);
3107 }
3108
3109 return tdep->i387_ext_type;
3110}
3111
3112/* Construct type for pseudo BND registers. We can't use
3113 tdesc_find_type since a complement of one value has to be used
3114 to describe the upper bound. */
3115
3116static struct type *
3118{
3119 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3120
3121
3122 if (!tdep->i386_bnd_type)
3123 {
3124 struct type *t;
3125 const struct builtin_type *bt = builtin_type (gdbarch);
3126
3127 /* The type we're building is described bellow: */
3128#if 0
3129 struct __bound128
3130 {
3131 void *lbound;
3132 void *ubound; /* One complement of raw ubound field. */
3133 };
3134#endif
3135
3137 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3138
3141
3142 t->set_name ("builtin_type_bound128");
3143 tdep->i386_bnd_type = t;
3144 }
3145
3146 return tdep->i386_bnd_type;
3147}
3148
3149/* Construct vector type for pseudo ZMM registers. We can't use
3150 tdesc_find_type since ZMM isn't described in target description. */
3151
3152static struct type *
3154{
3155 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3156
3157 if (!tdep->i386_zmm_type)
3158 {
3159 const struct builtin_type *bt = builtin_type (gdbarch);
3160
3161 /* The type we're building is this: */
3162#if 0
3163 union __gdb_builtin_type_vec512i
3164 {
3165 int128_t v4_int128[4];
3166 int64_t v8_int64[8];
3167 int32_t v16_int32[16];
3168 int16_t v32_int16[32];
3169 int8_t v64_int8[64];
3170 double v8_double[8];
3171 float v16_float[16];
3172 float16_t v32_half[32];
3173 bfloat16_t v32_bfloat16[32];
3174 };
3175#endif
3176
3177 struct type *t;
3178
3180 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3181 append_composite_type_field (t, "v32_bfloat16",
3183 append_composite_type_field (t, "v32_half",
3184 init_vector_type (bt->builtin_half, 32));
3185 append_composite_type_field (t, "v16_float",
3187 append_composite_type_field (t, "v8_double",
3189 append_composite_type_field (t, "v64_int8",
3190 init_vector_type (bt->builtin_int8, 64));
3191 append_composite_type_field (t, "v32_int16",
3193 append_composite_type_field (t, "v16_int32",
3195 append_composite_type_field (t, "v8_int64",
3197 append_composite_type_field (t, "v4_int128",
3199
3200 t->set_is_vector (true);
3201 t->set_name ("builtin_type_vec512i");
3202 tdep->i386_zmm_type = t;
3203 }
3204
3205 return tdep->i386_zmm_type;
3206}
3207
3208/* Construct vector type for pseudo YMM registers. We can't use
3209 tdesc_find_type since YMM isn't described in target description. */
3210
3211static struct type *
3213{
3214 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3215
3216 if (!tdep->i386_ymm_type)
3217 {
3218 const struct builtin_type *bt = builtin_type (gdbarch);
3219
3220 /* The type we're building is this: */
3221#if 0
3222 union __gdb_builtin_type_vec256i
3223 {
3224 int128_t v2_int128[2];
3225 int64_t v4_int64[4];
3226 int32_t v8_int32[8];
3227 int16_t v16_int16[16];
3228 int8_t v32_int8[32];
3229 double v4_double[4];
3230 float v8_float[8];
3231 float16_t v16_half[16];
3232 bfloat16_t v16_bfloat16[16];
3233 };
3234#endif
3235
3236 struct type *t;
3237
3239 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3240 append_composite_type_field (t, "v16_bfloat16",
3242 append_composite_type_field (t, "v16_half",
3243 init_vector_type (bt->builtin_half, 16));
3244 append_composite_type_field (t, "v8_float",
3246 append_composite_type_field (t, "v4_double",
3248 append_composite_type_field (t, "v32_int8",
3249 init_vector_type (bt->builtin_int8, 32));
3250 append_composite_type_field (t, "v16_int16",
3252 append_composite_type_field (t, "v8_int32",
3254 append_composite_type_field (t, "v4_int64",
3256 append_composite_type_field (t, "v2_int128",
3258
3259 t->set_is_vector (true);
3260 t->set_name ("builtin_type_vec256i");
3261 tdep->i386_ymm_type = t;
3262 }
3263
3264 return tdep->i386_ymm_type;
3265}
3266
3267/* Construct vector type for MMX registers. */
3268static struct type *
3270{
3271 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3272
3273 if (!tdep->i386_mmx_type)
3274 {
3275 const struct builtin_type *bt = builtin_type (gdbarch);
3276
3277 /* The type we're building is this: */
3278#if 0
3279 union __gdb_builtin_type_vec64i
3280 {
3281 int64_t uint64;
3282 int32_t v2_int32[2];
3283 int16_t v4_int16[4];
3284 int8_t v8_int8[8];
3285 };
3286#endif
3287
3288 struct type *t;
3289
3291 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3292
3293 append_composite_type_field (t, "uint64", bt->builtin_int64);
3294 append_composite_type_field (t, "v2_int32",
3296 append_composite_type_field (t, "v4_int16",
3298 append_composite_type_field (t, "v8_int8",
3300
3301 t->set_is_vector (true);
3302 t->set_name ("builtin_type_vec64i");
3303 tdep->i386_mmx_type = t;
3304 }
3305
3306 return tdep->i386_mmx_type;
3307}
3308
3309/* Return the GDB type object for the "standard" data type of data in
3310 register REGNUM. */
3311
3312struct type *
3314{
3316 return i386_bnd_type (gdbarch);
3318 return i386_mmx_type (gdbarch);
3319 else if (i386_ymm_regnum_p (gdbarch, regnum))
3320 return i386_ymm_type (gdbarch);
3322 return i386_ymm_type (gdbarch);
3323 else if (i386_zmm_regnum_p (gdbarch, regnum))
3324 return i386_zmm_type (gdbarch);
3325 else
3326 {
3327 const struct builtin_type *bt = builtin_type (gdbarch);
3329 return bt->builtin_int8;
3330 else if (i386_word_regnum_p (gdbarch, regnum))
3331 return bt->builtin_int16;
3333 return bt->builtin_int32;
3334 else if (i386_k_regnum_p (gdbarch, regnum))
3335 return bt->builtin_int64;
3336 }
3337
3338 internal_error (_("invalid regnum"));
3339}
3340
3341/* Map a cooked register onto a raw register or memory. For the i386,
3342 the MMX registers need to be mapped onto floating point registers. */
3343
3344static int
3346{
3347 gdbarch *arch = regcache->arch ();
3348 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
3349 int mmxreg, fpreg;
3350 ULONGEST fstat;
3351 int tos;
3352
3353 mmxreg = regnum - tdep->mm0_regnum;
3354 regcache->raw_read (I387_FSTAT_REGNUM (tdep), &fstat);
3355 tos = (fstat >> 11) & 0x7;
3356 fpreg = (mmxreg + tos) % 8;
3357
3358 return (I387_ST0_REGNUM (tdep) + fpreg);
3359}
3360
3361/* A helper function for us by i386_pseudo_register_read_value and
3362 amd64_pseudo_register_read_value. It does all the work but reads
3363 the data into an already-allocated value. */
3364
3365void
3368 int regnum,
3369 struct value *result_value)
3370{
3371 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3372 enum register_status status;
3373 gdb_byte *buf = value_contents_raw (result_value).data ();
3374
3376 {
3378
3379 /* Extract (always little endian). */
3380 status = regcache->raw_read (fpnum, raw_buf);
3381 if (status != REG_VALID)
3382 mark_value_bytes_unavailable (result_value, 0,
3383 value_type (result_value)->length ());
3384 else
3385 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3386 }
3387 else
3388 {
3389 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3391 {
3392 regnum -= tdep->bnd0_regnum;
3393
3394 /* Extract (always little endian). Read lower 128bits. */
3396 raw_buf);
3397 if (status != REG_VALID)
3398 mark_value_bytes_unavailable (result_value, 0, 16);
3399 else
3400 {
3401 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3402 LONGEST upper, lower;
3404
3405 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3406 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3407 upper = ~upper;
3408
3409 memcpy (buf, &lower, size);
3410 memcpy (buf + size, &upper, size);
3411 }
3412 }
3413 else if (i386_k_regnum_p (gdbarch, regnum))
3414 {
3415 regnum -= tdep->k0_regnum;
3416
3417 /* Extract (always little endian). */
3418 status = regcache->raw_read (tdep->k0_regnum + regnum, raw_buf);
3419 if (status != REG_VALID)
3420 mark_value_bytes_unavailable (result_value, 0, 8);
3421 else
3422 memcpy (buf, raw_buf, 8);
3423 }
3424 else if (i386_zmm_regnum_p (gdbarch, regnum))
3425 {
3426 regnum -= tdep->zmm0_regnum;
3427
3429 {
3430 /* Extract (always little endian). Read lower 128bits. */
3432 raw_buf);
3433 if (status != REG_VALID)
3434 mark_value_bytes_unavailable (result_value, 0, 16);
3435 else
3436 memcpy (buf, raw_buf, 16);
3437
3438 /* Extract (always little endian). Read upper 128bits. */
3440 raw_buf);
3441 if (status != REG_VALID)
3442 mark_value_bytes_unavailable (result_value, 16, 16);
3443 else
3444 memcpy (buf + 16, raw_buf, 16);
3445 }
3446 else
3447 {
3448 /* Extract (always little endian). Read lower 128bits. */
3451 raw_buf);
3452 if (status != REG_VALID)
3453 mark_value_bytes_unavailable (result_value, 0, 16);
3454 else
3455 memcpy (buf, raw_buf, 16);
3456
3457 /* Extract (always little endian). Read upper 128bits. */
3460 raw_buf);
3461 if (status != REG_VALID)
3462 mark_value_bytes_unavailable (result_value, 16, 16);
3463 else
3464 memcpy (buf + 16, raw_buf, 16);
3465 }
3466
3467 /* Read upper 256bits. */
3469 raw_buf);
3470 if (status != REG_VALID)
3471 mark_value_bytes_unavailable (result_value, 32, 32);
3472 else
3473 memcpy (buf + 32, raw_buf, 32);
3474 }
3475 else if (i386_ymm_regnum_p (gdbarch, regnum))
3476 {
3477 regnum -= tdep->ymm0_regnum;
3478
3479 /* Extract (always little endian). Read lower 128bits. */
3481 raw_buf);
3482 if (status != REG_VALID)
3483 mark_value_bytes_unavailable (result_value, 0, 16);
3484 else
3485 memcpy (buf, raw_buf, 16);
3486 /* Read upper 128bits. */
3488 raw_buf);
3489 if (status != REG_VALID)
3490 mark_value_bytes_unavailable (result_value, 16, 32);
3491 else
3492 memcpy (buf + 16, raw_buf, 16);
3493 }
3495 {
3496 regnum -= tdep->ymm16_regnum;
3497 /* Extract (always little endian). Read lower 128bits. */
3499 raw_buf);
3500 if (status != REG_VALID)
3501 mark_value_bytes_unavailable (result_value, 0, 16);
3502 else
3503 memcpy (buf, raw_buf, 16);
3504 /* Read upper 128bits. */
3506 raw_buf);
3507 if (status != REG_VALID)
3508 mark_value_bytes_unavailable (result_value, 16, 16);
3509 else
3510 memcpy (buf + 16, raw_buf, 16);
3511 }
3512 else if (i386_word_regnum_p (gdbarch, regnum))
3513 {
3514 int gpnum = regnum - tdep->ax_regnum;
3515
3516 /* Extract (always little endian). */
3517 status = regcache->raw_read (gpnum, raw_buf);
3518 if (status != REG_VALID)
3519 mark_value_bytes_unavailable (result_value, 0,
3520 value_type (result_value)->length ());
3521 else
3522 memcpy (buf, raw_buf, 2);
3523 }
3524 else if (i386_byte_regnum_p (gdbarch, regnum))
3525 {
3526 int gpnum = regnum - tdep->al_regnum;
3527
3528 /* Extract (always little endian). We read both lower and
3529 upper registers. */
3530 status = regcache->raw_read (gpnum % 4, raw_buf);
3531 if (status != REG_VALID)
3532 mark_value_bytes_unavailable (result_value, 0,
3533 value_type (result_value)->length ());
3534 else if (gpnum >= 4)
3535 memcpy (buf, raw_buf + 1, 1);
3536 else
3537 memcpy (buf, raw_buf, 1);
3538 }
3539 else
3540 internal_error (_("invalid regnum"));
3541 }
3542}
3543
3544static struct value *
3547 int regnum)
3548{
3549 struct value *result;
3550
3552 VALUE_LVAL (result) = lval_register;
3553 VALUE_REGNUM (result) = regnum;
3554
3556
3557 return result;
3558}
3559
3560void
3562 int regnum, const gdb_byte *buf)
3563{
3564 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3565
3567 {
3569
3570 /* Read ... */
3571 regcache->raw_read (fpnum, raw_buf);
3572 /* ... Modify ... (always little endian). */
3573 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3574 /* ... Write. */
3575 regcache->raw_write (fpnum, raw_buf);
3576 }
3577 else
3578 {
3579 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3580
3582 {
3583 ULONGEST upper, lower;
3585 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3586
3587 /* New values from input value. */
3588 regnum -= tdep->bnd0_regnum;
3589 lower = extract_unsigned_integer (buf, size, byte_order);
3590 upper = extract_unsigned_integer (buf + size, size, byte_order);
3591
3592 /* Fetching register buffer. */
3594 raw_buf);
3595
3596 upper = ~upper;
3597
3598 /* Set register bits. */
3599 memcpy (raw_buf, &lower, 8);
3600 memcpy (raw_buf + 8, &upper, 8);
3601
3602 regcache->raw_write (I387_BND0R_REGNUM (tdep) + regnum, raw_buf);
3603 }
3604 else if (i386_k_regnum_p (gdbarch, regnum))
3605 {
3606 regnum -= tdep->k0_regnum;
3607
3608 regcache->raw_write (tdep->k0_regnum + regnum, buf);
3609 }
3610 else if (i386_zmm_regnum_p (gdbarch, regnum))
3611 {
3612 regnum -= tdep->zmm0_regnum;
3613
3615 {
3616 /* Write lower 128bits. */
3617 regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf);
3618 /* Write upper 128bits. */
3619 regcache->raw_write (I387_YMM0_REGNUM (tdep) + regnum, buf + 16);
3620 }
3621 else
3622 {
3623 /* Write lower 128bits. */
3625 - num_lower_zmm_regs, buf);
3626 /* Write upper 128bits. */
3628 - num_lower_zmm_regs, buf + 16);
3629 }
3630 /* Write upper 256bits. */
3631 regcache->raw_write (tdep->zmm0h_regnum + regnum, buf + 32);
3632 }
3633 else if (i386_ymm_regnum_p (gdbarch, regnum))
3634 {
3635 regnum -= tdep->ymm0_regnum;
3636
3637 /* ... Write lower 128bits. */
3638 regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf);
3639 /* ... Write upper 128bits. */
3640 regcache->raw_write (tdep->ymm0h_regnum + regnum, buf + 16);
3641 }
3643 {
3644 regnum -= tdep->ymm16_regnum;
3645
3646 /* ... Write lower 128bits. */
3647 regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum, buf);
3648 /* ... Write upper 128bits. */
3649 regcache->raw_write (tdep->ymm16h_regnum + regnum, buf + 16);
3650 }
3651 else if (i386_word_regnum_p (gdbarch, regnum))
3652 {
3653 int gpnum = regnum - tdep->ax_regnum;
3654
3655 /* Read ... */
3656 regcache->raw_read (gpnum, raw_buf);
3657 /* ... Modify ... (always little endian). */
3658 memcpy (raw_buf, buf, 2);
3659 /* ... Write. */
3660 regcache->raw_write (gpnum, raw_buf);
3661 }
3662 else if (i386_byte_regnum_p (gdbarch, regnum))
3663 {
3664 int gpnum = regnum - tdep->al_regnum;
3665
3666 /* Read ... We read both lower and upper registers. */
3667 regcache->raw_read (gpnum % 4, raw_buf);
3668 /* ... Modify ... (always little endian). */
3669 if (gpnum >= 4)
3670 memcpy (raw_buf + 1, buf, 1);
3671 else
3672 memcpy (raw_buf, buf, 1);
3673 /* ... Write. */
3674 regcache->raw_write (gpnum % 4, raw_buf);
3675 }
3676 else
3677 internal_error (_("invalid regnum"));
3678 }
3679}
3680
3681/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3682
3683int
3685 struct agent_expr *ax, int regnum)
3686{
3687 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3688
3690 {
3691 /* MMX to FPU register mapping depends on current TOS. Let's just
3692 not care and collect everything... */
3693 int i;
3694
3695 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
3696 for (i = 0; i < 8; i++)
3697 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
3698 return 0;
3699 }
3700 else if (i386_bnd_regnum_p (gdbarch, regnum))
3701 {
3702 regnum -= tdep->bnd0_regnum;
3703 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
3704 return 0;
3705 }
3706 else if (i386_k_regnum_p (gdbarch, regnum))
3707 {
3708 regnum -= tdep->k0_regnum;
3709 ax_reg_mask (ax, tdep->k0_regnum + regnum);
3710 return 0;
3711 }
3712 else if (i386_zmm_regnum_p (gdbarch, regnum))
3713 {
3714 regnum -= tdep->zmm0_regnum;
3716 {
3717 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3718 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3719 }
3720 else
3721 {
3726 }
3727 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
3728 return 0;
3729 }
3730 else if (i386_ymm_regnum_p (gdbarch, regnum))
3731 {
3732 regnum -= tdep->ymm0_regnum;
3733 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3734 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3735 return 0;
3736 }
3738 {
3739 regnum -= tdep->ymm16_regnum;
3740 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
3741 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
3742 return 0;
3743 }
3744 else if (i386_word_regnum_p (gdbarch, regnum))
3745 {
3746 int gpnum = regnum - tdep->ax_regnum;
3747
3748 ax_reg_mask (ax, gpnum);
3749 return 0;
3750 }
3751 else if (i386_byte_regnum_p (gdbarch, regnum))
3752 {
3753 int gpnum = regnum - tdep->al_regnum;
3754
3755 ax_reg_mask (ax, gpnum % 4);
3756 return 0;
3757 }
3758 else
3759 internal_error (_("invalid regnum"));
3760 return 1;
3761}
3762
3763
3764/* Return the register number of the register allocated by GCC after
3765 REGNUM, or -1 if there is no such register. */
3766
3767static int
3769{
3770 /* GCC allocates the registers in the order:
3771
3772 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3773
3774 Since storing a variable in %esp doesn't make any sense we return
3775 -1 for %ebp and for %esp itself. */
3776 static int next_regnum[] =
3777 {
3778 I386_EDX_REGNUM, /* Slot for %eax. */
3779 I386_EBX_REGNUM, /* Slot for %ecx. */
3780 I386_ECX_REGNUM, /* Slot for %edx. */
3781 I386_ESI_REGNUM, /* Slot for %ebx. */
3782 -1, -1, /* Slots for %esp and %ebp. */
3783 I386_EDI_REGNUM, /* Slot for %esi. */
3784 I386_EBP_REGNUM /* Slot for %edi. */
3785 };
3786
3787 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3788 return next_regnum[regnum];
3789
3790 return -1;
3791}
3792
3793/* Return nonzero if a value of type TYPE stored in register REGNUM
3794 needs any special handling. */
3795
3796static int
3798 int regnum, struct type *type)
3799{
3800 int len = type->length ();
3801
3802 /* Values may be spread across multiple registers. Most debugging
3803 formats aren't expressive enough to specify the locations, so
3804 some heuristics is involved. Right now we only handle types that
3805 have a length that is a multiple of the word size, since GCC
3806 doesn't seem to put any other types into registers. */
3807 if (len > 4 && len % 4 == 0)
3808 {
3809 int last_regnum = regnum;
3810
3811 while (len > 4)
3812 {
3813 last_regnum = i386_next_regnum (last_regnum);
3814 len -= 4;
3815 }
3816
3817 if (last_regnum != -1)
3818 return 1;
3819 }
3820
3822}
3823
3824/* Read a value of type TYPE from register REGNUM in frame FRAME, and
3825 return its contents in TO. */
3826
3827static int
3829 struct type *type, gdb_byte *to,
3830 int *optimizedp, int *unavailablep)
3831{
3832 struct gdbarch *gdbarch = get_frame_arch (frame);
3833 int len = type->length ();
3834
3836 return i387_register_to_value (frame, regnum, type, to,
3837 optimizedp, unavailablep);
3838
3839 /* Read a value spread across multiple registers. */
3840
3841 gdb_assert (len > 4 && len % 4 == 0);
3842
3843 while (len > 0)
3844 {
3845 gdb_assert (regnum != -1);
3846 gdb_assert (register_size (gdbarch, regnum) == 4);
3847
3848 if (!get_frame_register_bytes (frame, regnum, 0,
3849 gdb::make_array_view (to,
3851 regnum)),
3852 optimizedp, unavailablep))
3853 return 0;
3854
3856 len -= 4;
3857 to += 4;
3858 }
3859
3860 *optimizedp = *unavailablep = 0;
3861 return 1;
3862}
3863
3864/* Write the contents FROM of a value of type TYPE into register
3865 REGNUM in frame FRAME. */
3866
3867static void
3869 struct type *type, const gdb_byte *from)
3870{
3871 int len = type->length ();
3872
3873 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3874 {
3875 i387_value_to_register (frame, regnum, type, from);
3876 return;
3877 }
3878
3879 /* Write a value spread across multiple registers. */
3880
3881 gdb_assert (len > 4 && len % 4 == 0);
3882
3883 while (len > 0)
3884 {
3885 gdb_assert (regnum != -1);
3886 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3887
3888 put_frame_register (frame, regnum, from);
3890 len -= 4;
3891 from += 4;
3892 }
3893}
3894
3895/* Supply register REGNUM from the buffer specified by GREGS and LEN
3896 in the general-purpose register set REGSET to register cache
3897 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3898
3899void
3901 int regnum, const void *gregs, size_t len)
3902{
3903 struct gdbarch *gdbarch = regcache->arch ();
3904 const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3905 const gdb_byte *regs = (const gdb_byte *) gregs;
3906 int i;
3907
3908 gdb_assert (len >= tdep->sizeof_gregset);
3909
3910 for (i = 0; i < tdep->gregset_num_regs; i++)
3911 {
3912 if ((regnum == i || regnum == -1)
3913 && tdep->gregset_reg_offset[i] != -1)
3914 regcache->raw_supply (i, regs + tdep->gregset_reg_offset[i]);
3915 }
3916}
3917
3918/* Collect register REGNUM from the register cache REGCACHE and store
3919 it in the buffer specified by GREGS and LEN as described by the
3920 general-purpose register set REGSET. If REGNUM is -1, do this for
3921 all registers in REGSET. */
3922
3923static void
3925 const struct regcache *regcache,
3926 int regnum, void *gregs, size_t len)
3927{
3928 struct gdbarch *gdbarch = regcache->arch ();
3929 const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3930 gdb_byte *regs = (gdb_byte *) gregs;
3931 int i;
3932
3933 gdb_assert (len >= tdep->sizeof_gregset);
3934
3935 for (i = 0; i < tdep->gregset_num_regs; i++)
3936 {
3937 if ((regnum == i || regnum == -1)
3938 && tdep->gregset_reg_offset[i] != -1)
3939 regcache->raw_collect (i, regs + tdep->gregset_reg_offset[i]);
3940 }
3941}
3942
3943/* Supply register REGNUM from the buffer specified by FPREGS and LEN
3944 in the floating-point register set REGSET to register cache
3945 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3946
3947static void
3949 int regnum, const void *fpregs, size_t len)
3950{
3951 struct gdbarch *gdbarch = regcache->arch ();
3952 const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3953
3954 if (len == I387_SIZEOF_FXSAVE)
3955 {
3957 return;
3958 }
3959
3960 gdb_assert (len >= tdep->sizeof_fpregset);
3962}
3963
3964/* Collect register REGNUM from the register cache REGCACHE and store
3965 it in the buffer specified by FPREGS and LEN as described by the
3966 floating-point register set REGSET. If REGNUM is -1, do this for
3967 all registers in REGSET. */
3968
3969static void
3971 const struct regcache *regcache,
3972 int regnum, void *fpregs, size_t len)
3973{
3974 struct gdbarch *gdbarch = regcache->arch ();
3975 const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
3976
3977 if (len == I387_SIZEOF_FXSAVE)
3978 {
3980 return;
3981 }
3982
3983 gdb_assert (len >= tdep->sizeof_fpregset);
3985}
3986
3987/* Register set definitions. */
3988
3989const struct regset i386_gregset =
3990 {
3992 };
3993
3994const struct regset i386_fpregset =
3995 {
3997 };
3998
3999/* Default iterator over core file register note sections. */
4000
4001void
4004 void *cb_data,
4005 const struct regcache *regcache)
4006{
4007 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
4008
4009 cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, &i386_gregset, NULL,
4010 cb_data);
4011 if (tdep->sizeof_fpregset)
4012 cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset,
4013 NULL, cb_data);
4014}
4015
4016
4017/* Stuff for WIN32 PE style DLL's but is pretty generic really. */
4018
4019CORE_ADDR
4021 CORE_ADDR pc, char *name)
4022{
4023 struct gdbarch *gdbarch = get_frame_arch (frame);
4024 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4025
4026 /* jmp *(dest) */
4027 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
4028 {
4029 unsigned long indirect =
4030 read_memory_unsigned_integer (pc + 2, 4, byte_order);
4031 struct minimal_symbol *indsym =
4032 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
4033 const char *symname = indsym ? indsym->linkage_name () : 0;
4034
4035 if (symname)
4036 {
4037 if (startswith (symname, "__imp_")
4038 || startswith (symname, "_imp_"))
4039 return name ? 1 :
4040 read_memory_unsigned_integer (indirect, 4, byte_order);
4041 }
4042 }
4043 return 0; /* Not a trampoline. */
4044}
4045
4046
4047/* Return whether the THIS_FRAME corresponds to a sigtramp
4048 routine. */
4049
4050int
4052{
4053 CORE_ADDR pc = get_frame_pc (this_frame);
4054 const char *name;
4055
4056 find_pc_partial_function (pc, &name, NULL, NULL);
4057 return (name && strcmp ("_sigtramp", name) == 0);
4058}
4059
4060
4061/* We have two flavours of disassembly. The machinery on this page
4062 deals with switching between those. */
4063
4064static int
4065i386_print_insn (bfd_vma pc, struct disassemble_info *info)
4066{
4067 gdb_assert (disassembly_flavor == att_flavor
4069
4070 info->disassembler_options = disassembly_flavor;
4071
4072 return default_print_insn (pc, info);
4073}
4074
4075
4076/* There are a few i386 architecture variants that differ only
4077 slightly from the generic i386 target. For now, we don't give them
4078 their own source file, but include them here. As a consequence,
4079 they'll always be included. */
4080
4081/* System V Release 4 (SVR4). */
4082
4083/* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4084 routine. */
4085
4086static int
4088{
4089 CORE_ADDR pc = get_frame_pc (this_frame);
4090 const char *name;
4091
4092 /* The origin of these symbols is currently unknown. */
4093 find_pc_partial_function (pc, &name, NULL, NULL);
4094 return (name && (strcmp ("_sigreturn", name) == 0
4095 || strcmp ("sigvechandler", name) == 0));
4096}
4097
4098/* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4099 address of the associated sigcontext (ucontext) structure. */
4100
4101static CORE_ADDR
4103{
4104 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4105 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4106 gdb_byte buf[4];
4107 CORE_ADDR sp;
4108
4109 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
4110 sp = extract_unsigned_integer (buf, 4, byte_order);
4111
4112 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
4113}
4114
4115
4116
4117/* Implementation of `gdbarch_stap_is_single_operand', as defined in
4118 gdbarch.h. */
4119
4120int
4122{
4123 return (*s == '$' /* Literal number. */
4124 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
4125 || (*s == '(' && s[1] == '%') /* Register indirection. */
4126 || (*s == '%' && isalpha (s[1]))); /* Register access. */
4127}
4128
4129/* Helper function for i386_stap_parse_special_token.
4130
4131 This function parses operands of the form `-8+3+1(%rbp)', which
4132 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4133
4134 Return true if the operand was parsed successfully, false
4135 otherwise. */
4136
4137static expr::operation_up
4139 struct stap_parse_info *p)
4140{
4141 const char *s = p->arg;
4142
4143 if (isdigit (*s) || *s == '-' || *s == '+')
4144 {
4145 bool got_minus[3];
4146 int i;
4147 long displacements[3];
4148 const char *start;
4149 int len;
4150 char *endp;
4151
4152 got_minus[0] = false;
4153 if (*s == '+')
4154 ++s;
4155 else if (*s == '-')
4156 {
4157 ++s;
4158 got_minus[0] = true;
4159 }
4160
4161 if (!isdigit ((unsigned char) *s))
4162 return {};
4163
4164 displacements[0] = strtol (s, &endp, 10);
4165 s = endp;
4166
4167 if (*s != '+' && *s != '-')
4168 {
4169 /* We are not dealing with a triplet. */
4170 return {};
4171 }
4172
4173 got_minus[1] = false;
4174 if (*s == '+')
4175 ++s;
4176 else
4177 {
4178 ++s;
4179 got_minus[1] = true;
4180 }
4181
4182 if (!isdigit ((unsigned char) *s))
4183 return {};
4184
4185 displacements[1] = strtol (s, &endp, 10);
4186 s = endp;
4187
4188 if (*s != '+' && *s != '-')
4189 {
4190 /* We are not dealing with a triplet. */
4191 return {};
4192 }
4193
4194 got_minus[2] = false;
4195 if (*s == '+')
4196 ++s;
4197 else
4198 {
4199 ++s;
4200 got_minus[2] = true;
4201 }
4202
4203 if (!isdigit ((unsigned char) *s))
4204 return {};
4205
4206 displacements[2] = strtol (s, &endp, 10);
4207 s = endp;
4208
4209 if (*s != '(' || s[1] != '%')
4210 return {};
4211
4212 s += 2;
4213 start = s;
4214
4215 while (isalnum (*s))
4216 ++s;
4217
4218 if (*s++ != ')')
4219 return {};
4220
4221 len = s - start - 1;
4222 std::string regname (start, len);
4223
4224 if (user_reg_map_name_to_regnum (gdbarch, regname.c_str (), len) == -1)
4225 error (_("Invalid register name `%s' on expression `%s'."),
4226 regname.c_str (), p->saved_arg);
4227
4228 LONGEST value = 0;
4229 for (i = 0; i < 3; i++)
4230 {
4231 LONGEST this_val = displacements[i];
4232 if (got_minus[i])
4233 this_val = -this_val;
4234 value += this_val;
4235 }
4236
4237 p->arg = s;
4238
4239 using namespace expr;
4240
4241 struct type *long_type = builtin_type (gdbarch)->builtin_long;
4242 operation_up offset
4243 = make_operation<long_const_operation> (long_type, value);
4244
4245 operation_up reg
4246 = make_operation<register_operation> (std::move (regname));
4247 struct type *void_ptr = builtin_type (gdbarch)->builtin_data_ptr;
4248 reg = make_operation<unop_cast_operation> (std::move (reg), void_ptr);
4249
4250 operation_up sum
4251 = make_operation<add_operation> (std::move (reg), std::move (offset));
4252 struct type *arg_ptr_type = lookup_pointer_type (p->arg_type);
4253 sum = make_operation<unop_cast_operation> (std::move (sum),
4254 arg_ptr_type);
4255 return make_operation<unop_ind_operation> (std::move (sum));
4256 }
4257
4258 return {};
4259}
4260
4261/* Helper function for i386_stap_parse_special_token.
4262
4263 This function parses operands of the form `register base +
4264 (register index * size) + offset', as represented in
4265 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4266
4267 Return true if the operand was parsed successfully, false
4268 otherwise. */
4269
4270static expr::operation_up
4272 struct stap_parse_info *p)
4273{
4274 const char *s = p->arg;
4275
4276 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4277 {
4278 bool offset_minus = false;
4279 long offset = 0;
4280 bool size_minus = false;
4281 long size = 0;
4282 const char *start;
4283 int len_base;
4284 int len_index;
4285
4286 if (*s == '+')
4287 ++s;
4288 else if (*s == '-')
4289 {
4290 ++s;
4291 offset_minus = true;
4292 }
4293
4294 if (offset_minus && !isdigit (*s))
4295 return {};
4296
4297 if (isdigit (*s))
4298 {
4299 char *endp;
4300
4301 offset = strtol (s, &endp, 10);
4302 s = endp;
4303 }
4304
4305 if (*s != '(' || s[1] != '%')
4306 return {};
4307
4308 s += 2;
4309 start = s;
4310
4311 while (isalnum (*s))
4312 ++s;
4313
4314 if (*s != ',' || s[1] != '%')
4315 return {};
4316
4317 len_base = s - start;
4318 std::string base (start, len_base);
4319
4320 if (user_reg_map_name_to_regnum (gdbarch, base.c_str (), len_base) == -1)
4321 error (_("Invalid register name `%s' on expression `%s'."),
4322 base.c_str (), p->saved_arg);
4323
4324 s += 2;
4325 start = s;
4326
4327 while (isalnum (*s))
4328 ++s;
4329
4330 len_index = s - start;
4331 std::string index (start, len_index);
4332
4333 if (user_reg_map_name_to_regnum (gdbarch, index.c_str (),
4334 len_index) == -1)
4335 error (_("Invalid register name `%s' on expression `%s'."),
4336 index.c_str (), p->saved_arg);
4337
4338 if (*s != ',' && *s != ')')
4339 return {};
4340
4341 if (*s == ',')
4342 {
4343 char *endp;
4344
4345 ++s;
4346 if (*s == '+')
4347 ++s;
4348 else if (*s == '-')
4349 {
4350 ++s;
4351 size_minus = true;
4352 }
4353
4354 size = strtol (s, &endp, 10);
4355 s = endp;
4356
4357 if (*s != ')')
4358 return {};
4359 }
4360
4361 ++s;
4362 p->arg = s;
4363
4364 using namespace expr;
4365
4366 struct type *long_type = builtin_type (gdbarch)->builtin_long;
4367 operation_up reg = make_operation<register_operation> (std::move (base));
4368
4369 if (offset != 0)
4370 {
4371 if (offset_minus)
4372 offset = -offset;
4374 = make_operation<long_const_operation> (long_type, offset);
4375 reg = make_operation<add_operation> (std::move (reg),
4376 std::move (value));
4377 }
4378
4379 operation_up ind_reg
4380 = make_operation<register_operation> (std::move (index));
4381
4382 if (size != 0)
4383 {
4384 if (size_minus)
4385 size = -size;
4387 = make_operation<long_const_operation> (long_type, size);
4388 ind_reg = make_operation<mul_operation> (std::move (ind_reg),
4389 std::move (value));
4390 }
4391
4392 operation_up sum
4393 = make_operation<add_operation> (std::move (reg),
4394 std::move (ind_reg));
4395
4396 struct type *arg_ptr_type = lookup_pointer_type (p->arg_type);
4397 sum = make_operation<unop_cast_operation> (std::move (sum),
4398 arg_ptr_type);
4399 return make_operation<unop_ind_operation> (std::move (sum));
4400 }
4401
4402 return {};
4403}
4404
4405/* Implementation of `gdbarch_stap_parse_special_token', as defined in
4406 gdbarch.h. */
4407
4410 struct stap_parse_info *p)
4411{
4412 /* The special tokens to be parsed here are:
4413
4414 - `register base + (register index * size) + offset', as represented
4415 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4416
4417 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4418 `*(-8 + 3 - 1 + (void *) $eax)'. */
4419
4420 expr::operation_up result
4422
4423 if (result == nullptr)
4425
4426 return result;
4427}
4428
4429/* Implementation of 'gdbarch_stap_adjust_register', as defined in
4430 gdbarch.h. */
4431
4432static std::string
4434 const std::string &regname, int regnum)
4435{
4436 static const std::unordered_set<std::string> reg_assoc
4437 = { "ax", "bx", "cx", "dx",
4438 "si", "di", "bp", "sp" };
4439
4440 /* If we are dealing with a register whose size is less than the size
4441 specified by the "[-]N@" prefix, and it is one of the registers that
4442 we know has an extended variant available, then use the extended
4443 version of the register instead. */
4445 && reg_assoc.find (regname) != reg_assoc.end ())
4446 return "e" + regname;
4447
4448 /* Otherwise, just use the requested register. */
4449 return regname;
4450}
4451
4452
4453
4454/* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4455 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4456
4457static const char *
4459{
4460 return "(x86_64|i.86)";
4461}
4462
4463
4464
4465/* Implement the "in_indirect_branch_thunk" gdbarch function. */
4466
4467static bool
4469{
4472}
4473
4474/* Generic ELF. */
4475
4476void
4478{
4479 static const char *const stap_integer_prefixes[] = { "$", NULL };
4480 static const char *const stap_register_prefixes[] = { "%", NULL };
4481 static const char *const stap_register_indirection_prefixes[] = { "(",
4482 NULL };
4483 static const char *const stap_register_indirection_suffixes[] = { ")",
4484 NULL };
4485
4486 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4488
4489 /* Registering SystemTap handlers. */
4490 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4491 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4493 stap_register_indirection_prefixes);
4495 stap_register_indirection_suffixes);
4502
4505}
4506
4507/* System V Release 4 (SVR4). */
4508
4509void
4511{
4512 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
4513
4514 /* System V Release 4 uses ELF. */
4515 i386_elf_init_abi (info, gdbarch);
4516
4517 /* System V Release 4 has shared libraries. */
4519
4522 tdep->sc_pc_offset = 36 + 14 * 4;
4523 tdep->sc_sp_offset = 36 + 17 * 4;
4524
4525 tdep->jb_pc_offset = 20;
4526}
4527
4528
4529
4530/* i386 register groups. In addition to the normal groups, add "mmx"
4531 and "sse". */
4532
4535
4536static void
4538{
4541}
4542
4543static void
4545{
4548}
4549
4550int
4552 const struct reggroup *group)
4553{
4554 const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
4555 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4556 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4557 bndr_regnum_p, bnd_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4558 mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4559 avx512_p, avx_p, sse_p, pkru_regnum_p;
4560
4561 /* Don't include pseudo registers, except for MMX, in any register
4562 groups. */
4564 return 0;
4565
4567 return 0;
4568
4570 return 0;
4571
4572 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4573 if (group == i386_mmx_reggroup)
4574 return mmx_regnum_p;
4575
4576 pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum);
4577 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4578 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4579 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4580 if (group == i386_sse_reggroup)
4581 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4582
4583 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4584 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4585 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4586
4587 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4588 == X86_XSTATE_AVX_AVX512_MASK);
4589 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4590 == X86_XSTATE_AVX_MASK) && !avx512_p;
4591 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4592 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4593
4594 if (group == vector_reggroup)
4595 return (mmx_regnum_p
4596 || (zmm_regnum_p && avx512_p)
4597 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4598 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4599 || mxcsr_regnum_p);
4600
4601 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4603 if (group == float_reggroup)
4604 return fp_regnum_p;
4605
4606 /* For "info reg all", don't include upper YMM registers nor XMM
4607 registers when AVX is supported. */
4608 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4609 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4610 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4611 if (group == all_reggroup
4612 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4613 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4614 || ymmh_regnum_p
4615 || ymmh_avx512_regnum_p
4616 || zmmh_regnum_p))
4617 return 0;
4618
4619 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4620 if (group == all_reggroup
4621 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4622 return bnd_regnum_p;
4623
4624 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4625 if (group == all_reggroup
4626 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4627 return 0;
4628
4629 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4630 if (group == all_reggroup
4631 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4632 return mpx_ctrl_regnum_p;
4633
4634 if (group == general_reggroup)
4635 return (!fp_regnum_p
4636 && !mmx_regnum_p
4637 && !mxcsr_regnum_p
4638 && !xmm_regnum_p
4639 && !xmm_avx512_regnum_p
4640 && !ymm_regnum_p
4641 && !ymmh_regnum_p
4642 && !ymm_avx512_regnum_p
4643 && !ymmh_avx512_regnum_p
4644 && !bndr_regnum_p
4645 && !bnd_regnum_p
4646 && !mpx_ctrl_regnum_p
4647 && !zmm_regnum_p
4648 && !zmmh_regnum_p
4649 && !pkru_regnum_p);
4650
4652}
4653
4654
4655/* Get the ARGIth function argument for the current function. */
4656
4657static CORE_ADDR
4659 struct type *type)
4660{
4661 struct gdbarch *gdbarch = get_frame_arch (frame);
4662 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4663 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4664 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4665}
4666
4667#define PREFIX_REPZ 0x01
4668#define PREFIX_REPNZ 0x02
4669#define PREFIX_LOCK 0x04
4670#define PREFIX_DATA 0x08
4671#define PREFIX_ADDR 0x10
4672
4673/* operand size */
4674enum
4675{
4681};
4682
4683/* i386 arith/logic operations */
4684enum
4685{
4694};
4695
4697{
4700 CORE_ADDR orig_addr;
4701 CORE_ADDR addr;
4704 int override;
4705 uint8_t modrm;
4706 uint8_t mod, reg, rm;
4707 int ot;
4708 uint8_t rex_x;
4709 uint8_t rex_b;
4712 const int *regmap;
4713};
4714
4715/* Parse the "modrm" part of the memory address irp->addr points at.
4716 Returns -1 if something goes wrong, 0 otherwise. */
4717
4718static int
4720{
4721 struct gdbarch *gdbarch = irp->gdbarch;
4722
4723 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4724 return -1;
4725
4726 irp->addr++;
4727 irp->mod = (irp->modrm >> 6) & 3;
4728 irp->reg = (irp->modrm >> 3) & 7;
4729 irp->rm = irp->modrm & 7;
4730
4731 return 0;
4732}
4733
4734/* Extract the memory address that the current instruction writes to,
4735 and return it in *ADDR. Return -1 if something goes wrong. */
4736
4737static int
4738i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4739{
4740 struct gdbarch *gdbarch = irp->gdbarch;
4741 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4742 gdb_byte buf[4];
4743 ULONGEST offset64;
4744
4745 *addr = 0;
4746 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4747 {
4748 /* 32/64 bits */
4749 int havesib = 0;
4750 uint8_t scale = 0;
4751 uint8_t byte;
4752 uint8_t index = 0;
4753 uint8_t base = irp->rm;
4754
4755 if (base == 4)
4756 {
4757 havesib = 1;
4758 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4759 return -1;
4760 irp->addr++;
4761 scale = (byte >> 6) & 3;
4762 index = ((byte >> 3) & 7) | irp->rex_x;
4763 base = (byte & 7);
4764 }
4765 base |= irp->rex_b;
4766
4767 switch (irp->mod)
4768 {
4769 case 0:
4770 if ((base & 7) == 5)
4771 {
4772 base = 0xff;
4773 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4774 return -1;
4775 irp->addr += 4;
4776 *addr = extract_signed_integer (buf, 4, byte_order);
4777 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4778 *addr += irp->addr + irp->rip_offset;
4779 }
4780 break;
4781 case 1:
4782 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4783 return -1;
4784 irp->addr++;
4785 *addr = (int8_t) buf[0];
4786 break;
4787 case 2:
4788 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4789 return -1;
4790 *addr = extract_signed_integer (buf, 4, byte_order);
4791 irp->addr += 4;
4792 break;
4793 }
4794
4795 offset64 = 0;
4796 if (base != 0xff)
4797 {
4798 if (base == 4 && irp->popl_esp_hack)
4799 *addr += irp->popl_esp_hack;
4800 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4801 &offset64);
4802 }
4803 if (irp->aflag == 2)
4804 {
4805 *addr += offset64;
4806 }
4807 else
4808 *addr = (uint32_t) (offset64 + *addr);
4809
4810 if (havesib && (index != 4 || scale != 0))
4811 {
4812 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4813 &offset64);
4814 if (irp->aflag == 2)
4815 *addr += offset64 << scale;
4816 else
4817 *addr = (uint32_t) (*addr + (offset64 << scale));
4818 }
4819
4820 if (!irp->aflag)
4821 {
4822 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4823 address from 32-bit to 64-bit. */
4824 *addr = (uint32_t) *addr;
4825 }
4826 }
4827 else
4828 {
4829 /* 16 bits */
4830 switch (irp->mod)
4831 {
4832 case 0:
4833 if (irp->rm == 6)
4834 {
4835 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4836 return -1;
4837 irp->addr += 2;
4838 *addr = extract_signed_integer (buf, 2, byte_order);
4839 irp->rm = 0;
4840 goto no_rm;
4841 }
4842 break;
4843 case 1:
4844 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4845 return -1;
4846 irp->addr++;
4847 *addr = (int8_t) buf[0];
4848 break;
4849 case 2:
4850 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4851 return -1;
4852 irp->addr += 2;
4853 *addr = extract_signed_integer (buf, 2, byte_order);
4854 break;
4855 }
4856
4857 switch (irp->rm)
4858 {
4859 case 0:
4862 &offset64);
4863 *addr = (uint32_t) (*addr + offset64);
4866 &offset64);
4867 *addr = (uint32_t) (*addr + offset64);
4868 break;
4869 case 1:
4872 &offset64);
4873 *addr = (uint32_t) (*addr + offset64);
4876 &offset64);
4877 *addr = (uint32_t) (*addr + offset64);
4878 break;
4879 case 2:
4882 &offset64);
4883 *addr = (uint32_t) (*addr + offset64);
4886 &offset64);
4887 *addr = (uint32_t) (*addr + offset64);
4888 break;
4889 case 3:
4892 &offset64);
4893 *addr = (uint32_t) (*addr + offset64);
4896 &offset64);
4897 *addr = (uint32_t) (*addr + offset64);
4898 break;
4899 case 4:
4902 &offset64);
4903 *addr = (uint32_t) (*addr + offset64);
4904 break;
4905 case 5:
4908 &offset64);
4909 *addr = (uint32_t) (*addr + offset64);
4910 break;
4911 case 6:
4914 &offset64);
4915 *addr = (uint32_t) (*addr + offset64);
4916 break;
4917 case 7:
4920 &offset64);
4921 *addr = (uint32_t) (*addr + offset64);
4922 break;
4923 }
4924 *addr &= 0xffff;
4925 }
4926
4927 no_rm:
4928 return 0;
4929}
4930
4931/* Record the address and contents of the memory that will be changed
4932 by the current instruction. Return -1 if something goes wrong, 0
4933 otherwise. */
4934
4935static int
4937{
4938 struct gdbarch *gdbarch = irp->gdbarch;
4939 uint64_t addr;
4940
4941 if (irp->override >= 0)
4942 {
4944 {
4945 if (yquery (_("\
4946Process record ignores the memory change of instruction at address %s\n\
4947because it can't get the value of the segment register.\n\
4948Do you want to stop the program?"),
4949 paddress (gdbarch, irp->orig_addr)))
4950 return -1;
4951 }
4952
4953 return 0;
4954 }
4955
4956 if (i386_record_lea_modrm_addr (irp, &addr))
4957 return -1;
4958
4959 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4960 return -1;
4961
4962 return 0;
4963}
4964
4965/* Record the effects of a push operation. Return -1 if something
4966 goes wrong, 0 otherwise. */
4967
4968static int
4970{
4971 ULONGEST addr;
4972
4975 return -1;
4978 &addr);
4979 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4980 return -1;
4981
4982 return 0;
4983}
4984
4985
4986/* Defines contents to record. */
4987#define I386_SAVE_FPU_REGS 0xfffd
4988#define I386_SAVE_FPU_ENV 0xfffe
4989#define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4990
4991/* Record the values of the floating point registers which will be
4992 changed by the current instruction. Returns -1 if something is
4993 wrong, 0 otherwise. */
4994
4996 struct i386_record_s *ir,
4997 uint32_t iregnum)
4998{
4999 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
5000 int i;
5001
5002 /* Oza: Because of floating point insn push/pop of fpu stack is going to
5003 happen. Currently we store st0-st7 registers, but we need not store all
5004 registers all the time, in future we use ftag register and record only
5005 those who are not marked as an empty. */
5006
5007 if (I386_SAVE_FPU_REGS == iregnum)
5008 {
5009 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
5010 {
5012 return -1;
5013 }
5014 }
5015 else if (I386_SAVE_FPU_ENV == iregnum)
5016 {
5017 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5018 {
5020 return -1;
5021 }
5022 }
5023 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
5024 {
5025 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5027 return -1;
5028 }
5029 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
5030 (iregnum <= I387_FOP_REGNUM (tdep)))
5031 {
5032 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
5033 return -1;
5034 }
5035 else
5036 {
5037 /* Parameter error. */
5038 return -1;
5039 }
5040 if(I386_SAVE_FPU_ENV != iregnum)
5041 {
5042 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5043 {
5045 return -1;
5046 }
5047 }
5048 return 0;
5049}
5050
5051/* Parse the current instruction, and record the values of the
5052 registers and memory that will be changed by the current
5053 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5054
5055#define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5056 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5057
5058int
5060 CORE_ADDR input_addr)
5061{
5062 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5063 int prefixes = 0;
5064 int regnum = 0;
5065 uint32_t opcode;
5066 uint8_t opcode8;
5067 ULONGEST addr;
5068 gdb_byte buf[I386_MAX_REGISTER_SIZE];
5069 struct i386_record_s ir;
5070 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
5071 uint8_t rex_w = -1;
5072 uint8_t rex_r = 0;
5073
5074 memset (&ir, 0, sizeof (struct i386_record_s));
5075 ir.regcache = regcache;
5076 ir.addr = input_addr;
5077 ir.orig_addr = input_addr;
5078 ir.aflag = 1;
5079 ir.dflag = 1;
5080 ir.override = -1;
5081 ir.popl_esp_hack = 0;
5082 ir.regmap = tdep->record_regmap;
5083 ir.gdbarch = gdbarch;
5084
5085 if (record_debug > 1)
5086 gdb_printf (gdb_stdlog, "Process record: i386_process_record "
5087 "addr = %s\n",
5088 paddress (gdbarch, ir.addr));
5089
5090 /* prefixes */
5091 while (1)
5092 {
5093 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5094 return -1;
5095 ir.addr++;
5096 switch (opcode8) /* Instruction prefixes */
5097 {
5098 case REPE_PREFIX_OPCODE:
5099 prefixes |= PREFIX_REPZ;
5100 break;
5101 case REPNE_PREFIX_OPCODE:
5102 prefixes |= PREFIX_REPNZ;
5103 break;
5104 case LOCK_PREFIX_OPCODE:
5105 prefixes |= PREFIX_LOCK;
5106 break;
5107 case CS_PREFIX_OPCODE:
5109 break;
5110 case SS_PREFIX_OPCODE:
5112 break;
5113 case DS_PREFIX_OPCODE:
5115 break;
5116 case ES_PREFIX_OPCODE:
5118 break;
5119 case FS_PREFIX_OPCODE:
5121 break;
5122 case GS_PREFIX_OPCODE:
5124 break;
5125 case DATA_PREFIX_OPCODE:
5126 prefixes |= PREFIX_DATA;
5127 break;
5128 case ADDR_PREFIX_OPCODE:
5129 prefixes |= PREFIX_ADDR;
5130 break;
5131 case 0x40: /* i386 inc %eax */
5132 case 0x41: /* i386 inc %ecx */
5133 case 0x42: /* i386 inc %edx */
5134 case 0x43: /* i386 inc %ebx */
5135 case 0x44: /* i386 inc %esp */
5136 case 0x45: /* i386 inc %ebp */
5137 case 0x46: /* i386 inc %esi */
5138 case 0x47: /* i386 inc %edi */
5139 case 0x48: /* i386 dec %eax */
5140 case 0x49: /* i386 dec %ecx */
5141 case 0x4a: /* i386 dec %edx */
5142 case 0x4b: /* i386 dec %ebx */
5143 case 0x4c: /* i386 dec %esp */
5144 case 0x4d: /* i386 dec %ebp */
5145 case 0x4e: /* i386 dec %esi */
5146 case 0x4f: /* i386 dec %edi */
5147 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5148 {
5149 /* REX */
5150 rex_w = (opcode8 >> 3) & 1;
5151 rex_r = (opcode8 & 0x4) << 1;
5152 ir.rex_x = (opcode8 & 0x2) << 2;
5153 ir.rex_b = (opcode8 & 0x1) << 3;
5154 }
5155 else /* 32 bit target */
5156 goto out_prefixes;
5157 break;
5158 default:
5159 goto out_prefixes;
5160 break;
5161 }
5162 }
5163 out_prefixes:
5164 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5165 {
5166 ir.dflag = 2;
5167 }
5168 else
5169 {
5170 if (prefixes & PREFIX_DATA)
5171 ir.dflag ^= 1;
5172 }
5173 if (prefixes & PREFIX_ADDR)
5174 ir.aflag ^= 1;
5175 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5176 ir.aflag = 2;
5177
5178 /* Now check op code. */
5179 opcode = (uint32_t) opcode8;
5180 reswitch:
5181 switch (opcode)
5182 {
5183 case 0x0f:
5184 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5185 return -1;
5186 ir.addr++;
5187 opcode = (uint32_t) opcode8 | 0x0f00;
5188 goto reswitch;
5189 break;
5190
5191 case 0x00: /* arith & logic */
5192 case 0x01:
5193 case 0x02:
5194 case 0x03:
5195 case 0x04:
5196 case 0x05:
5197 case 0x08:
5198 case 0x09:
5199 case 0x0a:
5200 case 0x0b:
5201 case 0x0c:
5202 case 0x0d:
5203 case 0x10:
5204 case 0x11:
5205 case 0x12:
5206 case 0x13:
5207 case 0x14:
5208 case 0x15:
5209 case 0x18:
5210 case 0x19:
5211 case 0x1a:
5212 case 0x1b:
5213 case 0x1c:
5214 case 0x1d:
5215 case 0x20:
5216 case 0x21:
5217 case 0x22:
5218 case 0x23:
5219 case 0x24:
5220 case 0x25:
5221 case 0x28:
5222 case 0x29:
5223 case 0x2a:
5224 case 0x2b:
5225 case 0x2c:
5226 case 0x2d:
5227 case 0x30:
5228 case 0x31:
5229 case 0x32:
5230 case 0x33:
5231 case 0x34:
5232 case 0x35:
5233 case 0x38:
5234 case 0x39:
5235 case 0x3a:
5236 case 0x3b:
5237 case 0x3c:
5238 case 0x3d:
5239 if (((opcode >> 3) & 7) != OP_CMPL)
5240 {
5241 if ((opcode & 1) == 0)
5242 ir.ot = OT_BYTE;
5243 else
5244 ir.ot = ir.dflag + OT_WORD;
5245
5246 switch ((opcode >> 1) & 3)
5247 {
5248 case 0: /* OP Ev, Gv */
5249 if (i386_record_modrm (&ir))
5250 return -1;
5251 if (ir.mod != 3)
5252 {
5253 if (i386_record_lea_modrm (&ir))
5254 return -1;
5255 }
5256 else
5257 {
5258 ir.rm |= ir.rex_b;
5259 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5260 ir.rm &= 0x3;
5262 }
5263 break;
5264 case 1: /* OP Gv, Ev */
5265 if (i386_record_modrm (&ir))
5266 return -1;
5267 ir.reg |= rex_r;
5268 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5269 ir.reg &= 0x3;
5271 break;
5272 case 2: /* OP A, Iv */
5274 break;
5275 }
5276 }
5278 break;
5279
5280 case 0x80: /* GRP1 */
5281 case 0x81:
5282 case 0x82:
5283 case 0x83:
5284 if (i386_record_modrm (&ir))
5285 return -1;
5286
5287 if (ir.reg != OP_CMPL)
5288 {
5289 if ((opcode & 1) == 0)
5290 ir.ot = OT_BYTE;
5291 else
5292 ir.ot = ir.dflag + OT_WORD;
5293
5294 if (ir.mod != 3)
5295 {
5296 if (opcode == 0x83)
5297 ir.rip_offset = 1;
5298 else
5299 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5300 if (i386_record_lea_modrm (&ir))
5301 return -1;
5302 }
5303 else
5305 }
5307 break;
5308
5309 case 0x40: /* inc */
5310 case 0x41:
5311 case 0x42:
5312 case 0x43:
5313 case 0x44:
5314 case 0x45:
5315 case 0x46:
5316 case 0x47:
5317
5318 case 0x48: /* dec */
5319 case 0x49:
5320 case 0x4a:
5321 case 0x4b:
5322 case 0x4c:
5323 case 0x4d:
5324 case 0x4e:
5325 case 0x4f:
5326
5329 break;
5330
5331 case 0xf6: /* GRP3 */
5332 case 0xf7:
5333 if ((opcode & 1) == 0)
5334 ir.ot = OT_BYTE;
5335 else
5336 ir.ot = ir.dflag + OT_WORD;
5337 if (i386_record_modrm (&ir))
5338 return -1;
5339
5340 if (ir.mod != 3 && ir.reg == 0)
5341 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5342
5343 switch (ir.reg)
5344 {
5345 case 0: /* test */
5347 break;
5348 case 2: /* not */
5349 case 3: /* neg */
5350 if (ir.mod != 3)
5351 {
5352 if (i386_record_lea_modrm (&ir))
5353 return -1;
5354 }
5355 else
5356 {
5357 ir.rm |= ir.rex_b;
5358 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5359 ir.rm &= 0x3;
5361 }
5362 if (ir.reg == 3) /* neg */
5364 break;
5365 case 4: /* mul */
5366 case 5: /* imul */
5367 case 6: /* div */
5368 case 7: /* idiv */
5370 if (ir.ot != OT_BYTE)
5373 break;
5374 default:
5375 ir.addr -= 2;
5376 opcode = opcode << 8 | ir.modrm;
5377 goto no_support;
5378 break;
5379 }
5380 break;
5381
5382 case 0xfe: /* GRP4 */
5383 case 0xff: /* GRP5 */
5384 if (i386_record_modrm (&ir))
5385 return -1;
5386 if (ir.reg >= 2 && opcode == 0xfe)
5387 {
5388 ir.addr -= 2;
5389 opcode = opcode << 8 | ir.modrm;
5390 goto no_support;
5391 }
5392 switch (ir.reg)
5393 {
5394 case 0: /* inc */
5395 case 1: /* dec */
5396 if ((opcode & 1) == 0)
5397 ir.ot = OT_BYTE;
5398 else
5399 ir.ot = ir.dflag + OT_WORD;
5400 if (ir.mod != 3)
5401 {
5402 if (i386_record_lea_modrm (&ir))
5403 return -1;
5404 }
5405 else
5406 {
5407 ir.rm |= ir.rex_b;
5408 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5409 ir.rm &= 0x3;
5411 }
5413 break;
5414 case 2: /* call */
5415 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5416 ir.dflag = 2;
5417 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5418 return -1;
5420 break;
5421 case 3: /* lcall */
5423 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5424 return -1;
5426 break;
5427 case 4: /* jmp */
5428 case 5: /* ljmp */
5430 break;
5431 case 6: /* push */
5432 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5433 ir.dflag = 2;
5434 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5435 return -1;
5436 break;
5437 default:
5438 ir.addr -= 2;
5439 opcode = opcode << 8 | ir.modrm;
5440 goto no_support;
5441 break;
5442 }
5443 break;
5444
5445 case 0x84: /* test */
5446 case 0x85:
5447 case 0xa8:
5448 case 0xa9:
5450 break;
5451
5452 case 0x98: /* CWDE/CBW */
5454 break;
5455
5456 case 0x99: /* CDQ/CWD */
5459 break;
5460
5461 case 0x0faf: /* imul */
5462 case 0x69:
5463 case 0x6b:
5464 ir.ot = ir.dflag + OT_WORD;
5465 if (i386_record_modrm (&ir))
5466 return -1;
5467 if (opcode == 0x69)
5468 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5469 else if (opcode == 0x6b)
5470 ir.rip_offset = 1;
5471 ir.reg |= rex_r;
5472 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5473 ir.reg &= 0x3;
5476 break;
5477
5478 case 0x0fc0: /* xadd */
5479 case 0x0fc1:
5480 if ((opcode & 1) == 0)
5481 ir.ot = OT_BYTE;
5482 else
5483 ir.ot = ir.dflag + OT_WORD;
5484 if (i386_record_modrm (&ir))
5485 return -1;
5486 ir.reg |= rex_r;
5487 if (ir.mod == 3)
5488 {
5489 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5490 ir.reg &= 0x3;
5492 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5493 ir.rm &= 0x3;
5495 }
5496 else
5497 {
5498 if (i386_record_lea_modrm (&ir))
5499 return -1;
5500 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5501 ir.reg &= 0x3;
5503 }
5505 break;
5506
5507 case 0x0fb0: /* cmpxchg */
5508 case 0x0fb1:
5509 if ((opcode & 1) == 0)
5510 ir.ot = OT_BYTE;
5511 else
5512 ir.ot = ir.dflag + OT_WORD;
5513 if (i386_record_modrm (&ir))
5514 return -1;
5515 if (ir.mod == 3)
5516 {
5517 ir.reg |= rex_r;
5519 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5520 ir.reg &= 0x3;
5522 }
5523 else
5524 {
5526 if (i386_record_lea_modrm (&ir))
5527 return -1;
5528 }
5530 break;
5531
5532 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5533 if (i386_record_modrm (&ir))
5534 return -1;
5535 if (ir.mod == 3)
5536 {
5537 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5538 an extended opcode. rdrand has bits 110 (/6) and rdseed
5539 has bits 111 (/7). */
5540 if (ir.reg == 6 || ir.reg == 7)
5541 {
5542 /* The storage register is described by the 3 R/M bits, but the
5543 REX.B prefix may be used to give access to registers
5544 R8~R15. In this case ir.rex_b + R/M will give us the register
5545 in the range R8~R15.
5546
5547 REX.W may also be used to access 64-bit registers, but we
5548 already record entire registers and not just partial bits
5549 of them. */
5551 /* These instructions also set conditional bits. */
5553 break;
5554 }
5555 else
5556 {
5557 /* We don't handle this particular instruction yet. */
5558 ir.addr -= 2;
5559 opcode = opcode << 8 | ir.modrm;
5560 goto no_support;
5561 }
5562 }
5565 if (i386_record_lea_modrm (&ir))
5566 return -1;
5568 break;
5569
5570 case 0x50: /* push */
5571 case 0x51:
5572 case 0x52:
5573 case 0x53:
5574 case 0x54:
5575 case 0x55:
5576 case 0x56:
5577 case 0x57:
5578 case 0x68:
5579 case 0x6a:
5580 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5581 ir.dflag = 2;
5582 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5583 return -1;
5584 break;
5585
5586 case 0x06: /* push es */
5587 case 0x0e: /* push cs */
5588 case 0x16: /* push ss */
5589 case 0x1e: /* push ds */
5591 {
5592 ir.addr -= 1;
5593 goto no_support;
5594 }
5595 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5596 return -1;
5597 break;
5598
5599 case 0x0fa0: /* push fs */
5600 case 0x0fa8: /* push gs */
5602 {
5603 ir.addr -= 2;
5604 goto no_support;
5605 }
5606 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5607 return -1;
5608 break;
5609
5610 case 0x60: /* pusha */
5612 {
5613 ir.addr -= 1;
5614 goto no_support;
5615 }
5616 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5617 return -1;
5618 break;
5619
5620 case 0x58: /* pop */
5621 case 0x59:
5622 case 0x5a:
5623 case 0x5b:
5624 case 0x5c:
5625 case 0x5d:
5626 case 0x5e:
5627 case 0x5f:
5629 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5630 break;
5631
5632 case 0x61: /* popa */
5634 {
5635 ir.addr -= 1;
5636 goto no_support;
5637 }
5640 regnum++)
5642 break;
5643
5644 case 0x8f: /* pop */
5646 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5647 else
5648 ir.ot = ir.dflag + OT_WORD;
5649 if (i386_record_modrm (&ir))
5650 return -1;
5651 if (ir.mod == 3)
5653 else
5654 {
5655 ir.popl_esp_hack = 1 << ir.ot;
5656 if (i386_record_lea_modrm (&ir))
5657 return -1;
5658 }
5660 break;
5661
5662 case 0xc8: /* enter */
5664 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5665 ir.dflag = 2;
5666 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5667 return -1;
5668 break;
5669
5670 case 0xc9: /* leave */
5673 break;
5674
5675 case 0x07: /* pop es */
5677 {
5678 ir.addr -= 1;
5679 goto no_support;
5680 }
5684 break;
5685
5686 case 0x17: /* pop ss */
5688 {
5689 ir.addr -= 1;
5690 goto no_support;
5691 }
5695 break;
5696
5697 case 0x1f: /* pop ds */
5699 {
5700 ir.addr -= 1;
5701 goto no_support;
5702 }
5706 break;
5707
5708 case 0x0fa1: /* pop fs */
5712 break;
5713
5714 case 0x0fa9: /* pop gs */
5718 break;
5719
5720 case 0x88: /* mov */
5721 case 0x89:
5722 case 0xc6:
5723 case 0xc7:
5724 if ((opcode & 1) == 0)
5725 ir.ot = OT_BYTE;
5726 else
5727 ir.ot = ir.dflag + OT_WORD;
5728
5729 if (i386_record_modrm (&ir))
5730 return -1;
5731
5732 if (ir.mod != 3)
5733 {
5734 if (opcode == 0xc6 || opcode == 0xc7)
5735 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5736 if (i386_record_lea_modrm (&ir))
5737 return -1;
5738 }
5739 else
5740 {
5741 if (opcode == 0xc6 || opcode == 0xc7)
5742 ir.rm |= ir.rex_b;
5743 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5744 ir.rm &= 0x3;
5746 }
5747 break;
5748
5749 case 0x8a: /* mov */
5750 case 0x8b:
5751 if ((opcode & 1) == 0)
5752 ir.ot = OT_BYTE;
5753 else
5754 ir.ot = ir.dflag + OT_WORD;
5755 if (i386_record_modrm (&ir))
5756 return -1;
5757 ir.reg |= rex_r;
5758 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5759 ir.reg &= 0x3;
5761 break;
5762
5763 case 0x8c: /* mov seg */
5764 if (i386_record_modrm (&ir))
5765 return -1;
5766 if (ir.reg > 5)
5767 {
5768 ir.addr -= 2;
5769 opcode = opcode << 8 | ir.modrm;
5770 goto no_support;
5771 }
5772
5773 if (ir.mod == 3)
5775 else
5776 {
5777 ir.ot = OT_WORD;
5778 if (i386_record_lea_modrm (&ir))
5779 return -1;
5780 }
5781 break;
5782
5783 case 0x8e: /* mov seg */
5784 if (i386_record_modrm (&ir))
5785 return -1;
5786 switch (ir.reg)
5787 {
5788 case 0:
5790 break;
5791 case 2:
5793 break;
5794 case 3:
5796 break;
5797 case 4:
5799 break;
5800 case 5:
5802 break;
5803 default:
5804 ir.addr -= 2;
5805 opcode = opcode << 8 | ir.modrm;
5806 goto no_support;
5807 break;
5808 }
5811 break;
5812
5813 case 0x0fb6: /* movzbS */
5814 case 0x0fb7: /* movzwS */
5815 case 0x0fbe: /* movsbS */
5816 case 0x0fbf: /* movswS */
5817 if (i386_record_modrm (&ir))
5818 return -1;
5820 break;
5821
5822 case 0x8d: /* lea */
5823 if (i386_record_modrm (&ir))
5824 return -1;
5825 if (ir.mod == 3)
5826 {
5827 ir.addr -= 2;
5828 opcode = opcode << 8 | ir.modrm;
5829 goto no_support;
5830 }
5831 ir.ot = ir.dflag;
5832 ir.reg |= rex_r;
5833 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5834 ir.reg &= 0x3;
5836 break;
5837
5838 case 0xa0: /* mov EAX */
5839 case 0xa1:
5840
5841 case 0xd7: /* xlat */
5843 break;
5844
5845 case 0xa2: /* mov EAX */
5846 case 0xa3:
5847 if (ir.override >= 0)
5848 {
5850 {
5851 if (yquery (_("\
5852Process record ignores the memory change of instruction at address %s\n\
5853because it can't get the value of the segment register.\n\
5854Do you want to stop the program?"),
5855 paddress (gdbarch, ir.orig_addr)))
5856 return -1;
5857 }
5858 }
5859 else
5860 {
5861 if ((opcode & 1) == 0)
5862 ir.ot = OT_BYTE;
5863 else
5864 ir.ot = ir.dflag + OT_WORD;
5865 if (ir.aflag == 2)
5866 {
5867 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5868 return -1;
5869 ir.addr += 8;
5870 addr = extract_unsigned_integer (buf, 8, byte_order);
5871 }
5872 else if (ir.aflag)
5873 {
5874 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5875 return -1;
5876 ir.addr += 4;
5877 addr = extract_unsigned_integer (buf, 4, byte_order);
5878 }
5879 else
5880 {
5881 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5882 return -1;
5883 ir.addr += 2;
5884 addr = extract_unsigned_integer (buf, 2, byte_order);
5885 }
5886 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5887 return -1;
5888 }
5889 break;
5890
5891 case 0xb0: /* mov R, Ib */
5892 case 0xb1:
5893 case 0xb2:
5894 case 0xb3:
5895 case 0xb4:
5896 case 0xb5:
5897 case 0xb6:
5898 case 0xb7:
5900 ? ((opcode & 0x7) | ir.rex_b)
5901 : ((opcode & 0x7) & 0x3));
5902 break;
5903
5904 case 0xb8: /* mov R, Iv */
5905 case 0xb9:
5906 case 0xba:
5907 case 0xbb:
5908 case 0xbc:
5909 case 0xbd:
5910 case 0xbe:
5911 case 0xbf:
5912 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5913 break;
5914
5915 case 0x91: /* xchg R, EAX */
5916 case 0x92:
5917 case 0x93:
5918 case 0x94:
5919 case 0x95:
5920 case 0x96:
5921 case 0x97:
5924 break;
5925
5926 case 0x86: /* xchg Ev, Gv */
5927 case 0x87:
5928 if ((opcode & 1) == 0)
5929 ir.ot = OT_BYTE;
5930 else
5931 ir.ot = ir.dflag + OT_WORD;
5932 if (i386_record_modrm (&ir))
5933 return -1;
5934 if (ir.mod == 3)
5935 {
5936 ir.rm |= ir.rex_b;
5937 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5938 ir.rm &= 0x3;
5940 }
5941 else
5942 {
5943 if (i386_record_lea_modrm (&ir))
5944 return -1;
5945 }
5946 ir.reg |= rex_r;
5947 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5948 ir.reg &= 0x3;
5950 break;
5951
5952 case 0xc4: /* les Gv */
5953 case 0xc5: /* lds Gv */
5955 {
5956 ir.addr -= 1;
5957 goto no_support;
5958 }
5959 /* FALLTHROUGH */
5960 case 0x0fb2: /* lss Gv */
5961 case 0x0fb4: /* lfs Gv */
5962 case 0x0fb5: /* lgs Gv */
5963 if (i386_record_modrm (&ir))
5964 return -1;
5965 if (ir.mod == 3)
5966 {
5967 if (opcode > 0xff)
5968 ir.addr -= 3;
5969 else
5970 ir.addr -= 2;
5971 opcode = opcode << 8 | ir.modrm;
5972 goto no_support;
5973 }
5974 switch (opcode)
5975 {
5976 case 0xc4: /* les Gv */
5978 break;
5979 case 0xc5: /* lds Gv */
5981 break;
5982 case 0x0fb2: /* lss Gv */
5984 break;
5985 case 0x0fb4: /* lfs Gv */
5987 break;
5988 case 0x0fb5: /* lgs Gv */
5990 break;
5991 }
5995 break;
5996
5997 case 0xc0: /* shifts */
5998 case 0xc1:
5999 case 0xd0:
6000 case 0xd1:
6001 case 0xd2:
6002 case 0xd3:
6003 if ((opcode & 1) == 0)
6004 ir.ot = OT_BYTE;
6005 else
6006 ir.ot = ir.dflag + OT_WORD;
6007 if (i386_record_modrm (&ir))
6008 return -1;
6009 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
6010 {
6011 if (i386_record_lea_modrm (&ir))
6012 return -1;
6013 }
6014 else
6015 {
6016 ir.rm |= ir.rex_b;
6017 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
6018 ir.rm &= 0x3;
6020 }
6022 break;
6023
6024 case 0x0fa4:
6025 case 0x0fa5:
6026 case 0x0fac:
6027 case 0x0fad:
6028 if (i386_record_modrm (&ir))
6029 return -1;
6030 if (ir.mod == 3)
6031 {
6033 return -1;
6034 }
6035 else
6036 {
6037 if (i386_record_lea_modrm (&ir))
6038 return -1;
6039 }
6040 break;
6041
6042 case 0xd8: /* Floats. */
6043 case 0xd9:
6044 case 0xda:
6045 case 0xdb:
6046 case 0xdc:
6047 case 0xdd:
6048 case 0xde:
6049 case 0xdf:
6050 if (i386_record_modrm (&ir))
6051 return -1;
6052 ir.reg |= ((opcode & 7) << 3);
6053 if (ir.mod != 3)
6054 {
6055 /* Memory. */
6056 uint64_t addr64;
6057
6058 if (i386_record_lea_modrm_addr (&ir, &addr64))
6059 return -1;
6060 switch (ir.reg)
6061 {
6062 case 0x02:
6063 case 0x12:
6064 case 0x22:
6065 case 0x32:
6066 /* For fcom, ficom nothing to do. */
6067 break;
6068 case 0x03:
6069 case 0x13:
6070 case 0x23:
6071 case 0x33:
6072 /* For fcomp, ficomp pop FPU stack, store all. */
6074 return -1;
6075 break;
6076 case 0x00:
6077 case 0x01:
6078 case 0x04:
6079 case 0x05:
6080 case 0x06:
6081 case 0x07:
6082 case 0x10:
6083 case 0x11:
6084 case 0x14:
6085 case 0x15:
6086 case 0x16:
6087 case 0x17:
6088 case 0x20:
6089 case 0x21:
6090 case 0x24:
6091 case 0x25:
6092 case 0x26:
6093 case 0x27:
6094 case 0x30:
6095 case 0x31:
6096 case 0x34:
6097 case 0x35:
6098 case 0x36:
6099 case 0x37:
6100 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6101 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6102 of code, always affects st(0) register. */
6103 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6104 return -1;
6105 break;
6106 case 0x08:
6107 case 0x0a:
6108 case 0x0b:
6109 case 0x18:
6110 case 0x19:
6111 case 0x1a:
6112 case 0x1b:
6113 case 0x1d:
6114 case 0x28:
6115 case 0x29:
6116 case 0x2a:
6117 case 0x2b:
6118 case 0x38:
6119 case 0x39:
6120 case 0x3a:
6121 case 0x3b:
6122 case 0x3c:
6123 case 0x3d:
6124 switch (ir.reg & 7)
6125 {
6126 case 0:
6127 /* Handling fld, fild. */
6129 return -1;
6130 break;
6131 case 1:
6132 switch (ir.reg >> 4)
6133 {
6134 case 0:
6135 if (record_full_arch_list_add_mem (addr64, 4))
6136 return -1;
6137 break;
6138 case 2:
6139 if (record_full_arch_list_add_mem (addr64, 8))
6140 return -1;
6141 break;
6142 case 3:
6143 break;
6144 default:
6145 if (record_full_arch_list_add_mem (addr64, 2))
6146 return -1;
6147 break;
6148 }
6149 break;
6150 default:
6151 switch (ir.reg >> 4)
6152 {
6153 case 0:
6154 if (record_full_arch_list_add_mem (addr64, 4))
6155 return -1;
6156 if (3 == (ir.reg & 7))
6157 {
6158 /* For fstp m32fp. */
6159 if (i386_record_floats (gdbarch, &ir,
6161 return -1;
6162 }
6163 break;
6164 case 1:
6165 if (record_full_arch_list_add_mem (addr64, 4))
6166 return -1;
6167 if ((3 == (ir.reg & 7))
6168 || (5 == (ir.reg & 7))
6169 || (7 == (ir.reg & 7)))
6170 {
6171 /* For fstp insn. */
6172 if (i386_record_floats (gdbarch, &ir,
6174 return -1;
6175 }
6176 break;
6177 case 2:
6178 if (record_full_arch_list_add_mem (addr64, 8))
6179 return -1;
6180 if (3 == (ir.reg & 7))
6181 {
6182 /* For fstp m64fp. */
6183 if (i386_record_floats (gdbarch, &ir,
6185 return -1;
6186 }
6187 break;
6188 case 3:
6189 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6190 {
6191 /* For fistp, fbld, fild, fbstp. */
6192 if (i386_record_floats (gdbarch, &ir,
6194 return -1;
6195 }
6196 /* Fall through */
6197 default:
6198 if (record_full_arch_list_add_mem (addr64, 2))
6199 return -1;
6200 break;
6201 }
6202 break;
6203 }
6204 break;
6205 case 0x0c:
6206 /* Insn fldenv. */
6207 if (i386_record_floats (gdbarch, &ir,
6209 return -1;
6210 break;
6211 case 0x0d:
6212 /* Insn fldcw. */
6213 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6214 return -1;
6215 break;
6216 case 0x2c:
6217 /* Insn frstor. */
6218 if (i386_record_floats (gdbarch, &ir,
6220 return -1;
6221 break;
6222 case 0x0e:
6223 if (ir.dflag)
6224 {
6225 if (record_full_arch_list_add_mem (addr64, 28))
6226 return -1;
6227 }
6228 else
6229 {
6230 if (record_full_arch_list_add_mem (addr64, 14))
6231 return -1;
6232 }
6233 break;
6234 case 0x0f:
6235 case 0x2f:
6236 if (record_full_arch_list_add_mem (addr64, 2))
6237 return -1;
6238 /* Insn fstp, fbstp. */
6240 return -1;
6241 break;
6242 case 0x1f:
6243 case 0x3e:
6244 if (record_full_arch_list_add_mem (addr64, 10))
6245 return -1;
6246 break;
6247 case 0x2e:
6248 if (ir.dflag)
6249 {
6250 if (record_full_arch_list_add_mem (addr64, 28))
6251 return -1;
6252 addr64 += 28;
6253 }
6254 else
6255 {
6256 if (record_full_arch_list_add_mem (addr64, 14))
6257 return -1;
6258 addr64 += 14;
6259 }
6260 if (record_full_arch_list_add_mem (addr64, 80))
6261 return -1;
6262 /* Insn fsave. */
6263 if (i386_record_floats (gdbarch, &ir,
6265 return -1;
6266 break;
6267 case 0x3f:
6268 if (record_full_arch_list_add_mem (addr64, 8))
6269 return -1;
6270 /* Insn fistp. */
6272 return -1;
6273 break;
6274 default:
6275 ir.addr -= 2;
6276 opcode = opcode << 8 | ir.modrm;
6277 goto no_support;
6278 break;
6279 }
6280 }
6281 /* Opcode is an extension of modR/M byte. */
6282 else
6283 {
6284 switch (opcode)
6285 {
6286 case 0xd8:
6287 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6288 return -1;
6289 break;
6290 case 0xd9:
6291 if (0x0c == (ir.modrm >> 4))
6292 {
6293 if ((ir.modrm & 0x0f) <= 7)
6294 {
6295 if (i386_record_floats (gdbarch, &ir,
6297 return -1;
6298 }
6299 else
6300 {
6301 if (i386_record_floats (gdbarch, &ir,
6302 I387_ST0_REGNUM (tdep)))
6303 return -1;
6304 /* If only st(0) is changing, then we have already
6305 recorded. */
6306 if ((ir.modrm & 0x0f) - 0x08)
6307 {
6308 if (i386_record_floats (gdbarch, &ir,
6309 I387_ST0_REGNUM (tdep) +
6310 ((ir.modrm & 0x0f) - 0x08)))
6311 return -1;
6312 }
6313 }
6314 }
6315 else
6316 {
6317 switch (ir.modrm)
6318 {
6319 case 0xe0:
6320 case 0xe1:
6321 case 0xf0:
6322 case 0xf5:
6323 case 0xf8:
6324 case 0xfa:
6325 case 0xfc:
6326 case 0xfe:
6327 case 0xff:
6328 if (i386_record_floats (gdbarch, &ir,
6329 I387_ST0_REGNUM (tdep)))
6330 return -1;
6331 break;
6332 case 0xf1:
6333 case 0xf2:
6334 case 0xf3:
6335 case 0xf4:
6336 case 0xf6:
6337 case 0xf7:
6338 case 0xe8:
6339 case 0xe9:
6340 case 0xea:
6341 case 0xeb:
6342 case 0xec:
6343 case 0xed:
6344 case 0xee:
6345 case 0xf9:
6346 case 0xfb:
6347 if (i386_record_floats (gdbarch, &ir,
6349 return -1;
6350 break;
6351 case 0xfd:
6352 if (i386_record_floats (gdbarch, &ir,
6353 I387_ST0_REGNUM (tdep)))
6354 return -1;
6355 if (i386_record_floats (gdbarch, &ir,
6356 I387_ST0_REGNUM (tdep) + 1))
6357 return -1;
6358 break;
6359 }
6360 }
6361 break;
6362 case 0xda:
6363 if (0xe9 == ir.modrm)
6364 {
6366 return -1;
6367 }
6368 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6369 {
6370 if (i386_record_floats (gdbarch, &ir,
6371 I387_ST0_REGNUM (tdep)))
6372 return -1;
6373 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6374 {
6375 if (i386_record_floats (gdbarch, &ir,
6376 I387_ST0_REGNUM (tdep) +
6377 (ir.modrm & 0x0f)))
6378 return -1;
6379 }
6380 else if ((ir.modrm & 0x0f) - 0x08)
6381 {
6382 if (i386_record_floats (gdbarch, &ir,
6383 I387_ST0_REGNUM (tdep) +
6384 ((ir.modrm & 0x0f) - 0x08)))
6385 return -1;
6386 }
6387 }
6388 break;
6389 case 0xdb:
6390 if (0xe3 == ir.modrm)
6391 {
6393 return -1;
6394 }
6395 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6396 {
6397 if (i386_record_floats (gdbarch, &ir,
6398 I387_ST0_REGNUM (tdep)))
6399 return -1;
6400 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6401 {
6402 if (i386_record_floats (gdbarch, &ir,
6403 I387_ST0_REGNUM (tdep) +
6404 (ir.modrm & 0x0f)))
6405 return -1;
6406 }
6407 else if ((ir.modrm & 0x0f) - 0x08)
6408 {
6409 if (i386_record_floats (gdbarch, &ir,
6410 I387_ST0_REGNUM (tdep) +
6411 ((ir.modrm & 0x0f) - 0x08)))
6412 return -1;
6413 }
6414 }
6415 break;
6416 case 0xdc:
6417 if ((0x0c == ir.modrm >> 4)
6418 || (0x0d == ir.modrm >> 4)
6419 || (0x0f == ir.modrm >> 4))
6420 {
6421 if ((ir.modrm & 0x0f) <= 7)
6422 {
6423 if (i386_record_floats (gdbarch, &ir,
6424 I387_ST0_REGNUM (tdep) +
6425 (ir.modrm & 0x0f)))
6426 return -1;
6427 }
6428 else
6429 {
6430 if (i386_record_floats (gdbarch, &ir,
6431 I387_ST0_REGNUM (tdep) +
6432 ((ir.modrm & 0x0f) - 0x08)))
6433 return -1;
6434 }
6435 }
6436 break;
6437 case 0xdd:
6438 if (0x0c == ir.modrm >> 4)
6439 {
6440 if (i386_record_floats (gdbarch, &ir,
6441 I387_FTAG_REGNUM (tdep)))
6442 return -1;
6443 }
6444 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6445 {
6446 if ((ir.modrm & 0x0f) <= 7)
6447 {
6448 if (i386_record_floats (gdbarch, &ir,
6449 I387_ST0_REGNUM (tdep) +
6450 (ir.modrm & 0x0f)))
6451 return -1;
6452 }
6453 else
6454 {
6455 if (i386_record_floats (gdbarch, &ir,
6457 return -1;
6458 }
6459 }
6460 break;
6461 case 0xde:
6462 if ((0x0c == ir.modrm >> 4)
6463 || (0x0e == ir.modrm >> 4)
6464 || (0x0f == ir.modrm >> 4)
6465 || (0xd9 == ir.modrm))
6466 {
6468 return -1;
6469 }
6470 break;
6471 case 0xdf:
6472 if (0xe0 == ir.modrm)
6473 {
6476 return -1;
6477 }
6478 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6479 {
6481 return -1;
6482 }
6483 break;
6484 }
6485 }
6486 break;
6487 /* string ops */
6488 case 0xa4: /* movsS */
6489 case 0xa5:
6490 case 0xaa: /* stosS */
6491 case 0xab:
6492 case 0x6c: /* insS */
6493 case 0x6d:
6496 &addr);
6497 if (addr)
6498 {
6499 ULONGEST es, ds;
6500
6501 if ((opcode & 1) == 0)
6502 ir.ot = OT_BYTE;
6503 else
6504 ir.ot = ir.dflag + OT_WORD;
6507 &addr);
6508
6511 &es);
6514 &ds);
6515 if (ir.aflag && (es != ds))
6516 {
6517 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6519 {
6520 if (yquery (_("\
6521Process record ignores the memory change of instruction at address %s\n\
6522because it can't get the value of the segment register.\n\
6523Do you want to stop the program?"),
6524 paddress (gdbarch, ir.orig_addr)))
6525 return -1;
6526 }
6527 }
6528 else
6529 {
6530 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6531 return -1;
6532 }
6533
6534 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6536 if (opcode == 0xa4 || opcode == 0xa5)
6540 }
6541 break;
6542
6543 case 0xa6: /* cmpsS */
6544 case 0xa7:
6547 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6550 break;
6551
6552 case 0xac: /* lodsS */
6553 case 0xad:
6556 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6559 break;
6560
6561 case 0xae: /* scasS */
6562 case 0xaf:
6564 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6567 break;
6568
6569 case 0x6e: /* outsS */
6570 case 0x6f:
6572 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6575 break;
6576
6577 case 0xe4: /* port I/O */
6578 case 0xe5:
6579 case 0xec:
6580 case 0xed:
6583 break;
6584
6585 case 0xe6:
6586 case 0xe7:
6587 case 0xee:
6588 case 0xef:
6589 break;
6590
6591 /* control */
6592 case 0xc2: /* ret im */
6593 case 0xc3: /* ret */
6596 break;
6597
6598 case 0xca: /* lret im */
6599 case 0xcb: /* lret */
6600 case 0xcf: /* iret */
6604 break;
6605
6606 case 0xe8: /* call im */
6607 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6608 ir.dflag = 2;
6609 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6610 return -1;
6611 break;
6612
6613 case 0x9a: /* lcall im */
6615 {
6616 ir.addr -= 1;
6617 goto no_support;
6618 }
6620 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6621 return -1;
6622 break;
6623
6624 case 0xe9: /* jmp im */
6625 case 0xea: /* ljmp im */
6626 case 0xeb: /* jmp Jb */
6627 case 0x70: /* jcc Jb */
6628 case 0x71:
6629 case 0x72:
6630 case 0x73:
6631 case 0x74:
6632 case 0x75:
6633 case 0x76:
6634 case 0x77:
6635 case 0x78:
6636 case 0x79:
6637 case 0x7a:
6638 case 0x7b:
6639 case 0x7c:
6640 case 0x7d:
6641 case 0x7e:
6642 case 0x7f:
6643 case 0x0f80: /* jcc Jv */
6644 case 0x0f81:
6645 case 0x0f82:
6646 case 0x0f83:
6647 case 0x0f84:
6648 case 0x0f85:
6649 case 0x0f86:
6650 case 0x0f87:
6651 case 0x0f88:
6652 case 0x0f89:
6653 case 0x0f8a:
6654 case 0x0f8b:
6655 case 0x0f8c:
6656 case 0x0f8d:
6657 case 0x0f8e:
6658 case 0x0f8f:
6659 break;
6660
6661 case 0x0f90: /* setcc Gv */
6662 case 0x0f91:
6663 case 0x0f92:
6664 case 0x0f93:
6665 case 0x0f94:
6666 case 0x0f95:
6667 case 0x0f96:
6668 case 0x0f97:
6669 case 0x0f98:
6670 case 0x0f99:
6671 case 0x0f9a:
6672 case 0x0f9b:
6673 case 0x0f9c:
6674 case 0x0f9d:
6675 case 0x0f9e:
6676 case 0x0f9f:
6678 ir.ot = OT_BYTE;
6679 if (i386_record_modrm (&ir))
6680 return -1;
6681 if (ir.mod == 3)
6683 : (ir.rm & 0x3));
6684 else
6685 {
6686 if (i386_record_lea_modrm (&ir))
6687 return -1;
6688 }
6689 break;
6690
6691 case 0x0f40: /* cmov Gv, Ev */
6692 case 0x0f41:
6693 case 0x0f42:
6694 case 0x0f43:
6695 case 0x0f44:
6696 case 0x0f45:
6697 case 0x0f46:
6698 case 0x0f47:
6699 case 0x0f48:
6700 case 0x0f49:
6701 case 0x0f4a:
6702 case 0x0f4b:
6703 case 0x0f4c:
6704 case 0x0f4d:
6705 case 0x0f4e:
6706 case 0x0f4f:
6707 if (i386_record_modrm (&ir))
6708 return -1;
6709 ir.reg |= rex_r;
6710 if (ir.dflag == OT_BYTE)
6711 ir.reg &= 0x3;
6713 break;
6714
6715 /* flags */
6716 case 0x9c: /* pushf */
6718 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6719 ir.dflag = 2;
6720 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6721 return -1;
6722 break;
6723
6724 case 0x9d: /* popf */
6727 break;
6728
6729 case 0x9e: /* sahf */
6731 {
6732 ir.addr -= 1;
6733 goto no_support;
6734 }
6735 /* FALLTHROUGH */
6736 case 0xf5: /* cmc */
6737 case 0xf8: /* clc */
6738 case 0xf9: /* stc */
6739 case 0xfc: /* cld */
6740 case 0xfd: /* std */
6742 break;
6743
6744 case 0x9f: /* lahf */
6746 {
6747 ir.addr -= 1;
6748 goto no_support;
6749 }
6752 break;
6753
6754 /* bit operations */
6755 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6756 ir.ot = ir.dflag + OT_WORD;
6757 if (i386_record_modrm (&ir))
6758 return -1;
6759 if (ir.reg < 4)
6760 {
6761 ir.addr -= 2;
6762 opcode = opcode << 8 | ir.modrm;
6763 goto no_support;
6764 }
6765 if (ir.reg != 4)
6766 {
6767 if (ir.mod == 3)
6769 else
6770 {
6771 if (i386_record_lea_modrm (&ir))
6772 return -1;
6773 }
6774 }
6776 break;
6777
6778 case 0x0fa3: /* bt Gv, Ev */
6780 break;
6781
6782 case 0x0fab: /* bts */
6783 case 0x0fb3: /* btr */
6784 case 0x0fbb: /* btc */
6785 ir.ot = ir.dflag + OT_WORD;
6786 if (i386_record_modrm (&ir))
6787 return -1;
6788 if (ir.mod == 3)
6790 else
6791 {
6792 uint64_t addr64;
6793 if (i386_record_lea_modrm_addr (&ir, &addr64))
6794 return -1;
6796 ir.regmap[ir.reg | rex_r],
6797 &addr);
6798 switch (ir.dflag)
6799 {
6800 case 0:
6801 addr64 += ((int16_t) addr >> 4) << 4;
6802 break;
6803 case 1:
6804 addr64 += ((int32_t) addr >> 5) << 5;
6805 break;
6806 case 2:
6807 addr64 += ((int64_t) addr >> 6) << 6;
6808 break;
6809 }
6810 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6811 return -1;
6812 if (i386_record_lea_modrm (&ir))
6813 return -1;
6814 }
6816 break;
6817
6818 case 0x0fbc: /* bsf */
6819 case 0x0fbd: /* bsr */
6822 break;
6823
6824 /* bcd */
6825 case 0x27: /* daa */
6826 case 0x2f: /* das */
6827 case 0x37: /* aaa */
6828 case 0x3f: /* aas */
6829 case 0xd4: /* aam */
6830 case 0xd5: /* aad */
6832 {
6833 ir.addr -= 1;
6834 goto no_support;
6835 }
6838 break;
6839
6840 /* misc */
6841 case 0x90: /* nop */
6842 if (prefixes & PREFIX_LOCK)
6843 {
6844 ir.addr -= 1;
6845 goto no_support;
6846 }
6847 break;
6848
6849 case 0x9b: /* fwait */
6850 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6851 return -1;
6852 opcode = (uint32_t) opcode8;
6853 ir.addr++;
6854 goto reswitch;
6855 break;
6856
6857 /* XXX */
6858 case 0xcc: /* int3 */
6860 _("Process record does not support instruction "
6861 "int3.\n"));
6862 ir.addr -= 1;
6863 goto no_support;
6864 break;
6865
6866 /* XXX */
6867 case 0xcd: /* int */
6868 {
6869 int ret;
6870 uint8_t interrupt;
6871 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6872 return -1;
6873 ir.addr++;
6874 if (interrupt != 0x80
6875 || tdep->i386_intx80_record == NULL)
6876 {
6878 _("Process record does not support "
6879 "instruction int 0x%02x.\n"),
6880 interrupt);
6881 ir.addr -= 2;
6882 goto no_support;
6883 }
6884 ret = tdep->i386_intx80_record (ir.regcache);
6885 if (ret)
6886 return ret;
6887 }
6888 break;
6889
6890 /* XXX */
6891 case 0xce: /* into */
6893 _("Process record does not support "
6894 "instruction into.\n"));
6895 ir.addr -= 1;
6896 goto no_support;
6897 break;
6898
6899 case 0xfa: /* cli */
6900 case 0xfb: /* sti */
6901 break;
6902
6903 case 0x62: /* bound */
6905 _("Process record does not support "
6906 "instruction bound.\n"));
6907 ir.addr -= 1;
6908 goto no_support;
6909 break;
6910
6911 case 0x0fc8: /* bswap reg */
6912 case 0x0fc9:
6913 case 0x0fca:
6914 case 0x0fcb:
6915 case 0x0fcc:
6916 case 0x0fcd:
6917 case 0x0fce:
6918 case 0x0fcf:
6919 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6920 break;
6921
6922 case 0xd6: /* salc */
6924 {
6925 ir.addr -= 1;
6926 goto no_support;
6927 }
6930 break;
6931
6932 case 0xe0: /* loopnz */
6933 case 0xe1: /* loopz */
6934 case 0xe2: /* loop */
6935 case 0xe3: /* jecxz */
6938 break;
6939
6940 case 0x0f30: /* wrmsr */
6942 _("Process record does not support "
6943 "instruction wrmsr.\n"));
6944 ir.addr -= 2;
6945 goto no_support;
6946 break;
6947
6948 case 0x0f32: /* rdmsr */
6950 _("Process record does not support "
6951 "instruction rdmsr.\n"));
6952 ir.addr -= 2;
6953 goto no_support;
6954 break;
6955
6956 case 0x0f31: /* rdtsc */
6959 break;
6960
6961 case 0x0f34: /* sysenter */
6962 {
6963 int ret;
6965 {
6966 ir.addr -= 2;
6967 goto no_support;
6968 }
6969 if (tdep->i386_sysenter_record == NULL)
6970 {
6972 _("Process record does not support "
6973 "instruction sysenter.\n"));
6974 ir.addr -= 2;
6975 goto no_support;
6976 }
6977 ret = tdep->i386_sysenter_record (ir.regcache);
6978 if (ret)
6979 return ret;
6980 }
6981 break;
6982
6983 case 0x0f35: /* sysexit */
6985 _("Process record does not support "
6986 "instruction sysexit.\n"));
6987 ir.addr -= 2;
6988 goto no_support;
6989 break;
6990
6991 case 0x0f05: /* syscall */
6992 {
6993 int ret;
6994 if (tdep->i386_syscall_record == NULL)
6995 {
6997 _("Process record does not support "
6998 "instruction syscall.\n"));
6999 ir.addr -= 2;
7000 goto no_support;
7001 }
7002 ret = tdep->i386_syscall_record (ir.regcache);
7003 if (ret)
7004 return ret;
7005 }
7006 break;
7007
7008 case 0x0f07: /* sysret */
7010 _("Process record does not support "
7011 "instruction sysret.\n"));
7012 ir.addr -= 2;
7013 goto no_support;
7014 break;
7015
7016 case 0x0fa2: /* cpuid */
7021 break;
7022
7023 case 0xf4: /* hlt */
7025 _("Process record does not support "
7026 "instruction hlt.\n"));
7027 ir.addr -= 1;
7028 goto no_support;
7029 break;
7030
7031 case 0x0f00:
7032 if (i386_record_modrm (&ir))
7033 return -1;
7034 switch (ir.reg)
7035 {
7036 case 0: /* sldt */
7037 case 1: /* str */
7038 if (ir.mod == 3)
7040 else
7041 {
7042 ir.ot = OT_WORD;
7043 if (i386_record_lea_modrm (&ir))
7044 return -1;
7045 }
7046 break;
7047 case 2: /* lldt */
7048 case 3: /* ltr */
7049 break;
7050 case 4: /* verr */
7051 case 5: /* verw */
7053 break;
7054 default:
7055 ir.addr -= 3;
7056 opcode = opcode << 8 | ir.modrm;
7057 goto no_support;
7058 break;
7059 }
7060 break;
7061
7062 case 0x0f01:
7063 if (i386_record_modrm (&ir))
7064 return -1;
7065 switch (ir.reg)
7066 {
7067 case 0: /* sgdt */
7068 {
7069 uint64_t addr64;
7070
7071 if (ir.mod == 3)
7072 {
7073 ir.addr -= 3;
7074 opcode = opcode << 8 | ir.modrm;
7075 goto no_support;
7076 }
7077 if (ir.override >= 0)
7078 {
7080 {
7081 if (yquery (_("\
7082Process record ignores the memory change of instruction at address %s\n\
7083because it can't get the value of the segment register.\n\
7084Do you want to stop the program?"),
7085 paddress (gdbarch, ir.orig_addr)))
7086 return -1;
7087 }
7088 }
7089 else
7090 {
7091 if (i386_record_lea_modrm_addr (&ir, &addr64))
7092 return -1;
7093 if (record_full_arch_list_add_mem (addr64, 2))
7094 return -1;
7095 addr64 += 2;
7097 {
7098 if (record_full_arch_list_add_mem (addr64, 8))
7099 return -1;
7100 }
7101 else
7102 {
7103 if (record_full_arch_list_add_mem (addr64, 4))
7104 return -1;
7105 }
7106 }
7107 }
7108 break;
7109 case 1:
7110 if (ir.mod == 3)
7111 {
7112 switch (ir.rm)
7113 {
7114 case 0: /* monitor */
7115 break;
7116 case 1: /* mwait */
7118 break;
7119 default:
7120 ir.addr -= 3;
7121 opcode = opcode << 8 | ir.modrm;
7122 goto no_support;
7123 break;
7124 }
7125 }
7126 else
7127 {
7128 /* sidt */
7129 if (ir.override >= 0)
7130 {
7132 {
7133 if (yquery (_("\
7134Process record ignores the memory change of instruction at address %s\n\
7135because it can't get the value of the segment register.\n\
7136Do you want to stop the program?"),
7137 paddress (gdbarch, ir.orig_addr)))
7138 return -1;
7139 }
7140 }
7141 else
7142 {
7143 uint64_t addr64;
7144
7145 if (i386_record_lea_modrm_addr (&ir, &addr64))
7146 return -1;
7147 if (record_full_arch_list_add_mem (addr64, 2))
7148 return -1;
7149 addr64 += 2;
7151 {
7152 if (record_full_arch_list_add_mem (addr64, 8))
7153 return -1;
7154 }
7155 else
7156 {
7157 if (record_full_arch_list_add_mem (addr64, 4))
7158 return -1;
7159 }
7160 }
7161 }
7162 break;
7163 case 2: /* lgdt */
7164 if (ir.mod == 3)
7165 {
7166 /* xgetbv */
7167 if (ir.rm == 0)
7168 {
7171 break;
7172 }
7173 /* xsetbv */
7174 else if (ir.rm == 1)
7175 break;
7176 }
7177 /* Fall through. */
7178 case 3: /* lidt */
7179 if (ir.mod == 3)
7180 {
7181 ir.addr -= 3;
7182 opcode = opcode << 8 | ir.modrm;
7183 goto no_support;
7184 }
7185 break;
7186 case 4: /* smsw */
7187 if (ir.mod == 3)
7188 {
7190 return -1;
7191 }
7192 else
7193 {
7194 ir.ot = OT_WORD;
7195 if (i386_record_lea_modrm (&ir))
7196 return -1;
7197 }
7199 break;
7200 case 6: /* lmsw */
7202 break;
7203 case 7: /* invlpg */
7204 if (ir.mod == 3)
7205 {
7206 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7208 else
7209 {
7210 ir.addr -= 3;
7211 opcode = opcode << 8 | ir.modrm;
7212 goto no_support;
7213 }
7214 }
7215 else
7217 break;
7218 default:
7219 ir.addr -= 3;
7220 opcode = opcode << 8 | ir.modrm;
7221 goto no_support;
7222 break;
7223 }
7224 break;
7225
7226 case 0x0f08: /* invd */
7227 case 0x0f09: /* wbinvd */
7228 break;
7229
7230 case 0x63: /* arpl */
7231 if (i386_record_modrm (&ir))
7232 return -1;
7233 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7234 {
7236 ? (ir.reg | rex_r) : ir.rm);
7237 }
7238 else
7239 {
7240 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7241 if (i386_record_lea_modrm (&ir))
7242 return -1;
7243 }
7246 break;
7247
7248 case 0x0f02: /* lar */
7249 case 0x0f03: /* lsl */
7250 if (i386_record_modrm (&ir))
7251 return -1;
7254 break;
7255
7256 case 0x0f18:
7257 if (i386_record_modrm (&ir))
7258 return -1;
7259 if (ir.mod == 3 && ir.reg == 3)
7260 {
7261 ir.addr -= 3;
7262 opcode = opcode << 8 | ir.modrm;
7263 goto no_support;
7264 }
7265 break;
7266
7267 case 0x0f19:
7268 case 0x0f1a:
7269 case 0x0f1b:
7270 case 0x0f1c:
7271 case 0x0f1d:
7272 case 0x0f1e:
7273 case 0x0f1f:
7274 /* nop (multi byte) */
7275 break;
7276
7277 case 0x0f20: /* mov reg, crN */
7278 case 0x0f22: /* mov crN, reg */
7279 if (i386_record_modrm (&ir))
7280 return -1;
7281 if ((ir.modrm & 0xc0) != 0xc0)
7282 {
7283 ir.addr -= 3;
7284 opcode = opcode << 8 | ir.modrm;
7285 goto no_support;
7286 }
7287 switch (ir.reg)
7288 {
7289 case 0:
7290 case 2:
7291 case 3:
7292 case 4:
7293 case 8:
7294 if (opcode & 2)
7296 else
7298 break;
7299 default:
7300 ir.addr -= 3;
7301 opcode = opcode << 8 | ir.modrm;
7302 goto no_support;
7303 break;
7304 }
7305 break;
7306
7307 case 0x0f21: /* mov reg, drN */
7308 case 0x0f23: /* mov drN, reg */
7309 if (i386_record_modrm (&ir))
7310 return -1;
7311 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7312 || ir.reg == 5 || ir.reg >= 8)
7313 {
7314 ir.addr -= 3;
7315 opcode = opcode << 8 | ir.modrm;
7316 goto no_support;
7317 }
7318 if (opcode & 2)
7320 else
7322 break;
7323
7324 case 0x0f06: /* clts */
7326 break;
7327
7328 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7329
7330 case 0x0f0d: /* 3DNow! prefetch */
7331 break;
7332
7333 case 0x0f0e: /* 3DNow! femms */
7334 case 0x0f77: /* emms */
7336 goto no_support;
7338 break;
7339
7340 case 0x0f0f: /* 3DNow! data */
7341 if (i386_record_modrm (&ir))
7342 return -1;
7343 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7344 return -1;
7345 ir.addr++;
7346 switch (opcode8)
7347 {
7348 case 0x0c: /* 3DNow! pi2fw */
7349 case 0x0d: /* 3DNow! pi2fd */
7350 case 0x1c: /* 3DNow! pf2iw */
7351 case 0x1d: /* 3DNow! pf2id */
7352 case 0x8a: /* 3DNow! pfnacc */
7353 case 0x8e: /* 3DNow! pfpnacc */
7354 case 0x90: /* 3DNow! pfcmpge */
7355 case 0x94: /* 3DNow! pfmin */
7356 case 0x96: /* 3DNow! pfrcp */
7357 case 0x97: /* 3DNow! pfrsqrt */
7358 case 0x9a: /* 3DNow! pfsub */
7359 case 0x9e: /* 3DNow! pfadd */
7360 case 0xa0: /* 3DNow! pfcmpgt */
7361 case 0xa4: /* 3DNow! pfmax */
7362 case 0xa6: /* 3DNow! pfrcpit1 */
7363 case 0xa7: /* 3DNow! pfrsqit1 */
7364 case 0xaa: /* 3DNow! pfsubr */
7365 case 0xae: /* 3DNow! pfacc */
7366 case 0xb0: /* 3DNow! pfcmpeq */
7367 case 0xb4: /* 3DNow! pfmul */
7368 case 0xb6: /* 3DNow! pfrcpit2 */
7369 case 0xb7: /* 3DNow! pmulhrw */
7370 case 0xbb: /* 3DNow! pswapd */
7371 case 0xbf: /* 3DNow! pavgusb */
7372 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7373 goto no_support_3dnow_data;
7375 break;
7376
7377 default:
7378no_support_3dnow_data:
7379 opcode = (opcode << 8) | opcode8;
7380 goto no_support;
7381 break;
7382 }
7383 break;
7384
7385 case 0x0faa: /* rsm */
7395 break;
7396
7397 case 0x0fae:
7398 if (i386_record_modrm (&ir))
7399 return -1;
7400 switch(ir.reg)
7401 {
7402 case 0: /* fxsave */
7403 {
7404 uint64_t tmpu64;
7405
7407 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7408 return -1;
7409 if (record_full_arch_list_add_mem (tmpu64, 512))
7410 return -1;
7411 }
7412 break;
7413
7414 case 1: /* fxrstor */
7415 {
7416 int i;
7417
7419
7420 for (i = I387_MM0_REGNUM (tdep);
7421 i386_mmx_regnum_p (gdbarch, i); i++)
7423
7424 for (i = I387_XMM0_REGNUM (tdep);
7425 i386_xmm_regnum_p (gdbarch, i); i++)
7427
7430 I387_MXCSR_REGNUM(tdep));
7431
7432 for (i = I387_ST0_REGNUM (tdep);
7433 i386_fp_regnum_p (gdbarch, i); i++)
7435
7436 for (i = I387_FCTRL_REGNUM (tdep);
7437 i386_fpc_regnum_p (gdbarch, i); i++)
7439 }
7440 break;
7441
7442 case 2: /* ldmxcsr */
7444 goto no_support;
7446 break;
7447
7448 case 3: /* stmxcsr */
7449 ir.ot = OT_LONG;
7450 if (i386_record_lea_modrm (&ir))
7451 return -1;
7452 break;
7453
7454 case 5: /* lfence */
7455 case 6: /* mfence */
7456 case 7: /* sfence clflush */
7457 break;
7458
7459 default:
7460 opcode = (opcode << 8) | ir.modrm;
7461 goto no_support;
7462 break;
7463 }
7464 break;
7465
7466 case 0x0fc3: /* movnti */
7467 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7468 if (i386_record_modrm (&ir))
7469 return -1;
7470 if (ir.mod == 3)
7471 goto no_support;
7472 ir.reg |= rex_r;
7473 if (i386_record_lea_modrm (&ir))
7474 return -1;
7475 break;
7476
7477 /* Add prefix to opcode. */
7478 case 0x0f10:
7479 case 0x0f11:
7480 case 0x0f12:
7481 case 0x0f13:
7482 case 0x0f14:
7483 case 0x0f15:
7484 case 0x0f16:
7485 case 0x0f17:
7486 case 0x0f28:
7487 case 0x0f29:
7488 case 0x0f2a:
7489 case 0x0f2b:
7490 case 0x0f2c:
7491 case 0x0f2d:
7492 case 0x0f2e:
7493 case 0x0f2f:
7494 case 0x0f38:
7495 case 0x0f39:
7496 case 0x0f3a:
7497 case 0x0f50:
7498 case 0x0f51:
7499 case 0x0f52:
7500 case 0x0f53:
7501 case 0x0f54:
7502 case 0x0f55:
7503 case 0x0f56:
7504 case 0x0f57:
7505 case 0x0f58:
7506 case 0x0f59:
7507 case 0x0f5a:
7508 case 0x0f5b:
7509 case 0x0f5c:
7510 case 0x0f5d:
7511 case 0x0f5e:
7512 case 0x0f5f:
7513 case 0x0f60:
7514 case 0x0f61:
7515 case 0x0f62:
7516 case 0x0f63:
7517 case 0x0f64:
7518 case 0x0f65:
7519 case 0x0f66:
7520 case 0x0f67:
7521 case 0x0f68:
7522 case 0x0f69:
7523 case 0x0f6a:
7524 case 0x0f6b:
7525 case 0x0f6c:
7526 case 0x0f6d:
7527 case 0x0f6e:
7528 case 0x0f6f:
7529 case 0x0f70:
7530 case 0x0f71:
7531 case 0x0f72:
7532 case 0x0f73:
7533 case 0x0f74:
7534 case 0x0f75:
7535 case 0x0f76:
7536 case 0x0f7c:
7537 case 0x0f7d:
7538 case 0x0f7e:
7539 case 0x0f7f:
7540 case 0x0fb8:
7541 case 0x0fc2:
7542 case 0x0fc4:
7543 case 0x0fc5:
7544 case 0x0fc6:
7545 case 0x0fd0:
7546 case 0x0fd1:
7547 case 0x0fd2:
7548 case 0x0fd3:
7549 case 0x0fd4:
7550 case 0x0fd5:
7551 case 0x0fd6:
7552 case 0x0fd7:
7553 case 0x0fd8:
7554 case 0x0fd9:
7555 case 0x0fda:
7556 case 0x0fdb:
7557 case 0x0fdc:
7558 case 0x0fdd:
7559 case 0x0fde:
7560 case 0x0fdf:
7561 case 0x0fe0:
7562 case 0x0fe1:
7563 case 0x0fe2:
7564 case 0x0fe3:
7565 case 0x0fe4:
7566 case 0x0fe5:
7567 case 0x0fe6:
7568 case 0x0fe7:
7569 case 0x0fe8:
7570 case 0x0fe9:
7571 case 0x0fea:
7572 case 0x0feb:
7573 case 0x0fec:
7574 case 0x0fed:
7575 case 0x0fee:
7576 case 0x0fef:
7577 case 0x0ff0:
7578 case 0x0ff1:
7579 case 0x0ff2:
7580 case 0x0ff3:
7581 case 0x0ff4:
7582 case 0x0ff5:
7583 case 0x0ff6:
7584 case 0x0ff7:
7585 case 0x0ff8:
7586 case 0x0ff9:
7587 case 0x0ffa:
7588 case 0x0ffb:
7589 case 0x0ffc:
7590 case 0x0ffd:
7591 case 0x0ffe:
7592 /* Mask out PREFIX_ADDR. */
7593 switch ((prefixes & ~PREFIX_ADDR))
7594 {
7595 case PREFIX_REPNZ:
7596 opcode |= 0xf20000;
7597 break;
7598 case PREFIX_DATA:
7599 opcode |= 0x660000;
7600 break;
7601 case PREFIX_REPZ:
7602 opcode |= 0xf30000;
7603 break;
7604 }
7605reswitch_prefix_add:
7606 switch (opcode)
7607 {
7608 case 0x0f38:
7609 case 0x660f38:
7610 case 0xf20f38:
7611 case 0x0f3a:
7612 case 0x660f3a:
7613 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7614 return -1;
7615 ir.addr++;
7616 opcode = (uint32_t) opcode8 | opcode << 8;
7617 goto reswitch_prefix_add;
7618 break;
7619
7620 case 0x0f10: /* movups */
7621 case 0x660f10: /* movupd */
7622 case 0xf30f10: /* movss */
7623 case 0xf20f10: /* movsd */
7624 case 0x0f12: /* movlps */
7625 case 0x660f12: /* movlpd */
7626 case 0xf30f12: /* movsldup */
7627 case 0xf20f12: /* movddup */
7628 case 0x0f14: /* unpcklps */
7629 case 0x660f14: /* unpcklpd */
7630 case 0x0f15: /* unpckhps */
7631 case 0x660f15: /* unpckhpd */
7632 case 0x0f16: /* movhps */
7633 case 0x660f16: /* movhpd */
7634 case 0xf30f16: /* movshdup */
7635 case 0x0f28: /* movaps */
7636 case 0x660f28: /* movapd */
7637 case 0x0f2a: /* cvtpi2ps */
7638 case 0x660f2a: /* cvtpi2pd */
7639 case 0xf30f2a: /* cvtsi2ss */
7640 case 0xf20f2a: /* cvtsi2sd */
7641 case 0x0f2c: /* cvttps2pi */
7642 case 0x660f2c: /* cvttpd2pi */
7643 case 0x0f2d: /* cvtps2pi */
7644 case 0x660f2d: /* cvtpd2pi */
7645 case 0x660f3800: /* pshufb */
7646 case 0x660f3801: /* phaddw */
7647 case 0x660f3802: /* phaddd */
7648 case 0x660f3803: /* phaddsw */
7649 case 0x660f3804: /* pmaddubsw */
7650 case 0x660f3805: /* phsubw */
7651 case 0x660f3806: /* phsubd */
7652 case 0x660f3807: /* phsubsw */
7653 case 0x660f3808: /* psignb */
7654 case 0x660f3809: /* psignw */
7655 case 0x660f380a: /* psignd */
7656 case 0x660f380b: /* pmulhrsw */
7657 case 0x660f3810: /* pblendvb */
7658 case 0x660f3814: /* blendvps */
7659 case 0x660f3815: /* blendvpd */
7660 case 0x660f381c: /* pabsb */
7661 case 0x660f381d: /* pabsw */
7662 case 0x660f381e: /* pabsd */
7663 case 0x660f3820: /* pmovsxbw */
7664 case 0x660f3821: /* pmovsxbd */
7665 case 0x660f3822: /* pmovsxbq */
7666 case 0x660f3823: /* pmovsxwd */
7667 case 0x660f3824: /* pmovsxwq */
7668 case 0x660f3825: /* pmovsxdq */
7669 case 0x660f3828: /* pmuldq */
7670 case 0x660f3829: /* pcmpeqq */
7671 case 0x660f382a: /* movntdqa */
7672 case 0x660f3a08: /* roundps */
7673 case 0x660f3a09: /* roundpd */
7674 case 0x660f3a0a: /* roundss */
7675 case 0x660f3a0b: /* roundsd */
7676 case 0x660f3a0c: /* blendps */
7677 case 0x660f3a0d: /* blendpd */
7678 case 0x660f3a0e: /* pblendw */
7679 case 0x660f3a0f: /* palignr */
7680 case 0x660f3a20: /* pinsrb */
7681 case 0x660f3a21: /* insertps */
7682 case 0x660f3a22: /* pinsrd pinsrq */
7683 case 0x660f3a40: /* dpps */
7684 case 0x660f3a41: /* dppd */
7685 case 0x660f3a42: /* mpsadbw */
7686 case 0x660f3a60: /* pcmpestrm */
7687 case 0x660f3a61: /* pcmpestri */
7688 case 0x660f3a62: /* pcmpistrm */
7689 case 0x660f3a63: /* pcmpistri */
7690 case 0x0f51: /* sqrtps */
7691 case 0x660f51: /* sqrtpd */
7692 case 0xf20f51: /* sqrtsd */
7693 case 0xf30f51: /* sqrtss */
7694 case 0x0f52: /* rsqrtps */
7695 case 0xf30f52: /* rsqrtss */
7696 case 0x0f53: /* rcpps */
7697 case 0xf30f53: /* rcpss */
7698 case 0x0f54: /* andps */
7699 case 0x660f54: /* andpd */
7700 case 0x0f55: /* andnps */
7701 case 0x660f55: /* andnpd */
7702 case 0x0f56: /* orps */
7703 case 0x660f56: /* orpd */
7704 case 0x0f57: /* xorps */
7705 case 0x660f57: /* xorpd */
7706 case 0x0f58: /* addps */
7707 case 0x660f58: /* addpd */
7708 case 0xf20f58: /* addsd */
7709 case 0xf30f58: /* addss */
7710 case 0x0f59: /* mulps */
7711 case 0x660f59: /* mulpd */
7712 case 0xf20f59: /* mulsd */
7713 case 0xf30f59: /* mulss */
7714 case 0x0f5a: /* cvtps2pd */
7715 case 0x660f5a: /* cvtpd2ps */
7716 case 0xf20f5a: /* cvtsd2ss */
7717 case 0xf30f5a: /* cvtss2sd */
7718 case 0x0f5b: /* cvtdq2ps */
7719 case 0x660f5b: /* cvtps2dq */
7720 case 0xf30f5b: /* cvttps2dq */
7721 case 0x0f5c: /* subps */
7722 case 0x660f5c: /* subpd */
7723 case 0xf20f5c: /* subsd */
7724 case 0xf30f5c: /* subss */
7725 case 0x0f5d: /* minps */
7726 case 0x660f5d: /* minpd */
7727 case 0xf20f5d: /* minsd */
7728 case 0xf30f5d: /* minss */
7729 case 0x0f5e: /* divps */
7730 case 0x660f5e: /* divpd */
7731 case 0xf20f5e: /* divsd */
7732 case 0xf30f5e: /* divss */
7733 case 0x0f5f: /* maxps */
7734 case 0x660f5f: /* maxpd */
7735 case 0xf20f5f: /* maxsd */
7736 case 0xf30f5f: /* maxss */
7737 case 0x660f60: /* punpcklbw */
7738 case 0x660f61: /* punpcklwd */
7739 case 0x660f62: /* punpckldq */
7740 case 0x660f63: /* packsswb */
7741 case 0x660f64: /* pcmpgtb */
7742 case 0x660f65: /* pcmpgtw */
7743 case 0x660f66: /* pcmpgtd */
7744 case 0x660f67: /* packuswb */
7745 case 0x660f68: /* punpckhbw */
7746 case 0x660f69: /* punpckhwd */
7747 case 0x660f6a: /* punpckhdq */
7748 case 0x660f6b: /* packssdw */
7749 case 0x660f6c: /* punpcklqdq */
7750 case 0x660f6d: /* punpckhqdq */
7751 case 0x660f6e: /* movd */
7752 case 0x660f6f: /* movdqa */
7753 case 0xf30f6f: /* movdqu */
7754 case 0x660f70: /* pshufd */
7755 case 0xf20f70: /* pshuflw */
7756 case 0xf30f70: /* pshufhw */
7757 case 0x660f74: /* pcmpeqb */
7758 case 0x660f75: /* pcmpeqw */
7759 case 0x660f76: /* pcmpeqd */
7760 case 0x660f7c: /* haddpd */
7761 case 0xf20f7c: /* haddps */
7762 case 0x660f7d: /* hsubpd */
7763 case 0xf20f7d: /* hsubps */
7764 case 0xf30f7e: /* movq */
7765 case 0x0fc2: /* cmpps */
7766 case 0x660fc2: /* cmppd */
7767 case 0xf20fc2: /* cmpsd */
7768 case 0xf30fc2: /* cmpss */
7769 case 0x660fc4: /* pinsrw */
7770 case 0x0fc6: /* shufps */
7771 case 0x660fc6: /* shufpd */
7772 case 0x660fd0: /* addsubpd */
7773 case 0xf20fd0: /* addsubps */
7774 case 0x660fd1: /* psrlw */
7775 case 0x660fd2: /* psrld */
7776 case 0x660fd3: /* psrlq */
7777 case 0x660fd4: /* paddq */
7778 case 0x660fd5: /* pmullw */
7779 case 0xf30fd6: /* movq2dq */
7780 case 0x660fd8: /* psubusb */
7781 case 0x660fd9: /* psubusw */
7782 case 0x660fda: /* pminub */
7783 case 0x660fdb: /* pand */
7784 case 0x660fdc: /* paddusb */
7785 case 0x660fdd: /* paddusw */
7786 case 0x660fde: /* pmaxub */
7787 case 0x660fdf: /* pandn */
7788 case 0x660fe0: /* pavgb */
7789 case 0x660fe1: /* psraw */
7790 case 0x660fe2: /* psrad */
7791 case 0x660fe3: /* pavgw */
7792 case 0x660fe4: /* pmulhuw */
7793 case 0x660fe5: /* pmulhw */
7794 case 0x660fe6: /* cvttpd2dq */
7795 case 0xf20fe6: /* cvtpd2dq */
7796 case 0xf30fe6: /* cvtdq2pd */
7797 case 0x660fe8: /* psubsb */
7798 case 0x660fe9: /* psubsw */
7799 case 0x660fea: /* pminsw */
7800 case 0x660feb: /* por */
7801 case 0x660fec: /* paddsb */
7802 case 0x660fed: /* paddsw */
7803 case 0x660fee: /* pmaxsw */
7804 case 0x660fef: /* pxor */
7805 case 0xf20ff0: /* lddqu */
7806 case 0x660ff1: /* psllw */
7807 case 0x660ff2: /* pslld */
7808 case 0x660ff3: /* psllq */
7809 case 0x660ff4: /* pmuludq */
7810 case 0x660ff5: /* pmaddwd */
7811 case 0x660ff6: /* psadbw */
7812 case 0x660ff8: /* psubb */
7813 case 0x660ff9: /* psubw */
7814 case 0x660ffa: /* psubd */
7815 case 0x660ffb: /* psubq */
7816 case 0x660ffc: /* paddb */
7817 case 0x660ffd: /* paddw */
7818 case 0x660ffe: /* paddd */
7819 if (i386_record_modrm (&ir))
7820 return -1;
7821 ir.reg |= rex_r;
7822 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7823 goto no_support;
7825 I387_XMM0_REGNUM (tdep) + ir.reg);
7826 if ((opcode & 0xfffffffc) == 0x660f3a60)
7828 break;
7829
7830 case 0x0f11: /* movups */
7831 case 0x660f11: /* movupd */
7832 case 0xf30f11: /* movss */
7833 case 0xf20f11: /* movsd */
7834 case 0x0f13: /* movlps */
7835 case 0x660f13: /* movlpd */
7836 case 0x0f17: /* movhps */
7837 case 0x660f17: /* movhpd */
7838 case 0x0f29: /* movaps */
7839 case 0x660f29: /* movapd */
7840 case 0x660f3a14: /* pextrb */
7841 case 0x660f3a15: /* pextrw */
7842 case 0x660f3a16: /* pextrd pextrq */
7843 case 0x660f3a17: /* extractps */
7844 case 0x660f7f: /* movdqa */
7845 case 0xf30f7f: /* movdqu */
7846 if (i386_record_modrm (&ir))
7847 return -1;
7848 if (ir.mod == 3)
7849 {
7850 if (opcode == 0x0f13 || opcode == 0x660f13
7851 || opcode == 0x0f17 || opcode == 0x660f17)
7852 goto no_support;
7853 ir.rm |= ir.rex_b;
7855 I387_XMM0_REGNUM (tdep) + ir.rm))
7856 goto no_support;
7858 I387_XMM0_REGNUM (tdep) + ir.rm);
7859 }
7860 else
7861 {
7862 switch (opcode)
7863 {
7864 case 0x660f3a14:
7865 ir.ot = OT_BYTE;
7866 break;
7867 case 0x660f3a15:
7868 ir.ot = OT_WORD;
7869 break;
7870 case 0x660f3a16:
7871 ir.ot = OT_LONG;
7872 break;
7873 case 0x660f3a17:
7874 ir.ot = OT_QUAD;
7875 break;
7876 default:
7877 ir.ot = OT_DQUAD;
7878 break;
7879 }
7880 if (i386_record_lea_modrm (&ir))
7881 return -1;
7882 }
7883 break;
7884
7885 case 0x0f2b: /* movntps */
7886 case 0x660f2b: /* movntpd */
7887 case 0x0fe7: /* movntq */
7888 case 0x660fe7: /* movntdq */
7889 if (ir.mod == 3)
7890 goto no_support;
7891 if (opcode == 0x0fe7)
7892 ir.ot = OT_QUAD;
7893 else
7894 ir.ot = OT_DQUAD;
7895 if (i386_record_lea_modrm (&ir))
7896 return -1;
7897 break;
7898
7899 case 0xf30f2c: /* cvttss2si */
7900 case 0xf20f2c: /* cvttsd2si */
7901 case 0xf30f2d: /* cvtss2si */
7902 case 0xf20f2d: /* cvtsd2si */
7903 case 0xf20f38f0: /* crc32 */
7904 case 0xf20f38f1: /* crc32 */
7905 case 0x0f50: /* movmskps */
7906 case 0x660f50: /* movmskpd */
7907 case 0x0fc5: /* pextrw */
7908 case 0x660fc5: /* pextrw */
7909 case 0x0fd7: /* pmovmskb */
7910 case 0x660fd7: /* pmovmskb */
7912 break;
7913
7914 case 0x0f3800: /* pshufb */
7915 case 0x0f3801: /* phaddw */
7916 case 0x0f3802: /* phaddd */
7917 case 0x0f3803: /* phaddsw */
7918 case 0x0f3804: /* pmaddubsw */
7919 case 0x0f3805: /* phsubw */
7920 case 0x0f3806: /* phsubd */
7921 case 0x0f3807: /* phsubsw */
7922 case 0x0f3808: /* psignb */
7923 case 0x0f3809: /* psignw */
7924 case 0x0f380a: /* psignd */
7925 case 0x0f380b: /* pmulhrsw */
7926 case 0x0f381c: /* pabsb */
7927 case 0x0f381d: /* pabsw */
7928 case 0x0f381e: /* pabsd */
7929 case 0x0f382b: /* packusdw */
7930 case 0x0f3830: /* pmovzxbw */
7931 case 0x0f3831: /* pmovzxbd */
7932 case 0x0f3832: /* pmovzxbq */
7933 case 0x0f3833: /* pmovzxwd */
7934 case 0x0f3834: /* pmovzxwq */
7935 case 0x0f3835: /* pmovzxdq */
7936 case 0x0f3837: /* pcmpgtq */
7937 case 0x0f3838: /* pminsb */
7938 case 0x0f3839: /* pminsd */
7939 case 0x0f383a: /* pminuw */
7940 case 0x0f383b: /* pminud */
7941 case 0x0f383c: /* pmaxsb */
7942 case 0x0f383d: /* pmaxsd */
7943 case 0x0f383e: /* pmaxuw */
7944 case 0x0f383f: /* pmaxud */
7945 case 0x0f3840: /* pmulld */
7946 case 0x0f3841: /* phminposuw */
7947 case 0x0f3a0f: /* palignr */
7948 case 0x0f60: /* punpcklbw */
7949 case 0x0f61: /* punpcklwd */
7950 case 0x0f62: /* punpckldq */
7951 case 0x0f63: /* packsswb */
7952 case 0x0f64: /* pcmpgtb */
7953 case 0x0f65: /* pcmpgtw */
7954 case 0x0f66: /* pcmpgtd */
7955 case 0x0f67: /* packuswb */
7956 case 0x0f68: /* punpckhbw */
7957 case 0x0f69: /* punpckhwd */
7958 case 0x0f6a: /* punpckhdq */
7959 case 0x0f6b: /* packssdw */
7960 case 0x0f6e: /* movd */
7961 case 0x0f6f: /* movq */
7962 case 0x0f70: /* pshufw */
7963 case 0x0f74: /* pcmpeqb */
7964 case 0x0f75: /* pcmpeqw */
7965 case 0x0f76: /* pcmpeqd */
7966 case 0x0fc4: /* pinsrw */
7967 case 0x0fd1: /* psrlw */
7968 case 0x0fd2: /* psrld */
7969 case 0x0fd3: /* psrlq */
7970 case 0x0fd4: /* paddq */
7971 case 0x0fd5: /* pmullw */
7972 case 0xf20fd6: /* movdq2q */
7973 case 0x0fd8: /* psubusb */
7974 case 0x0fd9: /* psubusw */
7975 case 0x0fda: /* pminub */
7976 case 0x0fdb: /* pand */
7977 case 0x0fdc: /* paddusb */
7978 case 0x0fdd: /* paddusw */
7979 case 0x0fde: /* pmaxub */
7980 case 0x0fdf: /* pandn */
7981 case 0x0fe0: /* pavgb */
7982 case 0x0fe1: /* psraw */
7983 case 0x0fe2: /* psrad */
7984 case 0x0fe3: /* pavgw */
7985 case 0x0fe4: /* pmulhuw */
7986 case 0x0fe5: /* pmulhw */
7987 case 0x0fe8: /* psubsb */
7988 case 0x0fe9: /* psubsw */
7989 case 0x0fea: /* pminsw */
7990 case 0x0feb: /* por */
7991 case 0x0fec: /* paddsb */
7992 case 0x0fed: /* paddsw */
7993 case 0x0fee: /* pmaxsw */
7994 case 0x0fef: /* pxor */
7995 case 0x0ff1: /* psllw */
7996 case 0x0ff2: /* pslld */
7997 case 0x0ff3: /* psllq */
7998 case 0x0ff4: /* pmuludq */
7999 case 0x0ff5: /* pmaddwd */
8000 case 0x0ff6: /* psadbw */
8001 case 0x0ff8: /* psubb */
8002 case 0x0ff9: /* psubw */
8003 case 0x0ffa: /* psubd */
8004 case 0x0ffb: /* psubq */
8005 case 0x0ffc: /* paddb */
8006 case 0x0ffd: /* paddw */
8007 case 0x0ffe: /* paddd */
8008 if (i386_record_modrm (&ir))
8009 return -1;
8010 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
8011 goto no_support;
8013 I387_MM0_REGNUM (tdep) + ir.reg);
8014 break;
8015
8016 case 0x0f71: /* psllw */
8017 case 0x0f72: /* pslld */
8018 case 0x0f73: /* psllq */
8019 if (i386_record_modrm (&ir))
8020 return -1;
8021 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8022 goto no_support;
8024 I387_MM0_REGNUM (tdep) + ir.rm);
8025 break;
8026
8027 case 0x660f71: /* psllw */
8028 case 0x660f72: /* pslld */
8029 case 0x660f73: /* psllq */
8030 if (i386_record_modrm (&ir))
8031 return -1;
8032 ir.rm |= ir.rex_b;
8033 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
8034 goto no_support;
8036 I387_XMM0_REGNUM (tdep) + ir.rm);
8037 break;
8038
8039 case 0x0f7e: /* movd */
8040 case 0x660f7e: /* movd */
8041 if (i386_record_modrm (&ir))
8042 return -1;
8043 if (ir.mod == 3)
8045 else
8046 {
8047 if (ir.dflag == 2)
8048 ir.ot = OT_QUAD;
8049 else
8050 ir.ot = OT_LONG;
8051 if (i386_record_lea_modrm (&ir))
8052 return -1;
8053 }
8054 break;
8055
8056 case 0x0f7f: /* movq */
8057 if (i386_record_modrm (&ir))
8058 return -1;
8059 if (ir.mod == 3)
8060 {
8061 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8062 goto no_support;
8064 I387_MM0_REGNUM (tdep) + ir.rm);
8065 }
8066 else
8067 {
8068 ir.ot = OT_QUAD;
8069 if (i386_record_lea_modrm (&ir))
8070 return -1;
8071 }
8072 break;
8073
8074 case 0xf30fb8: /* popcnt */
8075 if (i386_record_modrm (&ir))
8076 return -1;
8079 break;
8080
8081 case 0x660fd6: /* movq */
8082 if (i386_record_modrm (&ir))
8083 return -1;
8084 if (ir.mod == 3)
8085 {
8086 ir.rm |= ir.rex_b;
8088 I387_XMM0_REGNUM (tdep) + ir.rm))
8089 goto no_support;
8091 I387_XMM0_REGNUM (tdep) + ir.rm);
8092 }
8093 else
8094 {
8095 ir.ot = OT_QUAD;
8096 if (i386_record_lea_modrm (&ir))
8097 return -1;
8098 }
8099 break;
8100
8101 case 0x660f3817: /* ptest */
8102 case 0x0f2e: /* ucomiss */
8103 case 0x660f2e: /* ucomisd */
8104 case 0x0f2f: /* comiss */
8105 case 0x660f2f: /* comisd */
8107 break;
8108
8109 case 0x0ff7: /* maskmovq */
8112 &addr);
8114 return -1;
8115 break;
8116
8117 case 0x660ff7: /* maskmovdqu */
8120 &addr);
8122 return -1;
8123 break;
8124
8125 default:
8126 goto no_support;
8127 break;
8128 }
8129 break;
8130
8131 default:
8132 goto no_support;
8133 break;
8134 }
8135
8136 /* In the future, maybe still need to deal with need_dasm. */
8139 return -1;
8140
8141 return 0;
8142
8143 no_support:
8145 _("Process record does not support instruction 0x%02x "
8146 "at address %s.\n"),
8147 (unsigned int) (opcode),
8148 paddress (gdbarch, ir.orig_addr));
8149 return -1;
8150}
8151
8152static const int i386_record_regmap[] =
8153{
8156 0, 0, 0, 0, 0, 0, 0, 0,
8159};
8160
8161/* Check that the given address appears suitable for a fast
8162 tracepoint, which on x86-64 means that we need an instruction of at
8163 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8164 jump and not have to worry about program jumps to an address in the
8165 middle of the tracepoint jump. On x86, it may be possible to use
8166 4-byte jumps with a 2-byte offset to a trampoline located in the
8167 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8168 of instruction to replace, and 0 if not, plus an explanatory
8169 string. */
8170
8171static int
8173 std::string *msg)
8174{
8175 int len, jumplen;
8176
8177 /* Ask the target for the minimum instruction length supported. */
8179
8180 if (jumplen < 0)
8181 {
8182 /* If the target does not support the get_min_fast_tracepoint_insn_len
8183 operation, assume that fast tracepoints will always be implemented
8184 using 4-byte relative jumps on both x86 and x86-64. */
8185 jumplen = 5;
8186 }
8187 else if (jumplen == 0)
8188 {
8189 /* If the target does support get_min_fast_tracepoint_insn_len but
8190 returns zero, then the IPA has not loaded yet. In this case,
8191 we optimistically assume that truncated 2-byte relative jumps
8192 will be available on x86, and compensate later if this assumption
8193 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8194 jumps will always be used. */
8195 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8196 }
8197
8198 /* Check for fit. */
8199 len = gdb_insn_length (gdbarch, addr);
8200
8201 if (len < jumplen)
8202 {
8203 /* Return a bit of target-specific detail to add to the caller's
8204 generic failure message. */
8205 if (msg)
8206 *msg = string_printf (_("; instruction is only %d bytes long, "
8207 "need at least %d bytes for the jump"),
8208 len, jumplen);
8209 return 0;
8210 }
8211 else
8212 {
8213 if (msg)
8214 msg->clear ();
8215 return 1;
8216 }
8217}
8218
8219/* Return a floating-point format for a floating-point variable of
8220 length LEN in bits. If non-NULL, NAME is the name of its type.
8221 If no suitable type is found, return NULL. */
8222
8223static const struct floatformat **
8225 const char *name, int len)
8226{
8227 if (len == 128 && name)
8228 if (strcmp (name, "__float128") == 0
8229 || strcmp (name, "_Float128") == 0
8230 || strcmp (name, "complex _Float128") == 0
8231 || strcmp (name, "complex(kind=16)") == 0
8232 || strcmp (name, "complex*32") == 0
8233 || strcmp (name, "COMPLEX*32") == 0
8234 || strcmp (name, "quad complex") == 0
8235 || strcmp (name, "real(kind=16)") == 0
8236 || strcmp (name, "real*16") == 0
8237 || strcmp (name, "REAL*16") == 0)
8239
8241}
8242
8243static int
8246{
8247 const struct target_desc *tdesc = tdep->tdesc;
8248 const struct tdesc_feature *feature_core;
8249
8250 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8251 *feature_avx512, *feature_pkeys, *feature_segments;
8252 int i, num_regs, valid_p;
8253
8254 if (! tdesc_has_registers (tdesc))
8255 return 0;
8256
8257 /* Get core registers. */
8258 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8259 if (feature_core == NULL)
8260 return 0;
8261
8262 /* Get SSE registers. */
8263 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8264
8265 /* Try AVX registers. */
8266 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8267
8268 /* Try MPX registers. */
8269 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8270
8271 /* Try AVX512 registers. */
8272 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8273
8274 /* Try segment base registers. */
8275 feature_segments = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments");
8276
8277 /* Try PKEYS */
8278 feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys");
8279
8280 valid_p = 1;
8281
8282 /* The XCR0 bits. */
8283 if (feature_avx512)
8284 {
8285 /* AVX512 register description requires AVX register description. */
8286 if (!feature_avx)
8287 return 0;
8288
8289 tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK;
8290
8291 /* It may have been set by OSABI initialization function. */
8292 if (tdep->k0_regnum < 0)
8293 {
8295 tdep->k0_regnum = I386_K0_REGNUM;
8296 }
8297
8298 for (i = 0; i < I387_NUM_K_REGS; i++)
8299 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8300 tdep->k0_regnum + i,
8301 i386_k_names[i]);
8302
8303 if (tdep->num_zmm_regs == 0)
8304 {
8306 tdep->num_zmm_regs = 8;
8308 }
8309
8310 for (i = 0; i < tdep->num_zmm_regs; i++)
8311 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8312 tdep->zmm0h_regnum + i,
8313 tdep->zmmh_register_names[i]);
8314
8315 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8316 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8317 tdep->xmm16_regnum + i,
8318 tdep->xmm_avx512_register_names[i]);
8319
8320 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8321 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8322 tdep->ymm16h_regnum + i,
8323 tdep->ymm16h_register_names[i]);
8324 }
8325 if (feature_avx)
8326 {
8327 /* AVX register description requires SSE register description. */
8328 if (!feature_sse)
8329 return 0;
8330
8331 if (!feature_avx512)
8332 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8333
8334 /* It may have been set by OSABI initialization function. */
8335 if (tdep->num_ymm_regs == 0)
8336 {
8338 tdep->num_ymm_regs = 8;
8340 }
8341
8342 for (i = 0; i < tdep->num_ymm_regs; i++)
8343 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8344 tdep->ymm0h_regnum + i,
8345 tdep->ymmh_register_names[i]);
8346 }
8347 else if (feature_sse)
8348 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8349 else
8350 {
8351 tdep->xcr0 = X86_XSTATE_X87_MASK;
8352 tdep->num_xmm_regs = 0;
8353 }
8354
8355 num_regs = tdep->num_core_regs;
8356 for (i = 0; i < num_regs; i++)
8357 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8358 tdep->register_names[i]);
8359
8360 if (feature_sse)
8361 {
8362 /* Need to include %mxcsr, so add one. */
8363 num_regs += tdep->num_xmm_regs + 1;
8364 for (; i < num_regs; i++)
8365 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8366 tdep->register_names[i]);
8367 }
8368
8369 if (feature_mpx)
8370 {
8371 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8372
8373 if (tdep->bnd0r_regnum < 0)
8374 {
8378 }
8379
8380 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8381 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8382 I387_BND0R_REGNUM (tdep) + i,
8383 tdep->mpx_register_names[i]);
8384 }
8385
8386 if (feature_segments)
8387 {
8388 if (tdep->fsbase_regnum < 0)
8390 valid_p &= tdesc_numbered_register (feature_segments, tdesc_data,
8391 tdep->fsbase_regnum, "fs_base");
8392 valid_p &= tdesc_numbered_register (feature_segments, tdesc_data,
8393 tdep->fsbase_regnum + 1, "gs_base");
8394 }
8395
8396 if (feature_pkeys)
8397 {
8398 tdep->xcr0 |= X86_XSTATE_PKRU;
8399 if (tdep->pkru_regnum < 0)
8400 {
8403 tdep->num_pkeys_regs = 1;
8404 }
8405
8406 for (i = 0; i < I387_NUM_PKEYS_REGS; i++)
8407 valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data,
8408 I387_PKRU_REGNUM (tdep) + i,
8409 tdep->pkeys_register_names[i]);
8410 }
8411
8412 return valid_p;
8413}
8414
8415
8416
8417/* Implement the type_align gdbarch function. */
8418
8419static ULONGEST
8421{
8423
8424 if (gdbarch_ptr_bit (gdbarch) == 32)
8425 {
8426 if ((type->code () == TYPE_CODE_INT
8427 || type->code () == TYPE_CODE_FLT)
8428 && type->length () > 4)
8429 return 4;
8430
8431 /* Handle x86's funny long double. */
8432 if (type->code () == TYPE_CODE_FLT
8434 return 4;
8435 }
8436
8437 return 0;
8438}
8439
8440
8441/* Note: This is called for both i386 and amd64. */
8442
8443static struct gdbarch *
8445{
8446 struct gdbarch *gdbarch;
8447 const struct target_desc *tdesc;
8448 int mm0_regnum;
8449 int ymm0_regnum;
8450 int bnd0_regnum;
8451 int num_bnd_cooked;
8452
8453 /* If there is already a candidate, use it. */
8455 if (arches != NULL)
8456 return arches->gdbarch;
8457
8458 /* Allocate space for the new architecture. Assume i386 for now. */
8460 gdbarch = gdbarch_alloc (&info, tdep);
8461
8462 /* General-purpose registers. */
8463 tdep->gregset_reg_offset = NULL;
8465 tdep->sizeof_gregset = 0;
8466
8467 /* Floating-point registers. */
8469 tdep->fpregset = &i386_fpregset;
8470
8471 /* The default settings include the FPU registers, the MMX registers
8472 and the SSE registers. This can be overridden for a specific ABI
8473 by adjusting the members `st0_regnum', `mm0_regnum' and
8474 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8475 will show up in the output of "info all-registers". */
8476
8478
8479 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8480 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8481
8482 tdep->jb_pc_offset = -1;
8483 tdep->struct_return = pcc_struct_return;
8484 tdep->sigtramp_start = 0;
8485 tdep->sigtramp_end = 0;
8487 tdep->sigcontext_addr = NULL;
8488 tdep->sc_reg_offset = NULL;
8489 tdep->sc_pc_offset = -1;
8490 tdep->sc_sp_offset = -1;
8491
8492 tdep->xsave_xcr0_offset = -1;
8493
8495
8497
8498 /* The format used for `long double' on almost all i386 targets is
8499 the i387 extended floating-point format. In fact, of all targets
8500 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8501 on having a `long double' that's not `long' at all. */
8503
8504 /* Although the i387 extended floating-point has only 80 significant
8505 bits, a `long double' actually takes up 96, probably to enforce
8506 alignment. */
8508
8509 /* Support of bfloat16 format. */
8511
8512 /* Support for floating-point data type variants. */
8514
8515 /* Register numbers of various important registers. */
8520
8521 /* NOTE: kettenis/20040418: GCC does have two possible register
8522 numbering schemes on the i386: dbx and SVR4. These schemes
8523 differ in how they number %ebp, %esp, %eflags, and the
8524 floating-point registers, and are implemented by the arrays
8525 dbx_register_map[] and svr4_dbx_register_map in
8526 gcc/config/i386.c. GCC also defines a third numbering scheme in
8527 gcc/config/i386.c, which it designates as the "default" register
8528 map used in 64bit mode. This last register numbering scheme is
8529 implemented in dbx64_register_map, and is used for AMD64; see
8530 amd64-tdep.c.
8531
8532 Currently, each GCC i386 target always uses the same register
8533 numbering scheme across all its supported debugging formats
8534 i.e. SDB (COFF), stabs and DWARF 2. This is because
8535 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8536 DBX_REGISTER_NUMBER macro which is defined by each target's
8537 respective config header in a manner independent of the requested
8538 output debugging format.
8539
8540 This does not match the arrangement below, which presumes that
8541 the SDB and stabs numbering schemes differ from the DWARF and
8542 DWARF 2 ones. The reason for this arrangement is that it is
8543 likely to get the numbering scheme for the target's
8544 default/native debug format right. For targets where GCC is the
8545 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8546 targets where the native toolchain uses a different numbering
8547 scheme for a particular debug format (stabs-in-ELF on Solaris)
8548 the defaults below will have to be overridden, like
8549 i386_elf_init_abi() does. */
8550
8551 /* Use the dbx register numbering scheme for stabs and COFF. */
8554
8555 /* Use the SVR4 register numbering scheme for DWARF 2. */
8557
8558 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8559 be in use on any of the supported i386 targets. */
8560
8562
8564
8565 /* Call dummy code. */
8570
8574
8576
8578
8579 /* Stack grows downward. */
8581
8582 set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc);
8583 set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind);
8584
8587
8589
8591
8593
8595
8596 /* Add the i386 register groups. */
8599
8600 /* Helper for function argument information. */
8602
8603 /* Hook the function epilogue frame unwinder. This unwinder is
8604 appended to the list first, so that it supercedes the DWARF
8605 unwinder in function epilogues (where the DWARF unwinder
8606 currently fails). */
8608
8609 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8610 to the list before the prologue-based unwinders, so that DWARF
8611 CFI info will be used if it is available. */
8613
8615
8616 /* Pseudo registers may be changed by amd64_init_abi. */
8622
8625
8626 /* Override the normal target description method to make the AVX
8627 upper halves anonymous. */
8629
8630 /* Even though the default ABI only includes general-purpose registers,
8631 floating-point registers and the SSE registers, we have to leave a
8632 gap for the upper AVX, MPX and AVX512 registers. */
8634
8636
8637 /* Get the x86 target description from INFO. */
8638 tdesc = info.target_desc;
8639 if (! tdesc_has_registers (tdesc))
8640 tdesc = i386_target_description (X86_XSTATE_SSE_MASK, false);
8641 tdep->tdesc = tdesc;
8642
8645
8646 /* No upper YMM registers. */
8647 tdep->ymmh_register_names = NULL;
8648 tdep->ymm0h_regnum = -1;
8649
8650 /* No upper ZMM registers. */
8651 tdep->zmmh_register_names = NULL;
8652 tdep->zmm0h_regnum = -1;
8653
8654 /* No high XMM registers. */
8655 tdep->xmm_avx512_register_names = NULL;
8656 tdep->xmm16_regnum = -1;
8657
8658 /* No upper YMM16-31 registers. */
8659 tdep->ymm16h_register_names = NULL;
8660 tdep->ymm16h_regnum = -1;
8661
8662 tdep->num_byte_regs = 8;
8663 tdep->num_word_regs = 8;
8664 tdep->num_dword_regs = 0;
8665 tdep->num_mmx_regs = 8;
8666 tdep->num_ymm_regs = 0;
8667
8668 /* No MPX registers. */
8669 tdep->bnd0r_regnum = -1;
8670 tdep->bndcfgu_regnum = -1;
8671
8672 /* No AVX512 registers. */
8673 tdep->k0_regnum = -1;
8674 tdep->num_zmm_regs = 0;
8675 tdep->num_ymm_avx512_regs = 0;
8676 tdep->num_xmm_avx512_regs = 0;
8677
8678 /* No PKEYS registers */
8679 tdep->pkru_regnum = -1;
8680 tdep->num_pkeys_regs = 0;
8681
8682 /* No segment base registers. */
8683 tdep->fsbase_regnum = -1;
8684
8686
8688
8690
8694
8695 /* Hook in ABI-specific overrides, if they have been registered.
8696 Note: If INFO specifies a 64 bit arch, this is where we turn
8697 a 32-bit i386 into a 64-bit amd64. */
8698 info.tdesc_data = tdesc_data.get ();
8700
8701 if (!i386_validate_tdesc_p (tdep, tdesc_data.get ()))
8702 {
8703 delete tdep;
8705 return NULL;
8706 }
8707
8708 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8709
8710 /* Wire in pseudo registers. Number of pseudo registers may be
8711 changed. */
8713 + tdep->num_word_regs
8714 + tdep->num_dword_regs
8715 + tdep->num_mmx_regs
8716 + tdep->num_ymm_regs
8717 + num_bnd_cooked
8718 + tdep->num_ymm_avx512_regs
8719 + tdep->num_zmm_regs));
8720
8721 /* Target description may be changed. */
8722 tdesc = tdep->tdesc;
8723
8724 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
8725
8726 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8728
8729 /* Make %al the first pseudo-register. */
8731 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8732
8733 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8734 if (tdep->num_dword_regs)
8735 {
8736 /* Support dword pseudo-register if it hasn't been disabled. */
8737 tdep->eax_regnum = ymm0_regnum;
8738 ymm0_regnum += tdep->num_dword_regs;
8739 }
8740 else
8741 tdep->eax_regnum = -1;
8742
8743 mm0_regnum = ymm0_regnum;
8744 if (tdep->num_ymm_regs)
8745 {
8746 /* Support YMM pseudo-register if it is available. */
8747 tdep->ymm0_regnum = ymm0_regnum;
8748 mm0_regnum += tdep->num_ymm_regs;
8749 }
8750 else
8751 tdep->ymm0_regnum = -1;
8752
8753 if (tdep->num_ymm_avx512_regs)
8754 {
8755 /* Support YMM16-31 pseudo registers if available. */
8756 tdep->ymm16_regnum = mm0_regnum;
8757 mm0_regnum += tdep->num_ymm_avx512_regs;
8758 }
8759 else
8760 tdep->ymm16_regnum = -1;
8761
8762 if (tdep->num_zmm_regs)
8763 {
8764 /* Support ZMM pseudo-register if it is available. */
8765 tdep->zmm0_regnum = mm0_regnum;
8766 mm0_regnum += tdep->num_zmm_regs;
8767 }
8768 else
8769 tdep->zmm0_regnum = -1;
8770
8771 bnd0_regnum = mm0_regnum;
8772 if (tdep->num_mmx_regs != 0)
8773 {
8774 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8775 tdep->mm0_regnum = mm0_regnum;
8776 bnd0_regnum += tdep->num_mmx_regs;
8777 }
8778 else
8779 tdep->mm0_regnum = -1;
8780
8781 if (tdep->bnd0r_regnum > 0)
8782 tdep->bnd0_regnum = bnd0_regnum;
8783 else
8784 tdep-> bnd0_regnum = -1;
8785
8786 /* Hook in the legacy prologue-based unwinders last (fallback). */
8790
8791 /* If we have a register mapping, enable the generic core file
8792 support, unless it has already been enabled. */
8793 if (tdep->gregset_reg_offset
8797
8800
8801 return gdbarch;
8802}
8803
8804
8805
8806/* Return the target description for a specified XSAVE feature mask. */
8807
8808const struct target_desc *
8809i386_target_description (uint64_t xcr0, bool segments)
8810{
8811 static target_desc *i386_tdescs \
8812 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
8813 target_desc **tdesc;
8814
8815 tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0]
8816 [(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
8817 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
8818 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
8819 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0]
8820 [segments ? 1 : 0];
8821
8822 if (*tdesc == NULL)
8823 *tdesc = i386_create_target_description (xcr0, false, segments);
8824
8825 return *tdesc;
8826}
8827
8828#define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8829
8830/* Find the bound directory base address. */
8831
8832static unsigned long
8834{
8835 struct regcache *rcache;
8836 ULONGEST ret;
8837 enum register_status regstatus;
8838
8839 rcache = get_current_regcache ();
8840 gdbarch *arch = rcache->arch ();
8841 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
8842
8843 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8844
8845 if (regstatus != REG_VALID)
8846 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8847
8848 return ret & MPX_BASE_MASK;
8849}
8850
8851int
8853{
8855 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
8856 const struct target_desc *tdesc = tdep->tdesc;
8857
8858 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8859}
8860
8861#define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8862#define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8863#define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8864#define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8865
8866/* Find the bound table entry given the pointer location and the base
8867 address of the table. */
8868
8869static CORE_ADDR
8870i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8871{
8872 CORE_ADDR offset1;
8873 CORE_ADDR offset2;
8874 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8875 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8876 CORE_ADDR bd_entry_addr;
8877 CORE_ADDR bt_addr;
8878 CORE_ADDR bd_entry;
8879 struct gdbarch *gdbarch = get_current_arch ();
8880 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8881
8882
8883 if (gdbarch_ptr_bit (gdbarch) == 64)
8884 {
8885 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8886 bd_ptr_r_shift = 20;
8887 bd_ptr_l_shift = 3;
8888 bt_select_r_shift = 3;
8889 bt_select_l_shift = 5;
8890 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8891
8892 if ( sizeof (CORE_ADDR) == 4)
8893 error (_("bound table examination not supported\
8894 for 64-bit process with 32-bit GDB"));
8895 }
8896 else
8897 {
8898 mpx_bd_mask = MPX_BD_MASK_32;
8899 bd_ptr_r_shift = 12;
8900 bd_ptr_l_shift = 2;
8901 bt_select_r_shift = 2;
8902 bt_select_l_shift = 4;
8903 bt_mask = MPX_BT_MASK_32;
8904 }
8905
8906 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8907 bd_entry_addr = bd_base + offset1;
8908 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8909
8910 if ((bd_entry & 0x1) == 0)
8911 error (_("Invalid bounds directory entry at %s."),
8912 paddress (get_current_arch (), bd_entry_addr));
8913
8914 /* Clearing status bit. */
8915 bd_entry--;
8916 bt_addr = bd_entry & ~bt_select_r_shift;
8917 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8918
8919 return bt_addr + offset2;
8920}
8921
8922/* Print routine for the mpx bounds. */
8923
8924static void
8925i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8926{
8927 struct ui_out *uiout = current_uiout;
8928 LONGEST size;
8929 struct gdbarch *gdbarch = get_current_arch ();
8930 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8931 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8932
8933 if (bounds_in_map == 1)
8934 {
8935 uiout->text ("Null bounds on map:");
8936 uiout->text (" pointer value = ");
8937 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8938 uiout->text (".");
8939 uiout->text ("\n");
8940 }
8941 else
8942 {
8943 uiout->text ("{lbound = ");
8944 uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]);
8945 uiout->text (", ubound = ");
8946
8947 /* The upper bound is stored in 1's complement. */
8948 uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]);
8949 uiout->text ("}: pointer value = ");
8950 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8951
8952 if (gdbarch_ptr_bit (gdbarch) == 64)
8953 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8954 else
8955 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8956
8957 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8958 -1 represents in this sense full memory access, and there is no need
8959 one to the size. */
8960
8961 size = (size > -1 ? size + 1 : size);
8962 uiout->text (", size = ");
8963 uiout->field_string ("size", plongest (size));
8964
8965 uiout->text (", metadata = ");
8966 uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]);
8967 uiout->text ("\n");
8968 }
8969}
8970
8971/* Implement the command "show mpx bound". */
8972
8973static void
8974i386_mpx_info_bounds (const char *args, int from_tty)
8975{
8976 CORE_ADDR bd_base = 0;
8977 CORE_ADDR addr;
8978 CORE_ADDR bt_entry_addr = 0;
8979 CORE_ADDR bt_entry[4];
8980 int i;
8981 struct gdbarch *gdbarch = get_current_arch ();
8982 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8983
8984 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8985 || !i386_mpx_enabled ())
8986 {
8987 gdb_printf (_("Intel Memory Protection Extensions not "
8988 "supported on this target.\n"));
8989 return;
8990 }
8991
8992 if (args == NULL)
8993 {
8994 gdb_printf (_("Address of pointer variable expected.\n"));
8995 return;
8996 }
8997
8998 addr = parse_and_eval_address (args);
8999
9000 bd_base = i386_mpx_bd_base ();
9001 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
9002
9003 memset (bt_entry, 0, sizeof (bt_entry));
9004
9005 for (i = 0; i < 4; i++)
9006 bt_entry[i] = read_memory_typed_address (bt_entry_addr
9007 + i * data_ptr_type->length (),
9008 data_ptr_type);
9009
9010 i386_mpx_print_bounds (bt_entry);
9011}
9012
9013/* Implement the command "set mpx bound". */
9014
9015static void
9016i386_mpx_set_bounds (const char *args, int from_tty)
9017{
9018 CORE_ADDR bd_base = 0;
9019 CORE_ADDR addr, lower, upper;
9020 CORE_ADDR bt_entry_addr = 0;
9021 CORE_ADDR bt_entry[2];
9022 const char *input = args;
9023 int i;
9024 struct gdbarch *gdbarch = get_current_arch ();
9025 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9026 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
9027
9028 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
9029 || !i386_mpx_enabled ())
9030 error (_("Intel Memory Protection Extensions not supported\
9031 on this target."));
9032
9033 if (args == NULL)
9034 error (_("Pointer value expected."));
9035
9036 addr = value_as_address (parse_to_comma_and_eval (&input));
9037
9038 if (input[0] == ',')
9039 ++input;
9040 if (input[0] == '\0')
9041 error (_("wrong number of arguments: missing lower and upper bound."));
9042 lower = value_as_address (parse_to_comma_and_eval (&input));
9043
9044 if (input[0] == ',')
9045 ++input;
9046 if (input[0] == '\0')
9047 error (_("Wrong number of arguments; Missing upper bound."));
9048 upper = value_as_address (parse_to_comma_and_eval (&input));
9049
9050 bd_base = i386_mpx_bd_base ();
9051 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
9052 for (i = 0; i < 2; i++)
9053 bt_entry[i] = read_memory_typed_address (bt_entry_addr
9054 + i * data_ptr_type->length (),
9055 data_ptr_type);
9056 bt_entry[0] = (uint64_t) lower;
9057 bt_entry[1] = ~(uint64_t) upper;
9058
9059 for (i = 0; i < 2; i++)
9060 write_memory_unsigned_integer (bt_entry_addr
9061 + i * data_ptr_type->length (),
9062 data_ptr_type->length (), byte_order,
9063 bt_entry[i]);
9064}
9065
9067
9068void _initialize_i386_tdep ();
9069void
9071{
9072 gdbarch_register (bfd_arch_i386, i386_gdbarch_init);
9073
9074 /* Add the variable that controls the disassembly flavor. */
9075 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
9076 &disassembly_flavor, _("\
9077Set the disassembly flavor."), _("\
9078Show the disassembly flavor."), _("\
9079The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9080 NULL,
9081 NULL, /* FIXME: i18n: */
9082 &setlist, &showlist);
9083
9084 /* Add the variable that controls the convention for returning
9085 structs. */
9086 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
9087 &struct_convention, _("\
9088Set the convention for returning small structs."), _("\
9089Show the convention for returning small structs."), _("\
9090Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9091is \"default\"."),
9092 NULL,
9093 NULL, /* FIXME: i18n: */
9094 &setlist, &showlist);
9095
9096 /* Add "mpx" prefix for the set and show commands. */
9097
9099 ("mpx", class_support,
9100 _("Set Intel Memory Protection Extensions specific variables."),
9101 _("Show Intel Memory Protection Extensions specific variables."),
9103
9104 /* Add "bound" command for the show mpx commands list. */
9105
9107 "Show the memory bounds for a given array/pointer storage\
9108 in the bound table.",
9110
9111 /* Add "bound" command for the set mpx commands list. */
9112
9114 "Set the memory bounds for a given array/pointer storage\
9115 in the bound table.",
9117
9118 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
9120
9121 /* Initialize the i386-specific register groups. */
9123
9124 /* Tell remote stub that we support XML target description. */
9126}
int regnum
Definition: aarch64-tdep.c:68
const char *const name
Definition: aarch64-tdep.c:67
int code
Definition: ada-lex.l:688
void gdbarch_free(struct gdbarch *arch)
Definition: arch-utils.c:1192
int default_print_insn(bfd_vma memaddr, disassemble_info *info)
Definition: arch-utils.c:1033
const struct floatformat ** default_floatformat_for_type(struct gdbarch *gdbarch, const char *name, int len)
Definition: arch-utils.c:289
struct gdbarch * get_current_arch(void)
Definition: arch-utils.c:846
struct gdbarch * target_gdbarch(void)
Definition: arch-utils.c:1453
static std::vector< const char * > arches
Definition: arch-utils.c:685
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep)
Definition: arch-utils.c:1256
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition: arch-utils.c:177
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
Definition: arch-utils.c:1298
#define BP_MANIPULATION(BREAK_INSN)
Definition: arch-utils.h:70
@ pcc_struct_return
Definition: arm-tdep.h:85
@ axs_lvalue_memory
Definition: ax-gdb.h:62
void ax_reg_mask(struct agent_expr *ax, int reg)
Definition: ax-general.c:424
void ax_simple(struct agent_expr *x, enum agent_op op)
Definition: ax-general.c:126
void ax_const_l(struct agent_expr *x, LONGEST l)
Definition: ax-general.c:230
void ax_reg(struct agent_expr *x, int reg)
Definition: ax-general.c:275
bool find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr, const struct block **block)
Definition: blockframe.c:373
enum register_status raw_read(int regnum, gdb_byte *buf)
Definition: regcache.c:605
gdbarch * arch() const
Definition: regcache.c:230
void raw_collect(int regnum, void *buf) const override
Definition: regcache.c:1118
void raw_supply(int regnum, const void *buf) override
Definition: regcache.c:1053
void cooked_write(int regnum, const gdb_byte *buf)
Definition: regcache.c:861
void raw_write_part(int regnum, int offset, int len, const gdb_byte *buf)
Definition: regcache.c:1023
void raw_write(int regnum, const gdb_byte *buf)
Definition: regcache.c:827
void * get(unsigned key)
Definition: registry.h:211
Definition: ui-out.h:160
void field_core_addr(const char *fldname, struct gdbarch *gdbarch, CORE_ADDR address)
Definition: ui-out.c:478
void field_string(const char *fldname, const char *string, const ui_file_style &style=ui_file_style())
Definition: ui-out.c:511
void text(const char *string)
Definition: ui-out.c:566
struct cmd_list_element * showlist
Definition: cli-cmds.c:125
struct cmd_list_element * setlist
Definition: cli-cmds.c:117
struct cmd_list_element * add_cmd(const char *name, enum command_class theclass, const char *doc, struct cmd_list_element **list)
Definition: cli-decode.c:233
set_show_commands add_setshow_enum_cmd(const char *name, enum command_class theclass, const char *const *enumlist, const char **var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:618
set_show_commands add_setshow_prefix_cmd(const char *name, command_class theclass, const char *set_doc, const char *show_doc, cmd_list_element **set_subcommands_list, cmd_list_element **show_subcommands_list, cmd_list_element **set_list, cmd_list_element **show_list)
Definition: cli-decode.c:428
@ class_support
Definition: command.h:58
@ no_class
Definition: command.h:53
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition: corefile.c:346
CORE_ADDR read_memory_typed_address(CORE_ADDR addr, struct type *type)
Definition: corefile.c:335
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:305
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
Definition: corefile.c:369
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: corefile.c:237
LONGEST read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:295
ULONGEST read_code_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:325
void read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: corefile.c:253
LONGEST read_code_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:315
static void store_signed_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, LONGEST val)
Definition: defs.h:554
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition: defs.h:561
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
Definition: findvar.c:153
@ lval_register
Definition: defs.h:366
static LONGEST extract_signed_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
Definition: defs.h:511
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
Definition: defs.h:526
return_value_convention
Definition: defs.h:258
@ RETURN_VALUE_ABI_RETURNS_ADDRESS
Definition: defs.h:274
@ RETURN_VALUE_REGISTER_CONVENTION
Definition: defs.h:261
int gdb_buffered_insn_length(struct gdbarch *gdbarch, const gdb_byte *insn, int max_len, CORE_ADDR addr)
Definition: disasm.c:1266
int gdb_insn_length(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: disasm.c:1215
#define displaced_debug_printf(fmt,...)
std::unique_ptr< displaced_step_copy_insn_closure > displaced_step_copy_insn_closure_up
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
Definition: frame.c:1361
struct value * parse_to_comma_and_eval(const char **expp)
Definition: eval.c:82
CORE_ADDR parse_and_eval_address(const char *exp)
Definition: eval.c:52
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition: frame-base.c:93
int default_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
Definition: frame-unwind.c:217
struct value * frame_unwind_got_memory(frame_info_ptr frame, int regnum, CORE_ADDR addr)
Definition: frame-unwind.c:286
struct value * frame_unwind_got_register(frame_info_ptr frame, int regnum, int new_regnum)
Definition: frame-unwind.c:276
struct value * frame_unwind_got_constant(frame_info_ptr frame, int regnum, ULONGEST val)
Definition: frame-unwind.c:299
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
Definition: frame-unwind.c:107
int frame_relative_level(frame_info_ptr fi)
Definition: frame.c:2826
ULONGEST get_frame_register_unsigned(frame_info_ptr frame, int regnum)
Definition: frame.c:1351
CORE_ADDR get_frame_pc(frame_info_ptr frame)
Definition: frame.c:2592
void get_frame_register(frame_info_ptr frame, int regnum, gdb_byte *buf)
Definition: frame.c:1215
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:713
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
Definition: frame.c:2907
void frame_unwind_register(frame_info_ptr next_frame, int regnum, gdb_byte *buf)
Definition: frame.c:1195
struct frame_id frame_id_build_unavailable_stack(CORE_ADDR code_addr)
Definition: frame.c:686
CORE_ADDR get_frame_func(frame_info_ptr this_frame)
Definition: frame.c:1050
bool get_frame_register_bytes(frame_info_ptr frame, int regnum, CORE_ADDR offset, gdb::array_view< gdb_byte > buffer, int *optimizedp, int *unavailablep)
Definition: frame.c:1432
bool deprecated_frame_register_read(frame_info_ptr frame, int regnum, gdb_byte *myaddr)
Definition: frame.c:1416
void put_frame_register(frame_info_ptr frame, int regnum, const gdb_byte *buf)
Definition: frame.c:1378
@ SIGTRAMP_FRAME
Definition: frame.h:190
@ NORMAL_FRAME
Definition: frame.h:179
unwind_stop_reason
Definition: frame.h:436
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition: frame.h:608
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype *stab_reg_to_regnum)
void set_gdbarch_insn_is_jump(struct gdbarch *gdbarch, gdbarch_insn_is_jump_ftype *insn_is_jump)
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:2023
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype *unwind_pc)
void set_gdbarch_fetch_pointer_argument(struct gdbarch *gdbarch, gdbarch_fetch_pointer_argument_ftype *fetch_pointer_argument)
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition: gdbarch.c:2050
void set_gdbarch_register_to_value(struct gdbarch *gdbarch, gdbarch_register_to_value_ftype *register_to_value)
void set_gdbarch_gen_return_address(struct gdbarch *gdbarch, gdbarch_gen_return_address_ftype *gen_return_address)
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1370
void set_gdbarch_value_to_register(struct gdbarch *gdbarch, gdbarch_value_to_register_ftype *value_to_register)
void set_gdbarch_stap_parse_special_token(struct gdbarch *gdbarch, gdbarch_stap_parse_special_token_ftype *stap_parse_special_token)
void set_gdbarch_stap_integer_prefixes(struct gdbarch *gdbarch, const char *const *stap_integer_prefixes)
Definition: gdbarch.c:4460
void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype *breakpoint_kind_from_pc)
void set_gdbarch_pseudo_register_read_value(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_value_ftype *pseudo_register_read_value)
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype *frame_align)
void set_gdbarch_max_insn_length(struct gdbarch *gdbarch, ULONGEST max_insn_length)
Definition: gdbarch.c:4003
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype *get_longjmp_target)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype *skip_prologue)
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *register_name)
void set_gdbarch_push_dummy_code(struct gdbarch *gdbarch, gdbarch_push_dummy_code_ftype *push_dummy_code)
void set_gdbarch_skip_trampoline_code(struct gdbarch *gdbarch, gdbarch_skip_trampoline_code_ftype *skip_trampoline_code)
void set_gdbarch_bfloat16_format(struct gdbarch *gdbarch, const struct floatformat **bfloat16_format)
Definition: gdbarch.c:1500
void set_gdbarch_stap_is_single_operand(struct gdbarch *gdbarch, gdbarch_stap_is_single_operand_ftype *stap_is_single_operand)
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype *return_value)
void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
Definition: gdbarch.c:2848
void set_gdbarch_gnu_triplet_regexp(struct gdbarch *gdbarch, gdbarch_gnu_triplet_regexp_ftype *gnu_triplet_regexp)
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1899
void set_gdbarch_fp0_regnum(struct gdbarch *gdbarch, int fp0_regnum)
Definition: gdbarch.c:2067
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype *inner_than)
void set_gdbarch_stap_register_indirection_prefixes(struct gdbarch *gdbarch, const char *const *stap_register_indirection_prefixes)
Definition: gdbarch.c:4528
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition: gdbarch.c:2016
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *register_reggroup_p)
void set_gdbarch_ax_pseudo_register_collect(struct gdbarch *gdbarch, gdbarch_ax_pseudo_register_collect_ftype *ax_pseudo_register_collect)
void set_gdbarch_long_double_format(struct gdbarch *gdbarch, const struct floatformat **long_double_format)
Definition: gdbarch.c:1632
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2033
void set_gdbarch_call_dummy_location(struct gdbarch *gdbarch, enum call_dummy_location_type call_dummy_location)
Definition: gdbarch.c:2248
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype *print_insn)
int gdbarch_long_double_bit(struct gdbarch *gdbarch)
Definition: gdbarch.c:1606
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype *pseudo_register_write)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition: gdbarch.c:1927
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype *dwarf2_reg_to_regnum)
bool gdbarch_iterate_over_regset_sections_p(struct gdbarch *gdbarch)
Definition: gdbarch.c:3645
void set_gdbarch_insn_is_ret(struct gdbarch *gdbarch, gdbarch_insn_is_ret_ftype *insn_is_ret)
void set_gdbarch_convert_register_p(struct gdbarch *gdbarch, gdbarch_convert_register_p_ftype *convert_register_p)
void set_gdbarch_type_align(struct gdbarch *gdbarch, gdbarch_type_align_ftype *type_align)
void set_gdbarch_fast_tracepoint_valid_at(struct gdbarch *gdbarch, gdbarch_fast_tracepoint_valid_at_ftype *fast_tracepoint_valid_at)
void set_gdbarch_insn_is_call(struct gdbarch *gdbarch, gdbarch_insn_is_call_ftype *insn_is_call)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:1910
const struct bfd_arch_info * gdbarch_bfd_arch_info(struct gdbarch *gdbarch)
Definition: gdbarch.c:1361
void set_gdbarch_long_double_bit(struct gdbarch *gdbarch, int long_double_bit)
Definition: gdbarch.c:1616
void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype *sw_breakpoint_from_kind)
int gdbarch_ptr_bit(struct gdbarch *gdbarch)
Definition: gdbarch.c:1691
void set_gdbarch_sdb_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_sdb_reg_to_regnum_ftype *sdb_reg_to_regnum)
void set_gdbarch_stap_register_prefixes(struct gdbarch *gdbarch, const char *const *stap_register_prefixes)
Definition: gdbarch.c:4494
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype *dummy_id)
void set_gdbarch_relocate_instruction(struct gdbarch *gdbarch, gdbarch_relocate_instruction_ftype *relocate_instruction)
void set_gdbarch_print_float_info(struct gdbarch *gdbarch, gdbarch_print_float_info_ftype *print_float_info)
void set_gdbarch_stap_register_indirection_suffixes(struct gdbarch *gdbarch, const char *const *stap_register_indirection_suffixes)
Definition: gdbarch.c:4545
ULONGEST gdbarch_max_insn_length(struct gdbarch *gdbarch)
Definition: gdbarch.c:3992
void set_gdbarch_floatformat_for_type(struct gdbarch *gdbarch, gdbarch_floatformat_for_type_ftype *floatformat_for_type)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype *push_dummy_call)
void set_gdbarch_in_indirect_branch_thunk(struct gdbarch *gdbarch, gdbarch_in_indirect_branch_thunk_ftype *in_indirect_branch_thunk)
void set_gdbarch_iterate_over_regset_sections(struct gdbarch *gdbarch, gdbarch_iterate_over_regset_sections_ftype *iterate_over_regset_sections)
void set_gdbarch_stap_adjust_register(struct gdbarch *gdbarch, gdbarch_stap_adjust_register_ftype *stap_adjust_register)
void set_gdbarch_frame_args_skip(struct gdbarch *gdbarch, CORE_ADDR frame_args_skip)
Definition: gdbarch.c:2947
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep_base *tdep)
Definition: gdbarch.c:264
void() iterate_over_regset_sections_cb(const char *sect_name, int supply_size, int collect_size, const struct regset *regset, const char *human_name, void *cb_data)
Definition: gdbarch.h:102
@ ON_STACK
Definition: gdbarch.h:155
static int gdbarch_num_cooked_regs(gdbarch *arch)
Definition: gdbarch.h:377
function_call_return_method
Definition: gdbarch.h:112
@ return_method_struct
Definition: gdbarch.h:124
struct type * lookup_pointer_type(struct type *type)
Definition: gdbtypes.c:402
int field_is_static(struct field *f)
Definition: gdbtypes.c:5048
struct type * arch_composite_type(struct gdbarch *gdbarch, const char *name, enum type_code code)
Definition: gdbtypes.c:5989
const struct floatformat * floatformats_ieee_quad[BFD_ENDIAN_UNKNOWN]
Definition: gdbtypes.c:91
struct type * init_vector_type(struct type *elt_type, int n)
Definition: gdbtypes.c:1540
const struct floatformat * floatformats_bfloat16[BFD_ENDIAN_UNKNOWN]
Definition: gdbtypes.c:127
void append_composite_type_field(struct type *t, const char *name, struct type *field)
Definition: gdbtypes.c:6065
const struct floatformat * floatformats_i387_ext[BFD_ENDIAN_UNKNOWN]
Definition: gdbtypes.c:99
struct type * check_typedef(struct type *type)
Definition: gdbtypes.c:3010
type_code
Definition: gdbtypes.h:99
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
Definition: gnu-nat.c:1791
unsigned short offset1
Definition: go32-nat.c:7
size_t size
Definition: go32-nat.c:241
static void append_insns(CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
Definition: i386-tdep.c:962
int i386_svr4_reg_to_regnum(struct gdbarch *gdbarch, int reg)
Definition: i386-tdep.c:578
void i386_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
Definition: i386-tdep.c:4002
bool i386_pkru_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:427
static CORE_ADDR i386_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr)
Definition: i386-tdep.c:2840
#define PREFIX_DATA
Definition: i386-tdep.c:4670
static struct value * i386_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
Definition: i386-tdep.c:2140
static CORE_ADDR i386_analyze_struct_return(CORE_ADDR pc, CORE_ADDR current_pc, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1161
int i386_sigtramp_p(frame_info_ptr this_frame)
Definition: i386-tdep.c:4051
int i386_bnd_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:317
static int i386_mmx_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:170
static int i386_match_insn_block(CORE_ADDR pc, struct i386_insn *insn_patterns)
Definition: i386-tdep.c:1435
static struct frame_id i386_dummy_id(struct gdbarch *gdbarch, frame_info_ptr this_frame)
Definition: i386-tdep.c:2581
static struct cmd_list_element * mpx_show_cmdlist
Definition: i386-tdep.c:9066
#define I386_MAX_MATCHED_INSN_LEN
Definition: i386-tdep.c:1371
static int i386_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: i386-tdep.c:2219
static enum return_value_convention i386_return_value(struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition: i386-tdep.c:3031
static enum unwind_stop_reason i386_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
Definition: i386-tdep.c:2124
static CORE_ADDR i386_push_dummy_code(struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache)
Definition: i386-tdep.c:2669
int i386_fp_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:373
int i386_zmm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:235
struct type * i387_ext_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3099
const char * i386_pseudo_register_name(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:463
static const reggroup * i386_mmx_reggroup
Definition: i386-tdep.c:4534
static int i386_call_p(const gdb_byte *insn)
Definition: i386-tdep.c:732
int i386_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
Definition: i386-tdep.c:4551
#define HIGH_RETURN_REGNUM
Definition: i386-tdep.c:2855
const struct regset i386_fpregset
Definition: i386-tdep.c:3994
static CORE_ADDR i386_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
Definition: i386-tdep.c:2595
static int i386_absolute_call_p(const gdb_byte *insn)
Definition: i386-tdep.c:694
static ULONGEST i386_type_align(struct gdbarch *gdbarch, struct type *type)
Definition: i386-tdep.c:8420
static CORE_ADDR i386_frame_base_address(frame_info_ptr this_frame, void **this_cache)
Definition: i386-tdep.c:2565
#define I386_SAVE_FPU_REGS
Definition: i386-tdep.c:4987
static int i386_validate_tdesc_p(i386_gdbarch_tdep *tdep, struct tdesc_arch_data *tdesc_data)
Definition: i386-tdep.c:8244
static int i386_fast_tracepoint_valid_at(struct gdbarch *gdbarch, CORE_ADDR addr, std::string *msg)
Definition: i386-tdep.c:8172
static int i386_mpx_ctrl_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:413
int i386_process_record(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR input_addr)
Definition: i386-tdep.c:5059
int i386_stap_is_single_operand(struct gdbarch *gdbarch, const char *s)
Definition: i386-tdep.c:4121
static const char *const i386_ymmh_names[]
Definition: i386-tdep.c:114
static int i386_jmp_p(const gdb_byte *insn)
Definition: i386-tdep.c:680
static const char *const i386_zmm_names[]
Definition: i386-tdep.c:90
static struct gdbarch * i386_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
Definition: i386-tdep.c:8444
static CORE_ADDR i386_mpx_get_bt_entry(CORE_ADDR ptr, CORE_ADDR bd_base)
Definition: i386-tdep.c:8870
static int i386_convert_register_p(struct gdbarch *gdbarch, int regnum, struct type *type)
Definition: i386-tdep.c:3797
static void i386_mpx_info_bounds(const char *args, int from_tty)
Definition: i386-tdep.c:8974
static void i386_mpx_print_bounds(const CORE_ADDR bt_entry[4])
Definition: i386-tdep.c:8925
static const char *const i386_k_names[]
Definition: i386-tdep.c:102
static int i386_record_lea_modrm_addr(struct i386_record_s *irp, uint64_t *addr)
Definition: i386-tdep.c:4738
#define PREFIX_ADDR
Definition: i386-tdep.c:4671
static enum unwind_stop_reason i386_epilogue_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
Definition: i386-tdep.c:2285
void i386_svr4_init_abi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: i386-tdep.c:4510
static void i386_collect_gregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *gregs, size_t len)
Definition: i386-tdep.c:3924
static void i386_store_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, const gdb_byte *valbuf)
Definition: i386-tdep.c:2918
static CORE_ADDR i386_analyze_stack_align(CORE_ADDR pc, CORE_ADDR current_pc, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1260
static const char *const i386_mpx_names[]
Definition: i386-tdep.c:120
static i386_insn i386_frame_setup_skip_insns[]
Definition: i386-tdep.c:1473
static const char *const i386_mmx_names[]
Definition: i386-tdep.c:139
static int i386_record_push(struct i386_record_s *irp, int size)
Definition: i386-tdep.c:4969
static CORE_ADDR i386_skip_noop(CORE_ADDR pc)
Definition: i386-tdep.c:1543
static CORE_ADDR i386_skip_endbr(CORE_ADDR pc)
Definition: i386-tdep.c:1524
int i386_dword_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:207
static std::string i386_stap_adjust_register(struct gdbarch *gdbarch, struct stap_parse_info *p, const std::string &regname, int regnum)
Definition: i386-tdep.c:4433
static int i386_print_insn(bfd_vma pc, struct disassemble_info *info)
Definition: i386-tdep.c:4065
static void i386_init_reggroups(void)
Definition: i386-tdep.c:4537
static void i386_relocate_instruction(struct gdbarch *gdbarch, CORE_ADDR *to, CORE_ADDR oldloc)
Definition: i386-tdep.c:969
static int i386_record_lea_modrm(struct i386_record_s *irp)
Definition: i386-tdep.c:4936
const struct regset i386_gregset
Definition: i386-tdep.c:3989
int i386_ymm_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:302
static const char * i386_gnu_triplet_regexp(struct gdbarch *gdbarch)
Definition: i386-tdep.c:4458
static int i386_ymmh_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:261
int i386_k_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:248
const int num_lower_zmm_regs
Definition: i386-tdep.c:165
static const char *const i386_pkeys_names[]
Definition: i386-tdep.c:125
static int i386_ymmh_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:289
static i386_insn i386_tramp_chain_in_reg_insns[]
Definition: i386-tdep.c:2342
const struct target_desc * i386_target_description(uint64_t xcr0, bool segments)
Definition: i386-tdep.c:8809
constexpr gdb_byte i386_break_insn[]
Definition: i386-tdep.c:613
static void i386_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
Definition: i386-tdep.c:2105
#define PREFIX_LOCK
Definition: i386-tdep.c:4669
#define PREFIX_REPZ
Definition: i386-tdep.c:4667
void i386_pseudo_register_read_into_value(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, struct value *result_value)
Definition: i386-tdep.c:3366
int i386_ymm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:276
static void i386_extract_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, gdb_byte *valbuf)
Definition: i386-tdep.c:2861
static int i386_ret_p(const gdb_byte *insn)
Definition: i386-tdep.c:715
static int i386_match_pattern(CORE_ADDR pc, struct i386_insn pattern)
Definition: i386-tdep.c:1384
static CORE_ADDR i386_fetch_pointer_argument(frame_info_ptr frame, int argi, struct type *type)
Definition: i386-tdep.c:4658
static void i386_add_reggroups(struct gdbarch *gdbarch)
Definition: i386-tdep.c:4544
static i386_insn i386_tramp_chain_on_stack_insns[]
Definition: i386-tdep.c:2355
static const char att_flavor[]
Definition: i386-tdep.c:591
static struct type * i386_zmm_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3153
static const struct frame_unwind i386_stack_tramp_frame_unwind
Definition: i386-tdep.c:2403
#define LOW_RETURN_REGNUM
Definition: i386-tdep.c:2854
@ OT_QUAD
Definition: i386-tdep.c:4679
@ OT_BYTE
Definition: i386-tdep.c:4676
@ OT_WORD
Definition: i386-tdep.c:4677
@ OT_DQUAD
Definition: i386-tdep.c:4680
@ OT_LONG
Definition: i386-tdep.c:4678
static bool i386_in_indirect_branch_thunk(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: i386-tdep.c:4468
static struct type * i386_mmx_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3269
#define MPX_BT_MASK
Definition: i386-tdep.c:8862
static int i386_get_longjmp_target(frame_info_ptr frame, CORE_ADDR *pc)
Definition: i386-tdep.c:2608
void i386_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: i386-tdep.c:3561
static int i386_dbx_reg_to_regnum(struct gdbarch *gdbarch, int reg)
Definition: i386-tdep.c:486
static int i386_reg_struct_return_p(struct gdbarch *gdbarch, struct type *type)
Definition: i386-tdep.c:2997
static struct cmd_list_element * mpx_set_cmdlist
Definition: i386-tdep.c:9066
static const char * struct_convention
Definition: i386-tdep.c:2990
CORE_ADDR i386_thiscall_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr, bool thiscall)
Definition: i386-tdep.c:2686
static struct i386_frame_cache * i386_epilogue_frame_cache(frame_info_ptr this_frame, void **this_cache)
Definition: i386-tdep.c:2250
displaced_step_copy_insn_closure_up i386_displaced_step_copy_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: i386-tdep.c:806
#define I386_SAVE_FPU_ENV_REG_STACK
Definition: i386-tdep.c:4989
static struct type * i386_bnd_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3117
static struct value * i386_epilogue_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
Definition: i386-tdep.c:2312
#define MPX_BASE_MASK
Definition: i386-tdep.c:8828
static struct value * i386_sigtramp_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
Definition: i386-tdep.c:2512
static const char reg_struct_convention[]
Definition: i386-tdep.c:2982
CORE_ADDR i386_pe_skip_trampoline_code(frame_info_ptr frame, CORE_ADDR pc, char *name)
Definition: i386-tdep.c:4020
#define PREFIX_REPNZ
Definition: i386-tdep.c:4668
static const char * disassembly_flavor
Definition: i386-tdep.c:599
static const struct frame_base i386_frame_base
Definition: i386-tdep.c:2572
static const char *const i386_zmmh_names[]
Definition: i386-tdep.c:96
#define I386_NUM_SAVED_REGS
Definition: i386-tdep.c:1052
static int i386_stack_tramp_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_cache)
Definition: i386-tdep.c:2393
static CORE_ADDR i386_skip_probe(CORE_ADDR pc)
Definition: i386-tdep.c:1213
static struct type * i386_ymm_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3212
static int i386_insn_is_call(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: i386-tdep.c:767
static int i386_record_floats(struct gdbarch *gdbarch, struct i386_record_s *ir, uint32_t iregnum)
Definition: i386-tdep.c:4995
int i386_fpc_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:385
static void i386_supply_fpregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len)
Definition: i386-tdep.c:3948
#define MPX_BD_MASK_32
Definition: i386-tdep.c:8863
static unsigned long i386_mpx_bd_base(void)
Definition: i386-tdep.c:8833
static const char pcc_struct_convention[]
Definition: i386-tdep.c:2981
static CORE_ADDR i386_analyze_register_saves(CORE_ADDR pc, CORE_ADDR current_pc, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1760
static void i386_collect_fpregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len)
Definition: i386-tdep.c:3970
#define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum)
Definition: i386-tdep.c:5055
int i386_xmm_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:347
static const struct frame_unwind i386_sigtramp_frame_unwind
Definition: i386-tdep.c:2552
static CORE_ADDR i386_unwind_pc(struct gdbarch *gdbarch, frame_info_ptr next_frame)
Definition: i386-tdep.c:1968
static const char * i386_register_name(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:443
static void i386_epilogue_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
Definition: i386-tdep.c:2298
static const char *const i386_ymm_names[]
Definition: i386-tdep.c:108
#define I386_SAVE_FPU_ENV
Definition: i386-tdep.c:4988
static const char *const valid_flavors[]
Definition: i386-tdep.c:593
static int i386_bndr_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:399
static struct i386_frame_cache * i386_alloc_frame_cache(void)
Definition: i386-tdep.c:1075
static struct i386_insn * i386_match_insn(CORE_ADDR pc, struct i386_insn *insn_patterns)
Definition: i386-tdep.c:1418
static const reggroup * i386_sse_reggroup
Definition: i386-tdep.c:4533
static CORE_ADDR i386_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
Definition: i386-tdep.c:1830
static void i386_gen_return_address(struct gdbarch *gdbarch, struct agent_expr *ax, struct axs_value *value, CORE_ADDR scope)
Definition: i386-tdep.c:2417
static int i386_svr4_dwarf_reg_to_regnum(struct gdbarch *gdbarch, int reg)
Definition: i386-tdep.c:533
static int i386_sigtramp_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
Definition: i386-tdep.c:2522
static int i386_next_regnum(int regnum)
Definition: i386-tdep.c:3768
static expr::operation_up i386_stap_parse_special_token_three_arg_disp(struct gdbarch *gdbarch, struct stap_parse_info *p)
Definition: i386-tdep.c:4271
CORE_ADDR i386_skip_main_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: i386-tdep.c:1934
@ OP_XORL
Definition: i386-tdep.c:4692
@ OP_ADCL
Definition: i386-tdep.c:4688
@ OP_ADDL
Definition: i386-tdep.c:4686
@ OP_ORL
Definition: i386-tdep.c:4687
@ OP_SUBL
Definition: i386-tdep.c:4691
@ OP_CMPL
Definition: i386-tdep.c:4693
@ OP_ANDL
Definition: i386-tdep.c:4690
@ OP_SBBL
Definition: i386-tdep.c:4689
int i386_byte_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:185
int i386_xmm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:332
static int i386_register_to_value(frame_info_ptr frame, int regnum, struct type *type, gdb_byte *to, int *optimizedp, int *unavailablep)
Definition: i386-tdep.c:3828
#define MPX_BD_MASK
Definition: i386-tdep.c:8861
static const struct frame_unwind i386_frame_unwind
Definition: i386-tdep.c:2199
static int i386_syscall_p(const gdb_byte *insn, int *lengthp)
Definition: i386-tdep.c:748
int i386_ax_pseudo_register_collect(struct gdbarch *gdbarch, struct agent_expr *ax, int regnum)
Definition: i386-tdep.c:3684
static const char intel_flavor[]
Definition: i386-tdep.c:592
void i386_elf_init_abi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: i386-tdep.c:4477
static void i386_frame_cache_1(frame_info_ptr this_frame, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1980
static CORE_ADDR i386_analyze_frame_setup(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR limit, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1597
static const struct floatformat ** i386_floatformat_for_type(struct gdbarch *gdbarch, const char *name, int len)
Definition: i386-tdep.c:8224
static int i386_absolute_jmp_p(const gdb_byte *insn)
Definition: i386-tdep.c:657
static enum unwind_stop_reason i386_sigtramp_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
Definition: i386-tdep.c:2483
static const int i386_record_regmap[]
Definition: i386-tdep.c:8152
static void i386_value_to_register(frame_info_ptr frame, int regnum, struct type *type, const gdb_byte *from)
Definition: i386-tdep.c:3868
static CORE_ADDR i386_follow_jump(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: i386-tdep.c:1106
static int i386_record_modrm(struct i386_record_s *irp)
Definition: i386-tdep.c:4719
static struct i386_frame_cache * i386_sigtramp_frame_cache(frame_info_ptr this_frame, void **this_cache)
Definition: i386-tdep.c:2434
static int i386_insn_is_ret(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: i386-tdep.c:780
void i386_displaced_step_fixup(struct gdbarch *gdbarch, struct displaced_step_copy_insn_closure *closure_, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: i386-tdep.c:843
static const char *const i386_bnd_names[]
Definition: i386-tdep.c:132
static int i386_epilogue_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
Definition: i386-tdep.c:2238
static int i386_svr4_sigtramp_p(frame_info_ptr this_frame)
Definition: i386-tdep.c:4087
static const char *const i386_word_names[]
Definition: i386-tdep.c:155
static int i386_16_byte_align_p(struct type *type)
Definition: i386-tdep.c:2642
static const char *const i386_register_names[]
Definition: i386-tdep.c:75
static int i386_mxcsr_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:360
static void i386_mpx_set_bounds(const char *args, int from_tty)
Definition: i386-tdep.c:9016
expr::operation_up i386_stap_parse_special_token(struct gdbarch *gdbarch, struct stap_parse_info *p)
Definition: i386-tdep.c:4409
static const struct frame_unwind i386_epilogue_frame_unwind
Definition: i386-tdep.c:2321
static expr::operation_up i386_stap_parse_special_token_triplet(struct gdbarch *gdbarch, struct stap_parse_info *p)
Definition: i386-tdep.c:4138
static const char default_struct_convention[]
Definition: i386-tdep.c:2980
void _initialize_i386_tdep()
Definition: i386-tdep.c:9070
void i386_supply_gregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *gregs, size_t len)
Definition: i386-tdep.c:3900
static int i386_in_stack_tramp_p(CORE_ADDR pc)
Definition: i386-tdep.c:2369
static const char *const i386_byte_names[]
Definition: i386-tdep.c:147
static int i386_mmx_regnum_to_fp_regnum(readable_regcache *regcache, int regnum)
Definition: i386-tdep.c:3345
static struct value * i386_pseudo_register_read_value(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum)
Definition: i386-tdep.c:3545
static int i386_insn_is_jump(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: i386-tdep.c:793
static CORE_ADDR i386_svr4_sigcontext_addr(frame_info_ptr this_frame)
Definition: i386-tdep.c:4102
static const char *const valid_conventions[]
Definition: i386-tdep.c:2983
int i386_word_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:196
int i386_zmmh_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:222
#define MPX_BT_MASK_32
Definition: i386-tdep.c:8864
static CORE_ADDR i386_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR current_pc, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1813
int i386_mpx_enabled(void)
Definition: i386-tdep.c:8852
static void i386_sigtramp_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
Definition: i386-tdep.c:2496
struct type * i386_pseudo_register_type(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:3313
#define I386_NUM_XREGS
Definition: i386-tdep.h:341
#define I386_MAX_REGISTER_SIZE
Definition: i386-tdep.h:351
@ I386_PKRU_REGNUM
Definition: i386-tdep.h:305
@ I386_EFLAGS_REGNUM
Definition: i386-tdep.h:286
@ I386_ESI_REGNUM
Definition: i386-tdep.h:283
@ I386_ST0_REGNUM
Definition: i386-tdep.h:293
@ I386_FS_REGNUM
Definition: i386-tdep.h:291
@ I386_ZMM0H_REGNUM
Definition: i386-tdep.h:303
@ I386_BND0R_REGNUM
Definition: i386-tdep.h:297
@ I386_YMM0H_REGNUM
Definition: i386-tdep.h:295
@ I386_ECX_REGNUM
Definition: i386-tdep.h:278
@ I386_GS_REGNUM
Definition: i386-tdep.h:292
@ I386_EIP_REGNUM
Definition: i386-tdep.h:285
@ I386_EBP_REGNUM
Definition: i386-tdep.h:282
@ I386_ES_REGNUM
Definition: i386-tdep.h:290
@ I386_CS_REGNUM
Definition: i386-tdep.h:287
@ I386_EAX_REGNUM
Definition: i386-tdep.h:277
@ I386_SS_REGNUM
Definition: i386-tdep.h:288
@ I386_BNDCFGU_REGNUM
Definition: i386-tdep.h:299
@ I386_EDX_REGNUM
Definition: i386-tdep.h:279
@ I386_K0_REGNUM
Definition: i386-tdep.h:301
@ I386_ESP_REGNUM
Definition: i386-tdep.h:281
@ I386_EBX_REGNUM
Definition: i386-tdep.h:280
@ I386_DS_REGNUM
Definition: i386-tdep.h:289
@ I386_EDI_REGNUM
Definition: i386-tdep.h:284
@ I386_FSBASE_REGNUM
Definition: i386-tdep.h:306
#define I386_NUM_REGS
Definition: i386-tdep.h:348
#define I386_MAX_INSN_LEN
Definition: i386-tdep.h:395
@ X86_RECORD_REAX_REGNUM
Definition: i386-tdep.h:314
@ X86_RECORD_REDX_REGNUM
Definition: i386-tdep.h:316
@ X86_RECORD_RECX_REGNUM
Definition: i386-tdep.h:315
@ X86_RECORD_SS_REGNUM
Definition: i386-tdep.h:333
@ X86_RECORD_GS_REGNUM
Definition: i386-tdep.h:337
@ X86_RECORD_REBP_REGNUM
Definition: i386-tdep.h:319
@ X86_RECORD_REBX_REGNUM
Definition: i386-tdep.h:317
@ X86_RECORD_EFLAGS_REGNUM
Definition: i386-tdep.h:331
@ X86_RECORD_CS_REGNUM
Definition: i386-tdep.h:332
@ X86_RECORD_ES_REGNUM
Definition: i386-tdep.h:335
@ X86_RECORD_REIP_REGNUM
Definition: i386-tdep.h:330
@ X86_RECORD_DS_REGNUM
Definition: i386-tdep.h:334
@ X86_RECORD_RESP_REGNUM
Definition: i386-tdep.h:318
@ X86_RECORD_RESI_REGNUM
Definition: i386-tdep.h:320
@ X86_RECORD_REDI_REGNUM
Definition: i386-tdep.h:321
@ X86_RECORD_R8_REGNUM
Definition: i386-tdep.h:322
@ X86_RECORD_FS_REGNUM
Definition: i386-tdep.h:336
#define I386_NUM_GREGS
Definition: i386-tdep.h:340
target_desc * i386_create_target_description(uint64_t xcr0, bool is_linux, bool segments)
Definition: i386.c:36
void i387_value_to_register(frame_info_ptr frame, int regnum, struct type *type, const gdb_byte *from)
Definition: i387-tdep.c:383
void i387_supply_fxsave(struct regcache *regcache, int regnum, const void *fxsave)
Definition: i387-tdep.c:589
void i387_collect_fxsave(const struct regcache *regcache, int regnum, void *fxsave)
Definition: i387-tdep.c:673
void i387_reset_bnd_regs(struct gdbarch *gdbarch, struct regcache *regcache)
Definition: i387-tdep.c:1957
int i387_convert_register_p(struct gdbarch *gdbarch, int regnum, struct type *type)
Definition: i387-tdep.c:327
void i387_supply_fsave(struct regcache *regcache, int regnum, const void *fsave)
Definition: i387-tdep.c:440
void i387_collect_fsave(const struct regcache *regcache, int regnum, void *fsave)
Definition: i387-tdep.c:495
int i387_register_to_value(frame_info_ptr frame, int regnum, struct type *type, gdb_byte *to, int *optimizedp, int *unavailablep)
Definition: i387-tdep.c:348
void i387_print_float_info(struct gdbarch *gdbarch, struct ui_file *file, frame_info_ptr frame, const char *args)
Definition: i387-tdep.c:204
#define I387_XMM0_REGNUM(tdep)
Definition: i387-tdep.h:64
#define I387_ST0_REGNUM(tdep)
Definition: i387-tdep.h:32
#define I387_YMM0_REGNUM(tdep)
Definition: i387-tdep.h:68
#define I387_XMM16_REGNUM(tdep)
Definition: i387-tdep.h:65
#define I387_NUM_MPX_REGS
Definition: i387-tdep.h:43
#define I387_BND0R_REGNUM(tdep)
Definition: i387-tdep.h:39
#define I387_NUM_BND_REGS
Definition: i387-tdep.h:44
#define I387_YMM16H_REGNUM(tdep)
Definition: i387-tdep.h:54
#define I387_SIZEOF_FSAVE
Definition: i387-tdep.h:116
#define I387_NUM_PKEYS_REGS
Definition: i387-tdep.h:47
#define I387_FSTAT_REGNUM(tdep)
Definition: i387-tdep.h:57
#define I387_FOP_REGNUM(tdep)
Definition: i387-tdep.h:63
#define I387_SIZEOF_FXSAVE
Definition: i387-tdep.h:117
#define I387_NUM_REGS
Definition: i387-tdep.h:30
#define I387_FCTRL_REGNUM(tdep)
Definition: i387-tdep.h:56
#define I387_NUM_XMM_AVX512_REGS(tdep)
Definition: i387-tdep.h:34
#define I387_MXCSR_REGNUM(tdep)
Definition: i387-tdep.h:66
#define I387_BNDCFGU_REGNUM(tdep)
Definition: i387-tdep.h:40
#define I387_MM0_REGNUM(tdep)
Definition: i387-tdep.h:35
#define I387_NUM_MPX_CTRL_REGS
Definition: i387-tdep.h:45
#define I387_PKRU_REGNUM(tdep)
Definition: i387-tdep.h:49
#define I387_FTAG_REGNUM(tdep)
Definition: i387-tdep.h:58
#define I387_NUM_XMM_REGS(tdep)
Definition: i387-tdep.h:33
#define I387_NUM_K_REGS
Definition: i387-tdep.h:46
CORE_ADDR find_function_addr(struct value *function, struct type **retval_type, struct type **function_type)
Definition: infcall.c:277
std::string displaced_step_dump_bytes(const gdb_byte *buf, size_t len)
Definition: infrun.c:1660
obj_section * maint_obj_section_from_bfd_section(bfd *abfd, asection *asection, objfile *ofile)
Definition: maint.c:330
CORE_ADDR find_solib_trampoline_target(frame_info_ptr frame, CORE_ADDR pc)
Definition: minsyms.c:1534
struct bound_minimal_symbol lookup_minimal_symbol_by_pc(CORE_ADDR pc)
Definition: minsyms.c:977
Definition: ada-exp.h:80
std::unique_ptr< operation > operation_up
Definition: expression.h:81
def info(c)
Definition: gdbarch.py:184
struct obj_section * find_pc_section(CORE_ADDR pc)
Definition: objfiles.c:1170
static int in_plt_section(CORE_ADDR pc)
Definition: objfiles.h:901
void gdbarch_register_osabi(enum bfd_architecture arch, unsigned long machine, enum gdb_osabi osabi, void(*init_osabi)(struct gdbarch_info, struct gdbarch *))
Definition: osabi.c:146
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: osabi.c:382
@ GDB_OSABI_SVR4
Definition: osabi.h:29
bool producer_is_llvm(const char *producer)
Definition: producer.c:124
bool producer_is_icc_ge_19(const char *producer)
Definition: producer.c:79
bool record_full_memory_query
Definition: record-full.c:163
int record_full_arch_list_add_reg(struct regcache *regcache, int regnum)
Definition: record-full.c:610
int record_full_arch_list_add_mem(CORE_ADDR addr, int len)
Definition: record-full.c:633
int record_full_arch_list_add_end(void)
Definition: record-full.c:664
unsigned int record_debug
Definition: record.c:33
int record_read_memory(struct gdbarch *gdbarch, CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: record.c:139
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:643
int register_size(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:170
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:790
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:671
struct regcache * get_current_regcache(void)
Definition: regcache.c:426
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:819
struct type * register_type(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:158
const reggroup *const general_reggroup
Definition: reggroups.c:251
int default_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
Definition: reggroups.c:147
const reggroup * reggroup_new(const char *name, enum reggroup_type type)
Definition: reggroups.c:34
const reggroup *const float_reggroup
Definition: reggroups.c:252
const reggroup *const all_reggroup
Definition: reggroups.c:255
void reggroup_add(struct gdbarch *gdbarch, const reggroup *group)
Definition: reggroups.c:124
const reggroup *const vector_reggroup
Definition: reggroups.c:254
@ USER_REGGROUP
Definition: reggroups.h:32
void register_remote_support_xml(const char *xml)
Definition: remote.c:5437
Definition: ax.h:82
struct minimal_symbol * minsym
Definition: minsyms.h:49
struct type * builtin_double
Definition: gdbtypes.h:2258
struct type * builtin_int8
Definition: gdbtypes.h:2281
struct type * builtin_long
Definition: gdbtypes.h:2249
struct type * builtin_data_ptr
Definition: gdbtypes.h:2303
struct type * builtin_int64
Definition: gdbtypes.h:2289
struct type * builtin_int32
Definition: gdbtypes.h:2287
struct type * builtin_half
Definition: gdbtypes.h:2256
struct type * builtin_bfloat16
Definition: gdbtypes.h:2255
struct type * builtin_int128
Definition: gdbtypes.h:2291
struct type * builtin_int16
Definition: gdbtypes.h:2283
struct type * builtin_float
Definition: gdbtypes.h:2257
bool epilogue_unwind_valid() const
Definition: symtab.h:1808
const char * producer() const
Definition: symtab.h:1753
struct type * type() const
Definition: gdbtypes.h:559
const char * linkage_name() const
Definition: symtab.h:459
LONGEST sp_offset
Definition: i386-tdep.c:1059
CORE_ADDR saved_sp
Definition: i386-tdep.c:1064
CORE_ADDR pc
Definition: i386-tdep.c:1060
CORE_ADDR base
Definition: i386-tdep.c:1057
CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]
Definition: i386-tdep.c:1063
const char *const * mpx_register_names
Definition: i386-tdep.h:178
struct type * i386_bnd_type
Definition: i386-tdep.h:245
const struct regset * fpregset
Definition: i386-tdep.h:259
int * gregset_reg_offset
Definition: i386-tdep.h:63
const char *const * zmmh_register_names
Definition: i386-tdep.h:188
struct type * i387_ext_type
Definition: i386-tdep.h:244
const char *const * k_register_names
Definition: i386-tdep.h:185
struct type * i386_mmx_type
Definition: i386-tdep.h:241
const char *const * register_names
Definition: i386-tdep.h:149
int(* sigtramp_p)(frame_info_ptr)
Definition: i386-tdep.h:226
CORE_ADDR sigtramp_end
Definition: i386-tdep.h:223
size_t sizeof_fpregset
Definition: i386-tdep.h:68
CORE_ADDR sigtramp_start
Definition: i386-tdep.h:222
const char *const * xmm_avx512_register_names
Definition: i386-tdep.h:191
gdbarch_register_reggroup_p_ftype * register_reggroup_p
Definition: i386-tdep.h:213
CORE_ADDR(* sigcontext_addr)(frame_info_ptr)
Definition: i386-tdep.h:229
const char *const * pkeys_register_names
Definition: i386-tdep.h:203
const char *const * ymmh_register_names
Definition: i386-tdep.h:156
size_t sizeof_gregset
Definition: i386-tdep.h:65
struct type * i386_zmm_type
Definition: i386-tdep.h:243
const struct target_desc * tdesc
Definition: i386-tdep.h:210
const int * record_regmap
Definition: i386-tdep.h:250
struct type * i386_ymm_type
Definition: i386-tdep.h:242
const char *const * ymm16h_register_names
Definition: i386-tdep.h:163
gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]
Definition: i386-tdep.c:1378
gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]
Definition: i386-tdep.c:1377
size_t len
Definition: i386-tdep.c:1376
struct regcache * regcache
Definition: i386-tdep.c:4699
const int * regmap
Definition: i386-tdep.c:4712
uint8_t modrm
Definition: i386-tdep.c:4705
struct gdbarch * gdbarch
Definition: i386-tdep.c:4698
CORE_ADDR orig_addr
Definition: i386-tdep.c:4700
uint8_t rex_b
Definition: i386-tdep.c:4709
CORE_ADDR addr
Definition: i386-tdep.c:4701
uint8_t mod
Definition: i386-tdep.c:4706
uint8_t rm
Definition: i386-tdep.c:4706
uint8_t rex_x
Definition: i386-tdep.c:4708
uint8_t reg
Definition: i386-tdep.c:4706
CORE_ADDR addr() const
Definition: objfiles.h:822
struct objfile * objfile
Definition: objfiles.h:838
gdb_bfd_ref_ptr obfd
Definition: objfiles.h:653
Definition: regset.h:35
const char * arg
Definition: stap-probe.h:45
const char * saved_arg
Definition: stap-probe.h:53
struct type * arg_type
Definition: stap-probe.h:59
Definition: gdbtypes.h:922
struct type * target_type() const
Definition: gdbtypes.h:1000
type_code code() const
Definition: gdbtypes.h:927
ULONGEST length() const
Definition: gdbtypes.h:954
struct field & field(int idx) const
Definition: gdbtypes.h:983
bool is_vector() const
Definition: gdbtypes.h:1149
int num_fields() const
Definition: gdbtypes.h:965
void set_name(const char *name)
Definition: gdbtypes.h:945
gdbarch * arch() const
Definition: gdbtypes.c:245
void set_is_vector(bool is_vector)
Definition: gdbtypes.h:1154
Definition: value.c:181
struct type * type
Definition: value.c:304
struct compunit_symtab * find_pc_compunit_symtab(CORE_ADDR pc)
Definition: symtab.c:2954
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
Definition: symtab.c:3956
tdesc_arch_data_up tdesc_data_alloc(void)
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
static const registry< gdbarch >::key< tdesc_arch_data > tdesc_data
void tdesc_use_registers(struct gdbarch *gdbarch, const struct target_desc *target_desc, tdesc_arch_data_up &&early_data, tdesc_unknown_register_ftype unk_reg_cb)
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
int tdesc_has_registers(const struct target_desc *target_desc)
void set_tdesc_pseudo_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *pseudo_type)
const char * tdesc_register_name(struct gdbarch *gdbarch, int regno)
struct type * tdesc_find_type(struct gdbarch *gdbarch, const char *id)
std::unique_ptr< tdesc_arch_data, tdesc_arch_data_deleter > tdesc_arch_data_up
void target_float_convert(const gdb_byte *from, const struct type *from_type, gdb_byte *to, const struct type *to_type)
int target_get_min_fast_tracepoint_insn_len()
Definition: target.c:728
int target_read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1830
int target_write_memory(CORE_ADDR memaddr, const gdb_byte *myaddr, ssize_t len)
Definition: target.c:1847
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1771
#define current_uiout
Definition: ui-out.h:40
int user_reg_map_name_to_regnum(struct gdbarch *gdbarch, const char *name, int len)
Definition: user-regs.c:132
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: utils.c:3114
int yquery(const char *ctlstr,...)
Definition: utils.c:993
void gdb_printf(struct ui_file *stream, const char *format,...)
Definition: utils.c:1865
#define gdb_stderr
Definition: utils.h:193
#define gdb_stdlog
Definition: utils.h:196
struct type * value_type(const struct value *value)
Definition: value.c:1109
gdb::array_view< const gdb_byte > value_contents_all(struct value *value)
Definition: value.c:1284
struct value * allocate_value(struct type *type)
Definition: value.c:1053
CORE_ADDR value_as_address(struct value *val)
Definition: value.c:2804
void mark_value_bytes_unavailable(struct value *value, LONGEST offset, LONGEST length)
Definition: value.c:635
gdb::array_view< gdb_byte > value_contents_raw(struct value *value)
Definition: value.c:1167
struct type * value_enclosing_type(const struct value *value)
Definition: value.c:1189
#define VALUE_LVAL(val)
Definition: value.h:438
#define VALUE_REGNUM(val)
Definition: value.h:469
static void check(BOOL ok, const char *file, int line)
Definition: windows-nat.c:392
bool x86_in_indirect_branch_thunk(CORE_ADDR pc, const char *const *register_names, int lo, int hi)
Definition: x86-tdep.c:43