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/tmp/gdb-13.1/gdb/riscv-tdep.c
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1/* Target-dependent code for the RISC-V architecture, for GDB.
2
3 Copyright (C) 2018-2023 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "frame.h"
22#include "inferior.h"
23#include "symtab.h"
24#include "value.h"
25#include "gdbcmd.h"
26#include "language.h"
27#include "gdbcore.h"
28#include "symfile.h"
29#include "objfiles.h"
30#include "gdbtypes.h"
31#include "target.h"
32#include "arch-utils.h"
33#include "regcache.h"
34#include "osabi.h"
35#include "riscv-tdep.h"
36#include "block.h"
37#include "reggroups.h"
38#include "opcode/riscv.h"
39#include "elf/riscv.h"
40#include "elf-bfd.h"
41#include "symcat.h"
42#include "dis-asm.h"
43#include "frame-unwind.h"
44#include "frame-base.h"
45#include "trad-frame.h"
46#include "infcall.h"
47#include "floatformat.h"
48#include "remote.h"
49#include "target-descriptions.h"
50#include "dwarf2/frame.h"
51#include "user-regs.h"
52#include "valprint.h"
53#include "gdbsupport/common-defs.h"
54#include "opcode/riscv-opc.h"
55#include "cli/cli-decode.h"
56#include "observable.h"
57#include "prologue-value.h"
58#include "arch/riscv.h"
60
61/* The stack must be 16-byte aligned. */
62#define SP_ALIGNMENT 16
63
64/* The biggest alignment that the target supports. */
65#define BIGGEST_ALIGNMENT 16
66
67/* Define a series of is_XXX_insn functions to check if the value INSN
68 is an instance of instruction XXX. */
69#define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
70static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71{ \
72 return (insn & INSN_MASK) == INSN_MATCH; \
73}
74#include "opcode/riscv-opc.h"
75#undef DECLARE_INSN
76
77/* When this is set to non-zero debugging information about breakpoint
78 kinds will be printed. */
79
80static unsigned int riscv_debug_breakpoints = 0;
81
82/* When this is set to non-zero debugging information about inferior calls
83 will be printed. */
84
85static unsigned int riscv_debug_infcall = 0;
86
87/* When this is set to non-zero debugging information about stack unwinding
88 will be printed. */
89
90static unsigned int riscv_debug_unwinder = 0;
91
92/* When this is set to non-zero debugging information about gdbarch
93 initialisation will be printed. */
94
95static unsigned int riscv_debug_gdbarch = 0;
96
97/* The names of the RISC-V target description features. */
98const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr";
99static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu";
100static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu";
101static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual";
102static const char *riscv_feature_name_vector = "org.gnu.gdb.riscv.vector";
103
104/* The current set of options to be passed to the disassembler. */
106
107/* Cached information about a frame. */
108
110{
111 /* The register from which we can calculate the frame base. This is
112 usually $sp or $fp. */
114
115 /* The offset from the current value in register FRAME_BASE_REG to the
116 actual frame base address. */
118
119 /* Information about previous register values. */
121
122 /* The id for this frame. */
124
125 /* The base (stack) address for this frame. This is the stack pointer
126 value on entry to this frame before any adjustments are made. */
127 CORE_ADDR frame_base;
128};
129
130/* RISC-V specific register group for CSRs. */
131
132static const reggroup *csr_reggroup = nullptr;
133
134/* Callback function for user_reg_add. */
135
136static struct value *
137value_of_riscv_user_reg (frame_info_ptr frame, const void *baton)
138{
139 const int *reg_p = (const int *) baton;
140 return value_of_register (*reg_p, frame);
141}
142
143/* Information about a register alias that needs to be set up for this
144 target. These are collected when the target's XML description is
145 analysed, and then processed later, once the gdbarch has been created. */
146
148{
149public:
150 /* Constructor. */
151
152 riscv_pending_register_alias (const char *name, const void *baton)
153 : m_name (name),
154 m_baton (baton)
155 { /* Nothing. */ }
156
157 /* Convert this into a user register for GDBARCH. */
158
159 void create (struct gdbarch *gdbarch) const
160 {
162 }
163
164private:
165 /* The name for this alias. */
166 const char *m_name;
167
168 /* The baton value for passing to user_reg_add. This must point to some
169 data that will live for at least as long as the gdbarch object to
170 which the user register is attached. */
171 const void *m_baton;
172};
173
174/* A set of registers that we expect to find in a tdesc_feature. These
175 are use in RISCV_GDBARCH_INIT when processing the target description. */
176
178{
179 explicit riscv_register_feature (const char *feature_name)
180 : m_feature_name (feature_name)
181 { /* Delete. */ }
182
185
186 /* Information for a single register. */
188 {
189 /* The GDB register number for this register. */
191
192 /* List of names for this register. The first name in this list is the
193 preferred name, the name GDB should use when describing this
194 register. */
195 std::vector<const char *> names;
196
197 /* Look in FEATURE for a register with a name from this classes names
198 list. If the register is found then register its number with
199 TDESC_DATA and add all its aliases to the ALIASES list.
200 PREFER_FIRST_NAME_P is used when deciding which aliases to create. */
201 bool check (struct tdesc_arch_data *tdesc_data,
202 const struct tdesc_feature *feature,
203 bool prefer_first_name_p,
204 std::vector<riscv_pending_register_alias> *aliases) const;
205 };
206
207 /* Return the name of this feature. */
208 const char *name () const
209 { return m_feature_name; }
210
211protected:
212
213 /* Return a target description feature extracted from TDESC for this
214 register feature. Will return nullptr if there is no feature in TDESC
215 with the name M_FEATURE_NAME. */
216 const struct tdesc_feature *tdesc_feature (const struct target_desc *tdesc) const
217 {
218 return tdesc_find_feature (tdesc, name ());
219 }
220
221 /* List of all the registers that we expect that we might find in this
222 register set. */
223 std::vector<struct register_info> m_registers;
224
225private:
226
227 /* The name for this feature. This is the name used to find this feature
228 within the target description. */
229 const char *m_feature_name;
230};
231
232/* See description in the class declaration above. */
233
234bool
237 const struct tdesc_feature *feature,
238 bool prefer_first_name_p,
239 std::vector<riscv_pending_register_alias> *aliases) const
240{
241 for (const char *name : this->names)
242 {
243 bool found = tdesc_numbered_register (feature, tdesc_data,
244 this->regnum, name);
245 if (found)
246 {
247 /* We know that the target description mentions this
248 register. In RISCV_REGISTER_NAME we ensure that GDB
249 always uses the first name for each register, so here we
250 add aliases for all of the remaining names. */
251 int start_index = prefer_first_name_p ? 1 : 0;
252 for (int i = start_index; i < this->names.size (); ++i)
253 {
254 const char *alias = this->names[i];
255 if (alias == name && !prefer_first_name_p)
256 continue;
257 aliases->emplace_back (alias, (void *) &this->regnum);
258 }
259 return true;
260 }
261 }
262 return false;
263}
264
265/* Class representing the x-registers feature set. */
266
268{
271 {
272 m_registers = {
273 { RISCV_ZERO_REGNUM + 0, { "zero", "x0" } },
274 { RISCV_ZERO_REGNUM + 1, { "ra", "x1" } },
275 { RISCV_ZERO_REGNUM + 2, { "sp", "x2" } },
276 { RISCV_ZERO_REGNUM + 3, { "gp", "x3" } },
277 { RISCV_ZERO_REGNUM + 4, { "tp", "x4" } },
278 { RISCV_ZERO_REGNUM + 5, { "t0", "x5" } },
279 { RISCV_ZERO_REGNUM + 6, { "t1", "x6" } },
280 { RISCV_ZERO_REGNUM + 7, { "t2", "x7" } },
281 { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" } },
282 { RISCV_ZERO_REGNUM + 9, { "s1", "x9" } },
283 { RISCV_ZERO_REGNUM + 10, { "a0", "x10" } },
284 { RISCV_ZERO_REGNUM + 11, { "a1", "x11" } },
285 { RISCV_ZERO_REGNUM + 12, { "a2", "x12" } },
286 { RISCV_ZERO_REGNUM + 13, { "a3", "x13" } },
287 { RISCV_ZERO_REGNUM + 14, { "a4", "x14" } },
288 { RISCV_ZERO_REGNUM + 15, { "a5", "x15" } },
289 { RISCV_ZERO_REGNUM + 16, { "a6", "x16" } },
290 { RISCV_ZERO_REGNUM + 17, { "a7", "x17" } },
291 { RISCV_ZERO_REGNUM + 18, { "s2", "x18" } },
292 { RISCV_ZERO_REGNUM + 19, { "s3", "x19" } },
293 { RISCV_ZERO_REGNUM + 20, { "s4", "x20" } },
294 { RISCV_ZERO_REGNUM + 21, { "s5", "x21" } },
295 { RISCV_ZERO_REGNUM + 22, { "s6", "x22" } },
296 { RISCV_ZERO_REGNUM + 23, { "s7", "x23" } },
297 { RISCV_ZERO_REGNUM + 24, { "s8", "x24" } },
298 { RISCV_ZERO_REGNUM + 25, { "s9", "x25" } },
299 { RISCV_ZERO_REGNUM + 26, { "s10", "x26" } },
300 { RISCV_ZERO_REGNUM + 27, { "s11", "x27" } },
301 { RISCV_ZERO_REGNUM + 28, { "t3", "x28" } },
302 { RISCV_ZERO_REGNUM + 29, { "t4", "x29" } },
303 { RISCV_ZERO_REGNUM + 30, { "t5", "x30" } },
304 { RISCV_ZERO_REGNUM + 31, { "t6", "x31" } },
305 { RISCV_ZERO_REGNUM + 32, { "pc" } }
306 };
307 }
308
309 /* Return the preferred name for the register with gdb register number
310 REGNUM, which must be in the inclusive range RISCV_ZERO_REGNUM to
311 RISCV_PC_REGNUM. */
312 const char *register_name (int regnum) const
313 {
314 gdb_assert (regnum >= RISCV_ZERO_REGNUM && regnum <= m_registers.size ());
315 return m_registers[regnum].names[0];
316 }
317
318 /* Check this feature within TDESC, record the registers from this
319 feature into TDESC_DATA and update ALIASES and FEATURES. */
320 bool check (const struct target_desc *tdesc,
322 std::vector<riscv_pending_register_alias> *aliases,
323 struct riscv_gdbarch_features *features) const
324 {
325 const struct tdesc_feature *feature_cpu = tdesc_feature (tdesc);
326
327 if (feature_cpu == nullptr)
328 return false;
329
330 bool seen_an_optional_reg_p = false;
331 for (const auto &reg : m_registers)
332 {
333 bool found = reg.check (tdesc_data, feature_cpu, true, aliases);
334
335 bool is_optional_reg_p = (reg.regnum >= RISCV_ZERO_REGNUM + 16
336 && reg.regnum < RISCV_ZERO_REGNUM + 32);
337
338 if (!found && (!is_optional_reg_p || seen_an_optional_reg_p))
339 return false;
340 else if (found && is_optional_reg_p)
341 seen_an_optional_reg_p = true;
342 }
343
344 /* Check that all of the core cpu registers have the same bitsize. */
345 int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc");
346
347 bool valid_p = true;
348 for (auto &tdesc_reg : feature_cpu->registers)
349 valid_p &= (tdesc_reg->bitsize == xlen_bitsize);
350
351 features->xlen = (xlen_bitsize / 8);
352 features->embedded = !seen_an_optional_reg_p;
353
354 return valid_p;
355 }
356};
357
358/* An instance of the x-register feature set. */
359
361
362/* Class representing the f-registers feature set. */
363
365{
368 {
369 m_registers = {
370 { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" } },
371 { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" } },
372 { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" } },
373 { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" } },
374 { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" } },
375 { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" } },
376 { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" } },
377 { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" } },
378 { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" } },
379 { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" } },
380 { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" } },
381 { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" } },
382 { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" } },
383 { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" } },
384 { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" } },
385 { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" } },
386 { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" } },
387 { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" } },
388 { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" } },
389 { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" } },
390 { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" } },
391 { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" } },
392 { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" } },
393 { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" } },
394 { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" } },
395 { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" } },
396 { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" } },
397 { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" } },
398 { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" } },
399 { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" } },
400 { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" } },
401 { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" } },
402 { RISCV_CSR_FFLAGS_REGNUM, { "fflags", "csr1" } },
403 { RISCV_CSR_FRM_REGNUM, { "frm", "csr2" } },
404 { RISCV_CSR_FCSR_REGNUM, { "fcsr", "csr3" } },
405 };
406 }
407
408 /* Return the preferred name for the register with gdb register number
409 REGNUM, which must be in the inclusive range RISCV_FIRST_FP_REGNUM to
410 RISCV_LAST_FP_REGNUM. */
411 const char *register_name (int regnum) const
412 {
414 gdb_assert (regnum >= RISCV_FIRST_FP_REGNUM
417 return m_registers[regnum].names[0];
418 }
419
420 /* Check this feature within TDESC, record the registers from this
421 feature into TDESC_DATA and update ALIASES and FEATURES. */
422 bool check (const struct target_desc *tdesc,
424 std::vector<riscv_pending_register_alias> *aliases,
425 struct riscv_gdbarch_features *features) const
426 {
427 const struct tdesc_feature *feature_fpu = tdesc_feature (tdesc);
428
429 /* It's fine if this feature is missing. Update the architecture
430 feature set and return. */
431 if (feature_fpu == nullptr)
432 {
433 features->flen = 0;
434 return true;
435 }
436
437 /* Check all of the floating pointer registers are present. We also
438 check that the floating point CSRs are present too, though if these
439 are missing this is not fatal. */
440 for (const auto &reg : m_registers)
441 {
442 bool found = reg.check (tdesc_data, feature_fpu, true, aliases);
443
444 bool is_ctrl_reg_p = reg.regnum > RISCV_LAST_FP_REGNUM;
445
446 if (!found && !is_ctrl_reg_p)
447 return false;
448 }
449
450 /* Look through all of the floating point registers (not the FP CSRs
451 though), and check they all have the same bitsize. Use this bitsize
452 to update the feature set for this gdbarch. */
453 int fp_bitsize = -1;
454 for (const auto &reg : m_registers)
455 {
456 /* Stop once we get to the CSRs which are at the end of the
457 M_REGISTERS list. */
458 if (reg.regnum > RISCV_LAST_FP_REGNUM)
459 break;
460
461 int reg_bitsize = -1;
462 for (const char *name : reg.names)
463 {
464 if (tdesc_unnumbered_register (feature_fpu, name))
465 {
466 reg_bitsize = tdesc_register_bitsize (feature_fpu, name);
467 break;
468 }
469 }
470 gdb_assert (reg_bitsize != -1);
471 if (fp_bitsize == -1)
472 fp_bitsize = reg_bitsize;
473 else if (fp_bitsize != reg_bitsize)
474 return false;
475 }
476
477 features->flen = (fp_bitsize / 8);
478 return true;
479 }
480};
481
482/* An instance of the f-register feature set. */
483
485
486/* Class representing the virtual registers. These are not physical
487 registers on the hardware, but might be available from the target.
488 These are not pseudo registers, reading these really does result in a
489 register read from the target, it is just that there might not be a
490 physical register backing the result. */
491
493{
496 {
497 m_registers = {
498 { RISCV_PRIV_REGNUM, { "priv" } }
499 };
500 }
501
502 bool check (const struct target_desc *tdesc,
504 std::vector<riscv_pending_register_alias> *aliases,
505 struct riscv_gdbarch_features *features) const
506 {
507 const struct tdesc_feature *feature_virtual = tdesc_feature (tdesc);
508
509 /* It's fine if this feature is missing. */
510 if (feature_virtual == nullptr)
511 return true;
512
513 /* We don't check the return value from the call to check here, all the
514 registers in this feature are optional. */
515 for (const auto &reg : m_registers)
516 reg.check (tdesc_data, feature_virtual, true, aliases);
517
518 return true;
519 }
520};
521
522/* An instance of the virtual register feature. */
523
525
526/* Class representing the CSR feature. */
527
529{
532 {
533 m_registers = {
534#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
535 { RISCV_ ## VALUE ## _REGNUM, { # NAME } },
536#include "opcode/riscv-opc.h"
537#undef DECLARE_CSR
538 };
539 riscv_create_csr_aliases ();
540 }
541
542 bool check (const struct target_desc *tdesc,
544 std::vector<riscv_pending_register_alias> *aliases,
545 struct riscv_gdbarch_features *features) const
546 {
547 const struct tdesc_feature *feature_csr = tdesc_feature (tdesc);
548
549 /* It's fine if this feature is missing. */
550 if (feature_csr == nullptr)
551 return true;
552
553 /* We don't check the return value from the call to check here, all the
554 registers in this feature are optional. */
555 for (const auto &reg : m_registers)
556 reg.check (tdesc_data, feature_csr, true, aliases);
557
558 return true;
559 }
560
561private:
562
563 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
564 to the name list for each register. */
565
566 void
568 {
569 for (auto &reg : m_registers)
570 {
571 int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
572 gdb::unique_xmalloc_ptr<char> alias = xstrprintf ("csr%d", csr_num);
573 reg.names.push_back (alias.release ());
574 }
575 }
576};
577
578/* An instance of the csr register feature. */
579
581
582/* Class representing the v-registers feature set. */
583
585{
588 {
589 m_registers = {
590 { RISCV_V0_REGNUM + 0, { "v0" } },
591 { RISCV_V0_REGNUM + 1, { "v1" } },
592 { RISCV_V0_REGNUM + 2, { "v2" } },
593 { RISCV_V0_REGNUM + 3, { "v3" } },
594 { RISCV_V0_REGNUM + 4, { "v4" } },
595 { RISCV_V0_REGNUM + 5, { "v5" } },
596 { RISCV_V0_REGNUM + 6, { "v6" } },
597 { RISCV_V0_REGNUM + 7, { "v7" } },
598 { RISCV_V0_REGNUM + 8, { "v8" } },
599 { RISCV_V0_REGNUM + 9, { "v9" } },
600 { RISCV_V0_REGNUM + 10, { "v10" } },
601 { RISCV_V0_REGNUM + 11, { "v11" } },
602 { RISCV_V0_REGNUM + 12, { "v12" } },
603 { RISCV_V0_REGNUM + 13, { "v13" } },
604 { RISCV_V0_REGNUM + 14, { "v14" } },
605 { RISCV_V0_REGNUM + 15, { "v15" } },
606 { RISCV_V0_REGNUM + 16, { "v16" } },
607 { RISCV_V0_REGNUM + 17, { "v17" } },
608 { RISCV_V0_REGNUM + 18, { "v18" } },
609 { RISCV_V0_REGNUM + 19, { "v19" } },
610 { RISCV_V0_REGNUM + 20, { "v20" } },
611 { RISCV_V0_REGNUM + 21, { "v21" } },
612 { RISCV_V0_REGNUM + 22, { "v22" } },
613 { RISCV_V0_REGNUM + 23, { "v23" } },
614 { RISCV_V0_REGNUM + 24, { "v24" } },
615 { RISCV_V0_REGNUM + 25, { "v25" } },
616 { RISCV_V0_REGNUM + 26, { "v26" } },
617 { RISCV_V0_REGNUM + 27, { "v27" } },
618 { RISCV_V0_REGNUM + 28, { "v28" } },
619 { RISCV_V0_REGNUM + 29, { "v29" } },
620 { RISCV_V0_REGNUM + 30, { "v30" } },
621 { RISCV_V0_REGNUM + 31, { "v31" } },
622 };
623 }
624
625 /* Return the preferred name for the register with gdb register number
626 REGNUM, which must be in the inclusive range RISCV_V0_REGNUM to
627 RISCV_V0_REGNUM + 31. */
628 const char *register_name (int regnum) const
629 {
630 gdb_assert (regnum >= RISCV_V0_REGNUM
631 && regnum <= RISCV_V0_REGNUM + 31);
633 return m_registers[regnum].names[0];
634 }
635
636 /* Check this feature within TDESC, record the registers from this
637 feature into TDESC_DATA and update ALIASES and FEATURES. */
638 bool check (const struct target_desc *tdesc,
640 std::vector<riscv_pending_register_alias> *aliases,
641 struct riscv_gdbarch_features *features) const
642 {
643 const struct tdesc_feature *feature_vector = tdesc_feature (tdesc);
644
645 /* It's fine if this feature is missing. Update the architecture
646 feature set and return. */
647 if (feature_vector == nullptr)
648 {
649 features->vlen = 0;
650 return true;
651 }
652
653 /* Check all of the vector registers are present. */
654 for (const auto &reg : m_registers)
655 {
656 if (!reg.check (tdesc_data, feature_vector, true, aliases))
657 return false;
658 }
659
660 /* Look through all of the vector registers and check they all have the
661 same bitsize. Use this bitsize to update the feature set for this
662 gdbarch. */
663 int vector_bitsize = -1;
664 for (const auto &reg : m_registers)
665 {
666 int reg_bitsize = -1;
667 for (const char *name : reg.names)
668 {
669 if (tdesc_unnumbered_register (feature_vector, name))
670 {
671 reg_bitsize = tdesc_register_bitsize (feature_vector, name);
672 break;
673 }
674 }
675 gdb_assert (reg_bitsize != -1);
676 if (vector_bitsize == -1)
677 vector_bitsize = reg_bitsize;
678 else if (vector_bitsize != reg_bitsize)
679 return false;
680 }
681
682 features->vlen = (vector_bitsize / 8);
683 return true;
684 }
685};
686
687/* An instance of the v-register feature set. */
688
690
691/* Controls whether we place compressed breakpoints or not. When in auto
692 mode GDB tries to determine if the target supports compressed
693 breakpoints, and uses them if it does. */
694
696
697/* The show callback for 'show riscv use-compressed-breakpoints'. */
698
699static void
700show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
701 struct cmd_list_element *c,
702 const char *value)
703{
704 gdb_printf (file,
705 _("Debugger's use of compressed breakpoints is set "
706 "to %s.\n"), value);
707}
708
709/* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
710
711static struct cmd_list_element *setriscvcmdlist = NULL;
712static struct cmd_list_element *showriscvcmdlist = NULL;
713
714/* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
715
718
719/* The show callback for all 'show debug riscv VARNAME' variables. */
720
721static void
722show_riscv_debug_variable (struct ui_file *file, int from_tty,
723 struct cmd_list_element *c,
724 const char *value)
725{
726 gdb_printf (file,
727 _("RiscV debug variable `%s' is set to: %s\n"),
728 c->name, value);
729}
730
731/* See riscv-tdep.h. */
732
733int
735{
736 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
737 return tdep->isa_features.xlen;
738}
739
740/* See riscv-tdep.h. */
741
742int
744{
745 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
746 return tdep->abi_features.xlen;
747}
748
749/* See riscv-tdep.h. */
750
751int
753{
754 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
755 return tdep->isa_features.flen;
756}
757
758/* See riscv-tdep.h. */
759
760int
762{
763 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
764 return tdep->abi_features.flen;
765}
766
767/* See riscv-tdep.h. */
768
769bool
771{
772 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
773 return tdep->abi_features.embedded;
774}
775
776/* Return true if the target for GDBARCH has floating point hardware. */
777
778static bool
780{
781 return (riscv_isa_flen (gdbarch) > 0);
782}
783
784/* Return true if GDBARCH is using any of the floating point hardware ABIs. */
785
786static bool
788{
789 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
790 return tdep->abi_features.flen > 0;
791}
792
793/* Return true if REGNO is a floating pointer register. */
794
795static bool
797{
798 return (regno >= RISCV_FIRST_FP_REGNUM
799 && regno <= RISCV_LAST_FP_REGNUM);
800}
801
802/* Implement the breakpoint_kind_from_pc gdbarch method. */
803
804static int
806{
808 {
809 bool unaligned_p = false;
810 gdb_byte buf[1];
811
812 /* Some targets don't support unaligned reads. The address can only
813 be unaligned if the C extension is supported. So it is safe to
814 use a compressed breakpoint in this case. */
815 if (*pcptr & 0x2)
816 unaligned_p = true;
817 else
818 {
819 /* Read the opcode byte to determine the instruction length. If
820 the read fails this may be because we tried to set the
821 breakpoint at an invalid address, in this case we provide a
822 fake result which will give a breakpoint length of 4.
823 Hopefully when we try to actually insert the breakpoint we
824 will see a failure then too which will be reported to the
825 user. */
826 if (target_read_code (*pcptr, buf, 1) == -1)
827 buf[0] = 0;
828 }
829
831 {
832 const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
833 ? "C.EBREAK" : "EBREAK");
834
835 gdb_printf (gdb_stdlog, "Using %s for breakpoint at %s ",
836 bp, paddress (gdbarch, *pcptr));
837 if (unaligned_p)
838 gdb_printf (gdb_stdlog, "(unaligned address)\n");
839 else
840 gdb_printf (gdb_stdlog, "(instruction length %d)\n",
841 riscv_insn_length (buf[0]));
842 }
843 if (unaligned_p || riscv_insn_length (buf[0]) == 2)
844 return 2;
845 else
846 return 4;
847 }
849 return 2;
850 else
851 return 4;
852}
853
854/* Implement the sw_breakpoint_from_kind gdbarch method. */
855
856static const gdb_byte *
858{
859 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
860 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
861
862 *size = kind;
863 switch (kind)
864 {
865 case 2:
866 return c_ebreak;
867 case 4:
868 return ebreak;
869 default:
870 gdb_assert_not_reached ("unhandled breakpoint kind");
871 }
872}
873
874/* Implement the register_name gdbarch method. This is used instead of
875 the function supplied by calling TDESC_USE_REGISTERS so that we can
876 ensure the preferred names are offered for x-regs and f-regs. */
877
878static const char *
880{
881 /* Lookup the name through the target description. If we get back NULL
882 then this is an unknown register. If we do get a name back then we
883 look up the registers preferred name below. */
884 const char *name = tdesc_register_name (gdbarch, regnum);
885 gdb_assert (name != nullptr);
886 if (name[0] == '\0')
887 return name;
888
889 /* We want GDB to use the ABI names for registers even if the target
890 gives us a target description with the architectural name. For
891 example we want to see 'ra' instead of 'x1' whatever the target
892 description called it. */
895
896 /* Like with the x-regs we prefer the abi names for the floating point
897 registers. If the target doesn't have floating point registers then
898 the tdesc_register_name call above should have returned an empty
899 string. */
901 {
902 gdb_assert (riscv_has_fp_regs (gdbarch));
904 }
905
906 /* Some targets (QEMU) are reporting these three registers twice, once
907 in the FPU feature, and once in the CSR feature. Both of these read
908 the same underlying state inside the target, but naming the register
909 twice in the target description results in GDB having two registers
910 with the same name, only one of which can ever be accessed, but both
911 will show up in 'info register all'. Unless, we identify the
912 duplicate copies of these registers (in riscv_tdesc_unknown_reg) and
913 then hide the registers here by giving them no name. */
914 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
916 || tdep->duplicate_frm_regnum == regnum
917 || tdep->duplicate_fcsr_regnum == regnum)
918 return "";
919
920 /* The remaining registers are different. For all other registers on the
921 machine we prefer to see the names that the target description
922 provides. This is particularly important for CSRs which might be
923 renamed over time. If GDB keeps track of the "latest" name, but a
924 particular target provides an older name then we don't want to force
925 users to see the newer name in register output.
926
927 The other case that reaches here are any registers that the target
928 provided that GDB is completely unaware of. For these we have no
929 choice but to accept the target description name.
930
931 Just accept whatever name TDESC_REGISTER_NAME returned. */
932 return name;
933}
934
935/* Implement gdbarch_pseudo_register_read. Read pseudo-register REGNUM
936 from REGCACHE and place the register value into BUF. BUF is sized
937 based on the type of register REGNUM, all of BUF should be written too,
938 the result should be sign or zero extended as appropriate. */
939
940static enum register_status
943 int regnum, gdb_byte *buf)
944{
945 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
946
947 if (regnum == tdep->fflags_regnum || regnum == tdep->frm_regnum)
948 {
949 /* Clear BUF. */
950 memset (buf, 0, register_size (gdbarch, regnum));
951
952 /* Read the first byte of the fcsr register, this contains both frm
953 and fflags. */
954 enum register_status status
955 = regcache->raw_read_part (RISCV_CSR_FCSR_REGNUM, 0, 1, buf);
956
957 if (status != REG_VALID)
958 return status;
959
960 /* Extract the appropriate parts. */
961 if (regnum == tdep->fflags_regnum)
962 buf[0] &= 0x1f;
963 else if (regnum == tdep->frm_regnum)
964 buf[0] = (buf[0] >> 5) & 0x7;
965
966 return REG_VALID;
967 }
968
969 return REG_UNKNOWN;
970}
971
972/* Implement gdbarch_pseudo_register_write. Write the contents of BUF into
973 pseudo-register REGNUM in REGCACHE. BUF is sized based on the type of
974 register REGNUM. */
975
976static void
978 struct regcache *regcache, int regnum,
979 const gdb_byte *buf)
980{
981 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
982
983 if (regnum == tdep->fflags_regnum || regnum == tdep->frm_regnum)
984 {
985 int fcsr_regnum = RISCV_CSR_FCSR_REGNUM;
986 gdb_byte raw_buf[register_size (gdbarch, fcsr_regnum)];
987
988 regcache->raw_read (fcsr_regnum, raw_buf);
989
990 if (regnum == tdep->fflags_regnum)
991 raw_buf[0] = (raw_buf[0] & ~0x1f) | (buf[0] & 0x1f);
992 else if (regnum == tdep->frm_regnum)
993 raw_buf[0] = (raw_buf[0] & ~(0x7 << 5)) | ((buf[0] & 0x7) << 5);
994
995 regcache->raw_write (fcsr_regnum, raw_buf);
996 }
997 else
998 gdb_assert_not_reached ("unknown pseudo register %d", regnum);
999}
1000
1001/* Implement the cannot_store_register gdbarch method. The zero register
1002 (x0) is read-only on RISC-V. */
1003
1004static int
1006{
1007 return regnum == RISCV_ZERO_REGNUM;
1008}
1009
1010/* Construct a type for 64-bit FP registers. */
1011
1012static struct type *
1014{
1015 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
1016
1017 if (tdep->riscv_fpreg_d_type == nullptr)
1018 {
1019 const struct builtin_type *bt = builtin_type (gdbarch);
1020
1021 /* The type we're building is this: */
1022#if 0
1023 union __gdb_builtin_type_fpreg_d
1024 {
1025 float f;
1026 double d;
1027 };
1028#endif
1029
1030 struct type *t;
1031
1033 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
1036 t->set_is_vector (true);
1037 t->set_name ("builtin_type_fpreg_d");
1038 tdep->riscv_fpreg_d_type = t;
1039 }
1040
1041 return tdep->riscv_fpreg_d_type;
1042}
1043
1044/* Implement the register_type gdbarch method. This is installed as an
1045 for the override setup by TDESC_USE_REGISTERS, for most registers we
1046 delegate the type choice to the target description, but for a few
1047 registers we try to improve the types if the target description has
1048 taken a simplistic approach. */
1049
1050static struct type *
1052{
1054 int xlen = riscv_isa_xlen (gdbarch);
1055
1056 /* We want to perform some specific type "fixes" in cases where we feel
1057 that we really can do better than the target description. For all
1058 other cases we just return what the target description says. */
1060 {
1061 /* This spots the case for RV64 where the double is defined as
1062 either 'ieee_double' or 'float' (which is the generic name that
1063 converts to 'double' on 64-bit). In these cases its better to
1064 present the registers using a union type. */
1065 int flen = riscv_isa_flen (gdbarch);
1066 if (flen == 8
1067 && type->code () == TYPE_CODE_FLT
1068 && type->length () == flen
1069 && (strcmp (type->name (), "builtin_type_ieee_double") == 0
1070 || strcmp (type->name (), "double") == 0))
1072 }
1073
1079 || regnum == RISCV_TP_REGNUM)
1080 && type->code () == TYPE_CODE_INT
1081 && type->length () == xlen)
1082 {
1083 /* This spots the case where some interesting registers are defined
1084 as simple integers of the expected size, we force these registers
1085 to be pointers as we believe that is more useful. */
1087 || regnum == RISCV_RA_REGNUM)
1089 else if (regnum == RISCV_FP_REGNUM
1092 || regnum == RISCV_TP_REGNUM)
1094 }
1095
1096 return type;
1097}
1098
1099/* Helper for riscv_print_registers_info, prints info for a single register
1100 REGNUM. */
1101
1102static void
1104 struct ui_file *file,
1105 frame_info_ptr frame,
1106 int regnum)
1107{
1108 const char *name = gdbarch_register_name (gdbarch, regnum);
1109 struct value *val;
1110 struct type *regtype;
1111 int print_raw_format;
1112 enum tab_stops { value_column_1 = 15 };
1113
1114 gdb_puts (name, file);
1115 print_spaces (value_column_1 - strlen (name), file);
1116
1117 try
1118 {
1119 val = value_of_register (regnum, frame);
1120 regtype = value_type (val);
1121 }
1122 catch (const gdb_exception_error &ex)
1123 {
1124 /* Handle failure to read a register without interrupting the entire
1125 'info registers' flow. */
1126 gdb_printf (file, "%s\n", ex.what ());
1127 return;
1128 }
1129
1130 print_raw_format = (value_entirely_available (val)
1131 && !value_optimized_out (val));
1132
1133 if (regtype->code () == TYPE_CODE_FLT
1134 || (regtype->code () == TYPE_CODE_UNION
1135 && regtype->num_fields () == 2
1136 && regtype->field (0).type ()->code () == TYPE_CODE_FLT
1137 && regtype->field (1).type ()->code () == TYPE_CODE_FLT)
1138 || (regtype->code () == TYPE_CODE_UNION
1139 && regtype->num_fields () == 3
1140 && regtype->field (0).type ()->code () == TYPE_CODE_FLT
1141 && regtype->field (1).type ()->code () == TYPE_CODE_FLT
1142 && regtype->field (2).type ()->code () == TYPE_CODE_FLT))
1143 {
1144 struct value_print_options opts;
1145 const gdb_byte *valaddr = value_contents_for_printing (val).data ();
1146 enum bfd_endian byte_order = type_byte_order (regtype);
1147
1148 get_user_print_options (&opts);
1149 opts.deref_ref = 1;
1150
1151 common_val_print (val, file, 0, &opts, current_language);
1152
1153 if (print_raw_format)
1154 {
1155 gdb_printf (file, "\t(raw ");
1156 print_hex_chars (file, valaddr, regtype->length (), byte_order,
1157 true);
1158 gdb_printf (file, ")");
1159 }
1160 }
1161 else
1162 {
1163 struct value_print_options opts;
1164 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
1165
1166 /* Print the register in hex. */
1167 get_formatted_print_options (&opts, 'x');
1168 opts.deref_ref = 1;
1169 common_val_print (val, file, 0, &opts, current_language);
1170
1171 if (print_raw_format)
1172 {
1173 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
1174 {
1175 LONGEST d;
1177 unsigned xlen;
1178
1179 /* The SD field is always in the upper bit of MSTATUS, regardless
1180 of the number of bits in MSTATUS. */
1181 d = value_as_long (val);
1182 xlen = size * 8;
1183 gdb_printf (file,
1184 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
1185 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
1186 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
1187 (int) ((d >> (xlen - 1)) & 0x1),
1188 (int) ((d >> 24) & 0x1f),
1189 (int) ((d >> 19) & 0x1),
1190 (int) ((d >> 18) & 0x1),
1191 (int) ((d >> 17) & 0x1),
1192 (int) ((d >> 15) & 0x3),
1193 (int) ((d >> 13) & 0x3),
1194 (int) ((d >> 11) & 0x3),
1195 (int) ((d >> 9) & 0x3),
1196 (int) ((d >> 8) & 0x1),
1197 (int) ((d >> 7) & 0x1),
1198 (int) ((d >> 6) & 0x1),
1199 (int) ((d >> 5) & 0x1),
1200 (int) ((d >> 4) & 0x1),
1201 (int) ((d >> 3) & 0x1),
1202 (int) ((d >> 2) & 0x1),
1203 (int) ((d >> 1) & 0x1),
1204 (int) ((d >> 0) & 0x1));
1205 }
1206 else if (regnum == RISCV_CSR_MISA_REGNUM)
1207 {
1208 int base;
1209 unsigned xlen, i;
1210 LONGEST d;
1212
1213 /* The MXL field is always in the upper two bits of MISA,
1214 regardless of the number of bits in MISA. Mask out other
1215 bits to ensure we have a positive value. */
1216 d = value_as_long (val);
1217 base = (d >> ((size * 8) - 2)) & 0x3;
1218 xlen = 16;
1219
1220 for (; base > 0; base--)
1221 xlen *= 2;
1222 gdb_printf (file, "\tRV%d", xlen);
1223
1224 for (i = 0; i < 26; i++)
1225 {
1226 if (d & (1 << i))
1227 gdb_printf (file, "%c", 'A' + i);
1228 }
1229 }
1230 else if (regnum == RISCV_CSR_FCSR_REGNUM
1231 || regnum == tdep->fflags_regnum
1232 || regnum == tdep->frm_regnum)
1233 {
1234 LONGEST d = value_as_long (val);
1235
1236 gdb_printf (file, "\t");
1237 if (regnum != tdep->frm_regnum)
1238 gdb_printf (file,
1239 "NV:%d DZ:%d OF:%d UF:%d NX:%d",
1240 (int) ((d >> 4) & 0x1),
1241 (int) ((d >> 3) & 0x1),
1242 (int) ((d >> 2) & 0x1),
1243 (int) ((d >> 1) & 0x1),
1244 (int) ((d >> 0) & 0x1));
1245
1246 if (regnum != tdep->fflags_regnum)
1247 {
1248 static const char * const sfrm[] =
1249 {
1250 _("RNE (round to nearest; ties to even)"),
1251 _("RTZ (Round towards zero)"),
1252 _("RDN (Round down towards -INF)"),
1253 _("RUP (Round up towards +INF)"),
1254 _("RMM (Round to nearest; ties to max magnitude)"),
1255 _("INVALID[5]"),
1256 _("INVALID[6]"),
1257 /* A value of 0x7 indicates dynamic rounding mode when
1258 used within an instructions rounding-mode field, but
1259 is invalid within the FRM register. */
1260 _("INVALID[7] (Dynamic rounding mode)"),
1261 };
1262 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
1263 ? (d >> 5) : d) & 0x7;
1264
1265 gdb_printf (file, "%sFRM:%i [%s]",
1266 (regnum == RISCV_CSR_FCSR_REGNUM
1267 ? " " : ""),
1268 frm, sfrm[frm]);
1269 }
1270 }
1271 else if (regnum == RISCV_PRIV_REGNUM)
1272 {
1273 LONGEST d;
1274 uint8_t priv;
1275
1276 d = value_as_long (val);
1277 priv = d & 0xff;
1278
1279 if (priv < 4)
1280 {
1281 static const char * const sprv[] =
1282 {
1283 "User/Application",
1284 "Supervisor",
1285 "Hypervisor",
1286 "Machine"
1287 };
1288 gdb_printf (file, "\tprv:%d [%s]",
1289 priv, sprv[priv]);
1290 }
1291 else
1292 gdb_printf (file, "\tprv:%d [INVALID]", priv);
1293 }
1294 else
1295 {
1296 /* If not a vector register, print it also according to its
1297 natural format. */
1298 if (regtype->is_vector () == 0)
1299 {
1300 get_user_print_options (&opts);
1301 opts.deref_ref = 1;
1302 gdb_printf (file, "\t");
1303 common_val_print (val, file, 0, &opts, current_language);
1304 }
1305 }
1306 }
1307 }
1308 gdb_printf (file, "\n");
1309}
1310
1311/* Return true if REGNUM is a valid CSR register. The CSR register space
1312 is sparsely populated, so not every number is a named CSR. */
1313
1314static bool
1316{
1317 gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
1319
1320 switch (regnum)
1321 {
1322#define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
1323#include "opcode/riscv-opc.h"
1324#undef DECLARE_CSR
1325 return true;
1326
1327 default:
1328 return false;
1329 }
1330}
1331
1332/* Return true if REGNUM is an unknown CSR identified in
1333 riscv_tdesc_unknown_reg for GDBARCH. */
1334
1335static bool
1337{
1338 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
1339 return (regnum >= tdep->unknown_csrs_first_regnum
1341 + tdep->unknown_csrs_count));
1342}
1343
1344/* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
1345 of REGGROUP? */
1346
1347static int
1349 const struct reggroup *reggroup)
1350{
1351 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
1352
1353 /* Used by 'info registers' and 'info registers <groupname>'. */
1354
1355 if (gdbarch_register_name (gdbarch, regnum)[0] == '\0')
1356 return 0;
1357
1359 {
1360 /* Any extra registers from the CSR tdesc_feature (identified in
1361 riscv_tdesc_unknown_reg) are removed from the save/restore groups
1362 as some targets (QEMU) report CSRs which then can't be read and
1363 having unreadable registers in the save/restore group breaks
1364 things like inferior calls.
1365
1366 The unknown CSRs are also removed from the general group, and
1367 added into both the csr and system group. This is inline with the
1368 known CSRs (see below). */
1370 {
1373 return 0;
1375 return 1;
1376 }
1377
1378 /* This is some other unknown register from the target description.
1379 In this case we trust whatever the target description says about
1380 which groups this register should be in. */
1382 if (ret != -1)
1383 return ret;
1384
1386 }
1387
1388 if (reggroup == all_reggroup)
1389 {
1390 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum >= RISCV_PRIV_REGNUM)
1391 return 1;
1393 return 1;
1394 return 0;
1395 }
1396 else if (reggroup == float_reggroup)
1397 return (riscv_is_fp_regno_p (regnum)
1398 || regnum == RISCV_CSR_FCSR_REGNUM
1399 || regnum == tdep->fflags_regnum
1400 || regnum == tdep->frm_regnum);
1401 else if (reggroup == general_reggroup)
1404 {
1406 return (regnum <= RISCV_LAST_FP_REGNUM
1407 || regnum == RISCV_CSR_FCSR_REGNUM
1408 || regnum == tdep->fflags_regnum
1409 || regnum == tdep->frm_regnum);
1410 else
1412 }
1414 {
1416 return 1;
1417 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
1418 return 0;
1420 return 1;
1421 return 0;
1422 }
1423 else if (reggroup == vector_reggroup)
1425 else
1426 return 0;
1427}
1428
1429/* Return the name for pseudo-register REGNUM for GDBARCH. */
1430
1431static const char *
1433{
1434 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
1435
1436 if (regnum == tdep->fflags_regnum)
1437 return "fflags";
1438 else if (regnum == tdep->frm_regnum)
1439 return "frm";
1440 else
1441 gdb_assert_not_reached ("unknown pseudo register number %d", regnum);
1442}
1443
1444/* Return the type for pseudo-register REGNUM for GDBARCH. */
1445
1446static struct type *
1448{
1449 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
1450
1451 if (regnum == tdep->fflags_regnum || regnum == tdep->frm_regnum)
1453 else
1454 gdb_assert_not_reached ("unknown pseudo register number %d", regnum);
1455}
1456
1457/* Return true (non-zero) if pseudo-register REGNUM from GDBARCH is a
1458 member of REGGROUP, otherwise return false (zero). */
1459
1460static int
1462 const struct reggroup *reggroup)
1463{
1464 /* The standard function will also work for pseudo-registers. */
1466}
1467
1468/* Implement the print_registers_info gdbarch method. This is used by
1469 'info registers' and 'info all-registers'. */
1470
1471static void
1473 struct ui_file *file,
1474 frame_info_ptr frame,
1475 int regnum, int print_all)
1476{
1477 if (regnum != -1)
1478 {
1479 /* Print one specified register. */
1480 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
1481 error (_("Not a valid register for the current processor type"));
1483 }
1484 else
1485 {
1486 const struct reggroup *reggroup;
1487
1488 if (print_all)
1490 else
1492
1494 {
1495 /* Zero never changes, so might as well hide by default. */
1496 if (regnum == RISCV_ZERO_REGNUM && !print_all)
1497 continue;
1498
1499 /* Registers with no name are not valid on this ISA. */
1500 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
1501 continue;
1502
1503 /* Is the register in the group we're interested in? */
1505 continue;
1506
1508 }
1509 }
1510}
1511
1512/* Class that handles one decoded RiscV instruction. */
1513
1515{
1516public:
1517
1518 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
1520 {
1521 /* Unknown value is used at initialisation time. */
1523
1524 /* These instructions are all the ones we are interested in during the
1525 prologue scan. */
1537 /* These are needed for software breakpoint support. */
1546 /* These are needed for stepping over atomic sequences. */
1549 /* This instruction is used to do a syscall. */
1551
1552 /* Other instructions are not interesting during the prologue scan, and
1553 are ignored. */
1554 OTHER
1556
1558 : m_length (0),
1559 m_opcode (OTHER),
1560 m_rd (0),
1561 m_rs1 (0),
1562 m_rs2 (0)
1563 {
1564 /* Nothing. */
1565 }
1566
1567 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1568
1569 /* Get the length of the instruction in bytes. */
1570 int length () const
1571 { return m_length; }
1572
1573 /* Get the opcode for this instruction. */
1574 enum opcode opcode () const
1575 { return m_opcode; }
1576
1577 /* Get destination register field for this instruction. This is only
1578 valid if the OPCODE implies there is such a field for this
1579 instruction. */
1580 int rd () const
1581 { return m_rd; }
1582
1583 /* Get the RS1 register field for this instruction. This is only valid
1584 if the OPCODE implies there is such a field for this instruction. */
1585 int rs1 () const
1586 { return m_rs1; }
1587
1588 /* Get the RS2 register field for this instruction. This is only valid
1589 if the OPCODE implies there is such a field for this instruction. */
1590 int rs2 () const
1591 { return m_rs2; }
1592
1593 /* Get the immediate for this instruction in signed form. This is only
1594 valid if the OPCODE implies there is such a field for this
1595 instruction. */
1596 int imm_signed () const
1597 { return m_imm.s; }
1598
1599private:
1600
1601 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1602 int decode_register_index (unsigned long opcode, int offset)
1603 {
1604 return (opcode >> offset) & 0x1F;
1605 }
1606
1607 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1608 int decode_register_index_short (unsigned long opcode, int offset)
1609 {
1610 return ((opcode >> offset) & 0x7) + 8;
1611 }
1612
1613 /* Helper for DECODE, decode 32-bit R-type instruction. */
1614 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1615 {
1616 m_opcode = opcode;
1617 m_rd = decode_register_index (ival, OP_SH_RD);
1618 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1619 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1620 }
1621
1622 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1623 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1624 {
1625 m_opcode = opcode;
1626 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1627 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1628 }
1629
1630 /* Helper for DECODE, decode 32-bit I-type instruction. */
1631 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1632 {
1633 m_opcode = opcode;
1634 m_rd = decode_register_index (ival, OP_SH_RD);
1635 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1636 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1637 }
1638
1639 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1640 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1641 {
1642 m_opcode = opcode;
1643 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1644 m_imm.s = EXTRACT_CITYPE_IMM (ival);
1645 }
1646
1647 /* Helper for DECODE, decode 16-bit compressed CL-type instruction. */
1648 void decode_cl_type_insn (enum opcode opcode, ULONGEST ival)
1649 {
1650 m_opcode = opcode;
1651 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1652 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1653 m_imm.s = EXTRACT_CLTYPE_IMM (ival);
1654 }
1655
1656 /* Helper for DECODE, decode 32-bit S-type instruction. */
1657 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1658 {
1659 m_opcode = opcode;
1660 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1661 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1662 m_imm.s = EXTRACT_STYPE_IMM (ival);
1663 }
1664
1665 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1666 encoding is different for each CS format instruction, so extracting
1667 the immediate is left up to the caller, who should pass the extracted
1668 immediate value through in IMM. */
1669 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1670 {
1671 m_opcode = opcode;
1672 m_imm.s = imm;
1673 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1674 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1675 }
1676
1677 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1678 encoding is different for each CSS format instruction, so extracting
1679 the immediate is left up to the caller, who should pass the extracted
1680 immediate value through in IMM. */
1681 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1682 {
1683 m_opcode = opcode;
1684 m_imm.s = imm;
1685 m_rs1 = RISCV_SP_REGNUM;
1686 /* Not a compressed register number in this case. */
1687 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1688 }
1689
1690 /* Helper for DECODE, decode 32-bit U-type instruction. */
1691 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1692 {
1693 m_opcode = opcode;
1694 m_rd = decode_register_index (ival, OP_SH_RD);
1695 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1696 }
1697
1698 /* Helper for DECODE, decode 32-bit J-type instruction. */
1699 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1700 {
1701 m_opcode = opcode;
1702 m_rd = decode_register_index (ival, OP_SH_RD);
1703 m_imm.s = EXTRACT_JTYPE_IMM (ival);
1704 }
1705
1706 /* Helper for DECODE, decode 32-bit J-type instruction. */
1707 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1708 {
1709 m_opcode = opcode;
1710 m_imm.s = EXTRACT_CJTYPE_IMM (ival);
1711 }
1712
1713 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1714 {
1715 m_opcode = opcode;
1716 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1717 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1718 m_imm.s = EXTRACT_BTYPE_IMM (ival);
1719 }
1720
1721 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1722 {
1723 m_opcode = opcode;
1724 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1725 m_imm.s = EXTRACT_CBTYPE_IMM (ival);
1726 }
1727
1728 /* Fetch instruction from target memory at ADDR, return the content of
1729 the instruction, and update LEN with the instruction length. */
1730 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1731 CORE_ADDR addr, int *len);
1732
1733 /* The length of the instruction in bytes. Should be 2 or 4. */
1735
1736 /* The instruction opcode. */
1738
1739 /* The three possible registers an instruction might reference. Not
1740 every instruction fills in all of these registers. Which fields are
1741 valid depends on the opcode. The naming of these fields matches the
1742 naming in the riscv isa manual. */
1743 int m_rd;
1746
1747 /* Possible instruction immediate. This is only valid if the instruction
1748 format contains an immediate, not all instruction, whether this is
1749 valid depends on the opcode. Despite only having one format for now
1750 the immediate is packed into a union, later instructions might require
1751 an unsigned formatted immediate, having the union in place now will
1752 reduce the need for code churn later. */
1754 {
1756 : s (0)
1757 {
1758 /* Nothing. */
1759 }
1760
1761 int s;
1762 } m_imm;
1763};
1764
1765/* Fetch instruction from target memory at ADDR, return the content of the
1766 instruction, and update LEN with the instruction length. */
1767
1768ULONGEST
1770 CORE_ADDR addr, int *len)
1771{
1772 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1773 gdb_byte buf[RISCV_MAX_INSN_LEN];
1774 int instlen, status;
1775
1776 /* All insns are at least 16 bits. */
1777 status = target_read_memory (addr, buf, 2);
1778 if (status)
1780
1781 /* If we need more, grab it now. */
1782 instlen = riscv_insn_length (buf[0]);
1783 gdb_assert (instlen <= sizeof (buf));
1784 *len = instlen;
1785
1786 if (instlen > 2)
1787 {
1788 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1789 if (status)
1790 memory_error (TARGET_XFER_E_IO, addr + 2);
1791 }
1792
1793 return extract_unsigned_integer (buf, instlen, byte_order);
1794}
1795
1796/* Fetch from target memory an instruction at PC and decode it. This can
1797 throw an error if the memory access fails, callers are responsible for
1798 handling this error if that is appropriate. */
1799
1800void
1801riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1802{
1803 ULONGEST ival;
1804
1805 /* Fetch the instruction, and the instructions length. */
1806 ival = fetch_instruction (gdbarch, pc, &m_length);
1807
1808 if (m_length == 4)
1809 {
1810 if (is_add_insn (ival))
1811 decode_r_type_insn (ADD, ival);
1812 else if (is_addw_insn (ival))
1813 decode_r_type_insn (ADDW, ival);
1814 else if (is_addi_insn (ival))
1815 decode_i_type_insn (ADDI, ival);
1816 else if (is_addiw_insn (ival))
1817 decode_i_type_insn (ADDIW, ival);
1818 else if (is_auipc_insn (ival))
1819 decode_u_type_insn (AUIPC, ival);
1820 else if (is_lui_insn (ival))
1821 decode_u_type_insn (LUI, ival);
1822 else if (is_sd_insn (ival))
1823 decode_s_type_insn (SD, ival);
1824 else if (is_sw_insn (ival))
1825 decode_s_type_insn (SW, ival);
1826 else if (is_jal_insn (ival))
1827 decode_j_type_insn (JAL, ival);
1828 else if (is_jalr_insn (ival))
1829 decode_i_type_insn (JALR, ival);
1830 else if (is_beq_insn (ival))
1831 decode_b_type_insn (BEQ, ival);
1832 else if (is_bne_insn (ival))
1833 decode_b_type_insn (BNE, ival);
1834 else if (is_blt_insn (ival))
1835 decode_b_type_insn (BLT, ival);
1836 else if (is_bge_insn (ival))
1837 decode_b_type_insn (BGE, ival);
1838 else if (is_bltu_insn (ival))
1839 decode_b_type_insn (BLTU, ival);
1840 else if (is_bgeu_insn (ival))
1841 decode_b_type_insn (BGEU, ival);
1842 else if (is_lr_w_insn (ival))
1843 decode_r_type_insn (LR, ival);
1844 else if (is_lr_d_insn (ival))
1845 decode_r_type_insn (LR, ival);
1846 else if (is_sc_w_insn (ival))
1847 decode_r_type_insn (SC, ival);
1848 else if (is_sc_d_insn (ival))
1849 decode_r_type_insn (SC, ival);
1850 else if (is_ecall_insn (ival))
1851 decode_i_type_insn (ECALL, ival);
1852 else if (is_ld_insn (ival))
1853 decode_i_type_insn (LD, ival);
1854 else if (is_lw_insn (ival))
1855 decode_i_type_insn (LW, ival);
1856 else
1857 /* None of the other fields are valid in this case. */
1858 m_opcode = OTHER;
1859 }
1860 else if (m_length == 2)
1861 {
1862 int xlen = riscv_isa_xlen (gdbarch);
1863
1864 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1865 C_JALR. So must try to match C_JALR first as it has more bits in
1866 mask. */
1867 if (is_c_jalr_insn (ival))
1868 decode_cr_type_insn (JALR, ival);
1869 else if (is_c_add_insn (ival))
1870 decode_cr_type_insn (ADD, ival);
1871 /* C_ADDW is RV64 and RV128 only. */
1872 else if (xlen != 4 && is_c_addw_insn (ival))
1873 decode_cr_type_insn (ADDW, ival);
1874 else if (is_c_addi_insn (ival))
1875 decode_ci_type_insn (ADDI, ival);
1876 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1877 only and C_JAL is RV32 only. */
1878 else if (xlen != 4 && is_c_addiw_insn (ival))
1879 decode_ci_type_insn (ADDIW, ival);
1880 else if (xlen == 4 && is_c_jal_insn (ival))
1881 decode_cj_type_insn (JAL, ival);
1882 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1883 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1884 in mask. */
1885 else if (is_c_addi16sp_insn (ival))
1886 {
1887 m_opcode = ADDI;
1888 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1889 m_imm.s = EXTRACT_CITYPE_ADDI16SP_IMM (ival);
1890 }
1891 else if (is_c_addi4spn_insn (ival))
1892 {
1893 m_opcode = ADDI;
1894 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1895 m_rs1 = RISCV_SP_REGNUM;
1896 m_imm.s = EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival);
1897 }
1898 else if (is_c_lui_insn (ival))
1899 {
1900 m_opcode = LUI;
1901 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1902 m_imm.s = EXTRACT_CITYPE_LUI_IMM (ival);
1903 }
1904 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1905 and C_FSW is RV32 only. */
1906 else if (xlen != 4 && is_c_sd_insn (ival))
1907 decode_cs_type_insn (SD, ival, EXTRACT_CLTYPE_LD_IMM (ival));
1908 else if (is_c_sw_insn (ival))
1909 decode_cs_type_insn (SW, ival, EXTRACT_CLTYPE_LW_IMM (ival));
1910 else if (is_c_swsp_insn (ival))
1911 decode_css_type_insn (SW, ival, EXTRACT_CSSTYPE_SWSP_IMM (ival));
1912 else if (xlen != 4 && is_c_sdsp_insn (ival))
1913 decode_css_type_insn (SD, ival, EXTRACT_CSSTYPE_SDSP_IMM (ival));
1914 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1915 So must try to match C_JR first as it has more bits in mask. */
1916 else if (is_c_jr_insn (ival))
1917 decode_cr_type_insn (JALR, ival);
1918 else if (is_c_mv_insn (ival))
1919 decode_cr_type_insn (MV, ival);
1920 else if (is_c_j_insn (ival))
1921 decode_cj_type_insn (JAL, ival);
1922 else if (is_c_beqz_insn (ival))
1923 decode_cb_type_insn (BEQ, ival);
1924 else if (is_c_bnez_insn (ival))
1925 decode_cb_type_insn (BNE, ival);
1926 else if (is_c_ld_insn (ival))
1927 decode_cl_type_insn (LD, ival);
1928 else if (is_c_lw_insn (ival))
1929 decode_cl_type_insn (LW, ival);
1930 else
1931 /* None of the other fields of INSN are valid in this case. */
1932 m_opcode = OTHER;
1933 }
1934 else
1935 {
1936 /* 6 bytes or more. If the instruction is longer than 8 bytes, we don't
1937 have full instruction bits in ival. At least, such long instructions
1938 are not defined yet, so just ignore it. */
1939 gdb_assert (m_length > 0 && m_length % 2 == 0);
1940 m_opcode = OTHER;
1941 }
1942}
1943
1944/* The prologue scanner. This is currently only used for skipping the
1945 prologue of a function when the DWARF information is not sufficient.
1946 However, it is written with filling of the frame cache in mind, which
1947 is why different groups of stack setup instructions are split apart
1948 during the core of the inner loop. In the future, the intention is to
1949 extend this function to fully support building up a frame cache that
1950 can unwind register values when there is no DWARF information. */
1951
1952static CORE_ADDR
1954 CORE_ADDR start_pc, CORE_ADDR end_pc,
1955 struct riscv_unwind_cache *cache)
1956{
1957 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1958 CORE_ADDR end_prologue_addr = 0;
1959
1960 /* Find an upper limit on the function prologue using the debug
1961 information. If the debug information could not be used to provide
1962 that bound, then use an arbitrary large number as the upper bound. */
1963 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1964 if (after_prologue_pc == 0)
1965 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1966 if (after_prologue_pc < end_pc)
1967 end_pc = after_prologue_pc;
1968
1969 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1970 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1971 regs[regno] = pv_register (regno, 0);
1973
1976 (gdb_stdlog,
1977 "Prologue scan for function starting at %s (limit %s)\n",
1978 core_addr_to_string (start_pc),
1979 core_addr_to_string (end_pc));
1980
1981 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1982 {
1983 struct riscv_insn insn;
1984
1985 /* Decode the current instruction, and decide where the next
1986 instruction lives based on the size of this instruction. */
1987 insn.decode (gdbarch, cur_pc);
1988 gdb_assert (insn.length () > 0);
1989 next_pc = cur_pc + insn.length ();
1990
1991 /* Look for common stack adjustment insns. */
1992 if ((insn.opcode () == riscv_insn::ADDI
1993 || insn.opcode () == riscv_insn::ADDIW)
1994 && insn.rd () == RISCV_SP_REGNUM
1995 && insn.rs1 () == RISCV_SP_REGNUM)
1996 {
1997 /* Handle: addi sp, sp, -i
1998 or: addiw sp, sp, -i */
1999 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
2000 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
2001 regs[insn.rd ()]
2002 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
2003 }
2004 else if ((insn.opcode () == riscv_insn::SW
2005 || insn.opcode () == riscv_insn::SD)
2006 && (insn.rs1 () == RISCV_SP_REGNUM
2007 || insn.rs1 () == RISCV_FP_REGNUM))
2008 {
2009 /* Handle: sw reg, offset(sp)
2010 or: sd reg, offset(sp)
2011 or: sw reg, offset(s0)
2012 or: sd reg, offset(s0) */
2013 /* Instruction storing a register onto the stack. */
2014 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
2015 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
2016 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
2017 (insn.opcode () == riscv_insn::SW ? 4 : 8),
2018 regs[insn.rs2 ()]);
2019 }
2020 else if (insn.opcode () == riscv_insn::ADDI
2021 && insn.rd () == RISCV_FP_REGNUM
2022 && insn.rs1 () == RISCV_SP_REGNUM)
2023 {
2024 /* Handle: addi s0, sp, size */
2025 /* Instructions setting up the frame pointer. */
2026 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
2027 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
2028 regs[insn.rd ()]
2029 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
2030 }
2031 else if ((insn.opcode () == riscv_insn::ADD
2032 || insn.opcode () == riscv_insn::ADDW)
2033 && insn.rd () == RISCV_FP_REGNUM
2034 && insn.rs1 () == RISCV_SP_REGNUM
2035 && insn.rs2 () == RISCV_ZERO_REGNUM)
2036 {
2037 /* Handle: add s0, sp, 0
2038 or: addw s0, sp, 0 */
2039 /* Instructions setting up the frame pointer. */
2040 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
2041 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
2042 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
2043 }
2044 else if ((insn.opcode () == riscv_insn::ADDI
2045 && insn.rd () == RISCV_ZERO_REGNUM
2046 && insn.rs1 () == RISCV_ZERO_REGNUM
2047 && insn.imm_signed () == 0))
2048 {
2049 /* Handle: add x0, x0, 0 (NOP) */
2050 }
2051 else if (insn.opcode () == riscv_insn::AUIPC)
2052 {
2053 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
2054 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
2055 }
2056 else if (insn.opcode () == riscv_insn::LUI)
2057 {
2058 /* Handle: lui REG, n
2059 Where REG is not gp register. */
2060 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
2061 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
2062 }
2063 else if (insn.opcode () == riscv_insn::ADDI)
2064 {
2065 /* Handle: addi REG1, REG2, IMM */
2066 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
2067 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
2068 regs[insn.rd ()]
2069 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
2070 }
2071 else if (insn.opcode () == riscv_insn::ADD)
2072 {
2073 /* Handle: add REG1, REG2, REG3 */
2074 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
2075 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
2076 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
2077 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
2078 }
2079 else if (insn.opcode () == riscv_insn::LD
2080 || insn.opcode () == riscv_insn::LW)
2081 {
2082 /* Handle: ld reg, offset(rs1)
2083 or: c.ld reg, offset(rs1)
2084 or: lw reg, offset(rs1)
2085 or: c.lw reg, offset(rs1) */
2086 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
2087 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
2088 regs[insn.rd ()]
2089 = stack.fetch (pv_add_constant (regs[insn.rs1 ()],
2090 insn.imm_signed ()),
2091 (insn.opcode () == riscv_insn::LW ? 4 : 8));
2092 }
2093 else if (insn.opcode () == riscv_insn::MV)
2094 {
2095 /* Handle: c.mv RD, RS2 */
2096 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
2097 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
2098 gdb_assert (insn.rs2 () > 0);
2099 regs[insn.rd ()] = regs[insn.rs2 ()];
2100 }
2101 else
2102 {
2103 end_prologue_addr = cur_pc;
2104 break;
2105 }
2106 }
2107
2108 if (end_prologue_addr == 0)
2109 end_prologue_addr = cur_pc;
2110
2112 gdb_printf (gdb_stdlog, "End of prologue at %s\n",
2113 core_addr_to_string (end_prologue_addr));
2114
2115 if (cache != NULL)
2116 {
2117 /* Figure out if it is a frame pointer or just a stack pointer. Also
2118 the offset held in the pv_t is from the original register value to
2119 the current value, which for a grows down stack means a negative
2120 value. The FRAME_BASE_OFFSET is the negation of this, how to get
2121 from the current value to the original value. */
2123 {
2125 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
2126 }
2127 else
2128 {
2130 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
2131 }
2132
2133 /* Assign offset from old SP to all saved registers. As we don't
2134 have the previous value for the frame base register at this
2135 point, we store the offset as the address in the trad_frame, and
2136 then convert this to an actual address later. */
2137 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
2138 {
2139 CORE_ADDR offset;
2140 if (stack.find_reg (gdbarch, i, &offset))
2141 {
2143 {
2144 /* Display OFFSET as a signed value, the offsets are from
2145 the frame base address to the registers location on
2146 the stack, with a descending stack this means the
2147 offsets are always negative. */
2149 "Register $%s at stack offset %s\n",
2151 plongest ((LONGEST) offset));
2152 }
2153 cache->regs[i].set_addr (offset);
2154 }
2155 }
2156 }
2157
2158 return end_prologue_addr;
2159}
2160
2161/* Implement the riscv_skip_prologue gdbarch method. */
2162
2163static CORE_ADDR
2164riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2165{
2166 CORE_ADDR func_addr;
2167
2168 /* See if we can determine the end of the prologue via the symbol
2169 table. If so, then return either PC, or the PC after the
2170 prologue, whichever is greater. */
2171 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
2172 {
2173 CORE_ADDR post_prologue_pc
2174 = skip_prologue_using_sal (gdbarch, func_addr);
2175
2176 if (post_prologue_pc != 0)
2177 return std::max (pc, post_prologue_pc);
2178 }
2179
2180 /* Can't determine prologue from the symbol table, need to examine
2181 instructions. Pass -1 for the end address to indicate the prologue
2182 scanner can scan as far as it needs to find the end of the prologue. */
2183 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
2184}
2185
2186/* Implement the gdbarch push dummy code callback. */
2187
2188static CORE_ADDR
2190 CORE_ADDR funaddr, struct value **args, int nargs,
2191 struct type *value_type, CORE_ADDR *real_pc,
2192 CORE_ADDR *bp_addr, struct regcache *regcache)
2193{
2194 /* A nop instruction is 'add x0, x0, 0'. */
2195 static const gdb_byte nop_insn[] = { 0x13, 0x00, 0x00, 0x00 };
2196
2197 /* Allocate space for a breakpoint, and keep the stack correctly
2198 aligned. The space allocated here must be at least big enough to
2199 accommodate the NOP_INSN defined above. */
2200 sp -= 16;
2201 *bp_addr = sp;
2202 *real_pc = funaddr;
2203
2204 /* When we insert a breakpoint we select whether to use a compressed
2205 breakpoint or not based on the existing contents of the memory.
2206
2207 If the breakpoint is being placed onto the stack as part of setting up
2208 for an inferior call from GDB, then the existing stack contents may
2209 randomly appear to be a compressed instruction, causing GDB to insert
2210 a compressed breakpoint. If this happens on a target that does not
2211 support compressed instructions then this could cause problems.
2212
2213 To prevent this issue we write an uncompressed nop onto the stack at
2214 the location where the breakpoint will be inserted. In this way we
2215 ensure that we always use an uncompressed breakpoint, which should
2216 work on all targets.
2217
2218 We call TARGET_WRITE_MEMORY here so that if the write fails we don't
2219 throw an exception. Instead we ignore the error and move on. The
2220 assumption is that either GDB will error later when actually trying to
2221 insert a software breakpoint, or GDB will use hardware breakpoints and
2222 there will be no need to write to memory later. */
2223 int status = target_write_memory (*bp_addr, nop_insn, sizeof (nop_insn));
2224
2227 "Writing %s-byte nop instruction to %s: %s\n",
2228 plongest (sizeof (nop_insn)),
2229 paddress (gdbarch, *bp_addr),
2230 (status == 0 ? "success" : "failed"));
2231
2232 return sp;
2233}
2234
2235/* Implement the gdbarch type alignment method, overrides the generic
2236 alignment algorithm for anything that is RISC-V specific. */
2237
2238static ULONGEST
2240{
2242 if (type->code () == TYPE_CODE_ARRAY && type->is_vector ())
2243 return std::min (type->length (), (ULONGEST) BIGGEST_ALIGNMENT);
2244
2245 /* Anything else will be aligned by the generic code. */
2246 return 0;
2247}
2248
2249/* Holds information about a single argument either being passed to an
2250 inferior function, or returned from an inferior function. This includes
2251 information about the size, type, etc of the argument, and also
2252 information about how the argument will be passed (or returned). */
2253
2255{
2256 /* Contents of the argument. */
2257 const gdb_byte *contents;
2258
2259 /* Length of argument. */
2261
2262 /* Alignment required for an argument of this type. */
2264
2265 /* The type for this argument. */
2266 struct type *type;
2267
2268 /* Each argument can have either 1 or 2 locations assigned to it. Each
2269 location describes where part of the argument will be placed. The
2270 second location is valid based on the LOC_TYPE and C_LENGTH fields
2271 of the first location (which is always valid). */
2273 {
2274 /* What type of location this is. */
2276 {
2277 /* Argument passed in a register. */
2279
2280 /* Argument passed as an on stack argument. */
2282
2283 /* Argument passed by reference. The second location is always
2284 valid for a BY_REF argument, and describes where the address
2285 of the BY_REF argument should be placed. */
2286 by_ref
2287 } loc_type;
2288
2289 /* Information that depends on the location type. */
2290 union
2291 {
2292 /* Which register number to use. */
2294
2295 /* The offset into the stack region. */
2297 } loc_data;
2298
2299 /* The length of contents covered by this location. If this is less
2300 than the total length of the argument, then the second location
2301 will be valid, and will describe where the rest of the argument
2302 will go. */
2304
2305 /* The offset within CONTENTS for this part of the argument. This can
2306 be non-zero even for the first part (the first field of a struct can
2307 have a non-zero offset due to padding). For the second part of the
2308 argument, this might be the C_LENGTH value of the first part,
2309 however, if we are passing a structure in two registers, and there's
2310 is padding between the first and second field, then this offset
2311 might be greater than the length of the first argument part. When
2312 the second argument location is not holding part of the argument
2313 value, but is instead holding the address of a reference argument,
2314 then this offset will be set to 0. */
2316 } argloc[2];
2317
2318 /* TRUE if this is an unnamed argument. */
2320};
2321
2322/* Information about a set of registers being used for passing arguments as
2323 part of a function call. The register set must be numerically
2324 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
2325 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
2326
2328{
2329 riscv_arg_reg (int first, int last)
2330 : next_regnum (first),
2331 last_regnum (last)
2332 {
2333 /* Nothing. */
2334 }
2335
2336 /* The GDB register number to use in this set. */
2338
2339 /* The last GDB register number to use in this set. */
2341};
2342
2343/* Arguments can be passed as on stack arguments, or by reference. The
2344 on stack arguments must be in a continuous region starting from $sp,
2345 while the by reference arguments can be anywhere, but we'll put them
2346 on the stack after (at higher address) the on stack arguments.
2347
2348 This might not be the right approach to take. The ABI is clear that
2349 an argument passed by reference can be modified by the callee, which
2350 us placing the argument (temporarily) onto the stack will not achieve
2351 (changes will be lost). There's also the possibility that very large
2352 arguments could overflow the stack.
2353
2354 This struct is used to track offset into these two areas for where
2355 arguments are to be placed. */
2357{
2359 : arg_offset (0),
2360 ref_offset (0)
2361 {
2362 /* Nothing. */
2363 }
2364
2365 /* Offset into on stack argument area. */
2367
2368 /* Offset into the pass by reference area. */
2370};
2371
2372/* Holds information about where arguments to a call will be placed. This
2373 is updated as arguments are added onto the call, and can be used to
2374 figure out where the next argument should be placed. */
2375
2377{
2379 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
2380 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
2381 {
2382 xlen = riscv_abi_xlen (gdbarch);
2383 flen = riscv_abi_flen (gdbarch);
2384
2385 /* Reduce the number of integer argument registers when using the
2386 embedded abi (i.e. rv32e). */
2388 int_regs.last_regnum = RISCV_A0_REGNUM + 5;
2389
2390 /* Disable use of floating point registers if needed. */
2392 float_regs.next_regnum = float_regs.last_regnum + 1;
2393 }
2394
2395 /* Track the memory areas used for holding in-memory arguments to a
2396 call. */
2398
2399 /* Holds information about the next integer register to use for passing
2400 an argument. */
2401 struct riscv_arg_reg int_regs;
2402
2403 /* Holds information about the next floating point register to use for
2404 passing an argument. */
2405 struct riscv_arg_reg float_regs;
2406
2407 /* The XLEN and FLEN are copied in to this structure for convenience, and
2408 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
2409 int xlen;
2410 int flen;
2411};
2412
2413/* Return the number of registers available for use as parameters in the
2414 register set REG. Returned value can be 0 or more. */
2415
2416static int
2418{
2419 if (reg->next_regnum > reg->last_regnum)
2420 return 0;
2421
2422 return (reg->last_regnum - reg->next_regnum + 1);
2423}
2424
2425/* If there is at least one register available in the register set REG then
2426 the next register from REG is assigned to LOC and the length field of
2427 LOC is updated to LENGTH. The register set REG is updated to indicate
2428 that the assigned register is no longer available and the function
2429 returns true.
2430
2431 If there are no registers available in REG then the function returns
2432 false, and LOC and REG are unchanged. */
2433
2434static bool
2436 struct riscv_arg_reg *reg,
2437 int length, int offset)
2438{
2439 if (reg->next_regnum <= reg->last_regnum)
2440 {
2442 loc->loc_data.regno = reg->next_regnum;
2443 reg->next_regnum++;
2444 loc->c_length = length;
2445 loc->c_offset = offset;
2446 return true;
2447 }
2448
2449 return false;
2450}
2451
2452/* Assign LOC a location as the next stack parameter, and update MEMORY to
2453 record that an area of stack has been used to hold the parameter
2454 described by LOC.
2455
2456 The length field of LOC is updated to LENGTH, the length of the
2457 parameter being stored, and ALIGN is the alignment required by the
2458 parameter, which will affect how memory is allocated out of MEMORY. */
2459
2460static void
2462 struct riscv_memory_offsets *memory,
2463 int length, int align)
2464{
2466 memory->arg_offset
2467 = align_up (memory->arg_offset, align);
2468 loc->loc_data.offset = memory->arg_offset;
2469 memory->arg_offset += length;
2470 loc->c_length = length;
2471
2472 /* Offset is always 0, either we're the first location part, in which
2473 case we're reading content from the start of the argument, or we're
2474 passing the address of a reference argument, so 0. */
2475 loc->c_offset = 0;
2476}
2477
2478/* Update AINFO, which describes an argument that should be passed or
2479 returned using the integer ABI. The argloc fields within AINFO are
2480 updated to describe the location in which the argument will be passed to
2481 a function, or returned from a function.
2482
2483 The CINFO structure contains the ongoing call information, the holds
2484 information such as which argument registers are remaining to be
2485 assigned to parameter, and how much memory has been used by parameters
2486 so far.
2487
2488 By examining the state of CINFO a suitable location can be selected,
2489 and assigned to AINFO. */
2490
2491static void
2493 struct riscv_call_info *cinfo)
2494{
2495 if (ainfo->length > (2 * cinfo->xlen))
2496 {
2497 /* Argument is going to be passed by reference. */
2498 ainfo->argloc[0].loc_type
2500 cinfo->memory.ref_offset
2501 = align_up (cinfo->memory.ref_offset, ainfo->align);
2502 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
2503 cinfo->memory.ref_offset += ainfo->length;
2504 ainfo->argloc[0].c_length = ainfo->length;
2505
2506 /* The second location for this argument is given over to holding the
2507 address of the by-reference data. Pass 0 for the offset as this
2508 is not part of the actual argument value. */
2509 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2510 &cinfo->int_regs,
2511 cinfo->xlen, 0))
2513 &cinfo->memory, cinfo->xlen,
2514 cinfo->xlen);
2515 }
2516 else
2517 {
2518 int len = std::min (ainfo->length, cinfo->xlen);
2519 int align = std::max (ainfo->align, cinfo->xlen);
2520
2521 /* Unnamed arguments in registers that require 2*XLEN alignment are
2522 passed in an aligned register pair. */
2523 if (ainfo->is_unnamed && (align == cinfo->xlen * 2)
2524 && cinfo->int_regs.next_regnum & 1)
2525 cinfo->int_regs.next_regnum++;
2526
2527 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2528 &cinfo->int_regs, len, 0))
2530 &cinfo->memory, len, align);
2531
2532 if (len < ainfo->length)
2533 {
2534 len = ainfo->length - len;
2535 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2536 &cinfo->int_regs, len,
2537 cinfo->xlen))
2539 &cinfo->memory, len, cinfo->xlen);
2540 }
2541 }
2542}
2543
2544/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2545 is being passed with the floating point ABI. */
2546
2547static void
2549 struct riscv_call_info *cinfo)
2550{
2551 if (ainfo->length > cinfo->flen || ainfo->is_unnamed)
2552 return riscv_call_arg_scalar_int (ainfo, cinfo);
2553 else
2554 {
2555 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2556 &cinfo->float_regs,
2557 ainfo->length, 0))
2558 return riscv_call_arg_scalar_int (ainfo, cinfo);
2559 }
2560}
2561
2562/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2563 is a complex floating point argument, and is therefore handled
2564 differently to other argument types. */
2565
2566static void
2568 struct riscv_call_info *cinfo)
2569{
2570 if (ainfo->length <= (2 * cinfo->flen)
2571 && riscv_arg_regs_available (&cinfo->float_regs) >= 2
2572 && !ainfo->is_unnamed)
2573 {
2574 bool result;
2575 int len = ainfo->length / 2;
2576
2577 result = riscv_assign_reg_location (&ainfo->argloc[0],
2578 &cinfo->float_regs, len, 0);
2579 gdb_assert (result);
2580
2581 result = riscv_assign_reg_location (&ainfo->argloc[1],
2582 &cinfo->float_regs, len, len);
2583 gdb_assert (result);
2584 }
2585 else
2586 return riscv_call_arg_scalar_int (ainfo, cinfo);
2587}
2588
2589/* A structure used for holding information about a structure type within
2590 the inferior program. The RiscV ABI has special rules for handling some
2591 structures with a single field or with two fields. The counting of
2592 fields here is done after flattening out all nested structures. */
2593
2595{
2596public:
2598 : m_number_of_fields (0),
2599 m_types { nullptr, nullptr },
2600 m_offsets { 0, 0 }
2601 {
2602 /* Nothing. */
2603 }
2604
2605 /* Analyse TYPE descending into nested structures, count the number of
2606 scalar fields and record the types of the first two fields found. */
2607 void analyse (struct type *type)
2608 {
2609 analyse_inner (type, 0);
2610 }
2611
2612 /* The number of scalar fields found in the analysed type. This is
2613 currently only accurate if the value returned is 0, 1, or 2 as the
2614 analysis stops counting when the number of fields is 3. This is
2615 because the RiscV ABI only has special cases for 1 or 2 fields,
2616 anything else we just don't care about. */
2617 int number_of_fields () const
2618 { return m_number_of_fields; }
2619
2620 /* Return the type for scalar field INDEX within the analysed type. Will
2621 return nullptr if there is no field at that index. Only INDEX values
2622 0 and 1 can be requested as the RiscV ABI only has special cases for
2623 structures with 1 or 2 fields. */
2624 struct type *field_type (int index) const
2625 {
2626 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
2627 return m_types[index];
2628 }
2629
2630 /* Return the offset of scalar field INDEX within the analysed type. Will
2631 return 0 if there is no field at that index. Only INDEX values 0 and
2632 1 can be requested as the RiscV ABI only has special cases for
2633 structures with 1 or 2 fields. */
2634 int field_offset (int index) const
2635 {
2636 gdb_assert (index < (sizeof (m_offsets) / sizeof (m_offsets[0])));
2637 return m_offsets[index];
2638 }
2639
2640private:
2641 /* The number of scalar fields found within the structure after recursing
2642 into nested structures. */
2644
2645 /* The types of the first two scalar fields found within the structure
2646 after recursing into nested structures. */
2647 struct type *m_types[2];
2648
2649 /* The offsets of the first two scalar fields found within the structure
2650 after recursing into nested structures. */
2651 int m_offsets[2];
2652
2653 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2654 offset from the start of the top level structure being analysed. */
2655 void analyse_inner (struct type *type, int offset);
2656};
2657
2658/* See description in class declaration. */
2659
2660void
2662{
2663 unsigned int count = type->num_fields ();
2664 unsigned int i;
2665
2666 for (i = 0; i < count; ++i)
2667 {
2669 continue;
2670
2671 struct type *field_type = type->field (i).type ();
2672 field_type = check_typedef (field_type);
2673 int field_offset
2674 = offset + type->field (i).loc_bitpos () / TARGET_CHAR_BIT;
2675
2676 switch (field_type->code ())
2677 {
2678 case TYPE_CODE_STRUCT:
2679 analyse_inner (field_type, field_offset);
2680 break;
2681
2682 default:
2683 /* RiscV only flattens out structures. Anything else does not
2684 need to be flattened, we just record the type, and when we
2685 look at the analysis results we'll realise this is not a
2686 structure we can special case, and pass the structure in
2687 memory. */
2688 if (m_number_of_fields < 2)
2689 {
2690 m_types[m_number_of_fields] = field_type;
2691 m_offsets[m_number_of_fields] = field_offset;
2692 }
2693 m_number_of_fields++;
2694 break;
2695 }
2696
2697 /* RiscV only has special handling for structures with 1 or 2 scalar
2698 fields, any more than that and the structure is just passed in
2699 memory. We can safely drop out early when we find 3 or more
2700 fields then. */
2701
2702 if (m_number_of_fields > 2)
2703 return;
2704 }
2705}
2706
2707/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2708 is a structure. Small structures on RiscV have some special case
2709 handling in order that the structure might be passed in register.
2710 Larger structures are passed in memory. After assigning location
2711 information to AINFO, CINFO will have been updated. */
2712
2713static void
2715 struct riscv_call_info *cinfo)
2716{
2717 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2718 {
2719 struct riscv_struct_info sinfo;
2720
2721 sinfo.analyse (ainfo->type);
2722 if (sinfo.number_of_fields () == 1
2723 && sinfo.field_type(0)->code () == TYPE_CODE_COMPLEX)
2724 {
2725 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2726 except we use the type of the complex field instead of the
2727 type from AINFO, and the first location might be at a non-zero
2728 offset. */
2729 if (sinfo.field_type (0)->length () <= (2 * cinfo->flen)
2730 && riscv_arg_regs_available (&cinfo->float_regs) >= 2
2731 && !ainfo->is_unnamed)
2732 {
2733 bool result;
2734 int len = sinfo.field_type (0)->length () / 2;
2735 int offset = sinfo.field_offset (0);
2736
2737 result = riscv_assign_reg_location (&ainfo->argloc[0],
2738 &cinfo->float_regs, len,
2739 offset);
2740 gdb_assert (result);
2741
2742 result = riscv_assign_reg_location (&ainfo->argloc[1],
2743 &cinfo->float_regs, len,
2744 (offset + len));
2745 gdb_assert (result);
2746 }
2747 else
2748 riscv_call_arg_scalar_int (ainfo, cinfo);
2749 return;
2750 }
2751
2752 if (sinfo.number_of_fields () == 1
2753 && sinfo.field_type(0)->code () == TYPE_CODE_FLT)
2754 {
2755 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2756 except we use the type of the first scalar field instead of
2757 the type from AINFO. Also the location might be at a non-zero
2758 offset. */
2759 if (sinfo.field_type (0)->length () > cinfo->flen
2760 || ainfo->is_unnamed)
2761 riscv_call_arg_scalar_int (ainfo, cinfo);
2762 else
2763 {
2764 int offset = sinfo.field_offset (0);
2765 int len = sinfo.field_type (0)->length ();
2766
2767 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2768 &cinfo->float_regs,
2769 len, offset))
2770 riscv_call_arg_scalar_int (ainfo, cinfo);
2771 }
2772 return;
2773 }
2774
2775 if (sinfo.number_of_fields () == 2
2776 && sinfo.field_type(0)->code () == TYPE_CODE_FLT
2777 && sinfo.field_type (0)->length () <= cinfo->flen
2778 && sinfo.field_type(1)->code () == TYPE_CODE_FLT
2779 && sinfo.field_type (1)->length () <= cinfo->flen
2780 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2781 {
2782 int len0 = sinfo.field_type (0)->length ();
2783 int offset = sinfo.field_offset (0);
2784 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2785 &cinfo->float_regs, len0, offset))
2786 error (_("failed during argument setup"));
2787
2788 int len1 = sinfo.field_type (1)->length ();
2789 offset = sinfo.field_offset (1);
2790 gdb_assert (len1 <= (ainfo->type->length ()
2791 - sinfo.field_type (0)->length ()));
2792
2793 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2794 &cinfo->float_regs,
2795 len1, offset))
2796 error (_("failed during argument setup"));
2797 return;
2798 }
2799
2800 if (sinfo.number_of_fields () == 2
2801 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2802 && (sinfo.field_type(0)->code () == TYPE_CODE_FLT
2803 && sinfo.field_type (0)->length () <= cinfo->flen
2804 && is_integral_type (sinfo.field_type (1))
2805 && sinfo.field_type (1)->length () <= cinfo->xlen))
2806 {
2807 int len0 = sinfo.field_type (0)->length ();
2808 int offset = sinfo.field_offset (0);
2809 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2810 &cinfo->float_regs, len0, offset))
2811 error (_("failed during argument setup"));
2812
2813 int len1 = sinfo.field_type (1)->length ();
2814 offset = sinfo.field_offset (1);
2815 gdb_assert (len1 <= cinfo->xlen);
2816 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2817 &cinfo->int_regs, len1, offset))
2818 error (_("failed during argument setup"));
2819 return;
2820 }
2821
2822 if (sinfo.number_of_fields () == 2
2823 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2824 && (is_integral_type (sinfo.field_type (0))
2825 && sinfo.field_type (0)->length () <= cinfo->xlen
2826 && sinfo.field_type(1)->code () == TYPE_CODE_FLT
2827 && sinfo.field_type (1)->length () <= cinfo->flen))
2828 {
2829 int len0 = sinfo.field_type (0)->length ();
2830 int len1 = sinfo.field_type (1)->length ();
2831
2832 gdb_assert (len0 <= cinfo->xlen);
2833 gdb_assert (len1 <= cinfo->flen);
2834
2835 int offset = sinfo.field_offset (0);
2836 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2837 &cinfo->int_regs, len0, offset))
2838 error (_("failed during argument setup"));
2839
2840 offset = sinfo.field_offset (1);
2841 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2842 &cinfo->float_regs,
2843 len1, offset))
2844 error (_("failed during argument setup"));
2845
2846 return;
2847 }
2848 }
2849
2850 /* Non of the structure flattening cases apply, so we just pass using
2851 the integer ABI. */
2852 riscv_call_arg_scalar_int (ainfo, cinfo);
2853}
2854
2855/* Assign a location to call (or return) argument AINFO, the location is
2856 selected from CINFO which holds information about what call argument
2857 locations are available for use next. The TYPE is the type of the
2858 argument being passed, this information is recorded into AINFO (along
2859 with some additional information derived from the type). IS_UNNAMED
2860 is true if this is an unnamed (stdarg) argument, this info is also
2861 recorded into AINFO.
2862
2863 After assigning a location to AINFO, CINFO will have been updated. */
2864
2865static void
2867 struct riscv_arg_info *ainfo,
2868 struct riscv_call_info *cinfo,
2869 struct type *type, bool is_unnamed)
2870{
2871 ainfo->type = type;
2872 ainfo->length = ainfo->type->length ();
2873 ainfo->align = type_align (ainfo->type);
2874 ainfo->is_unnamed = is_unnamed;
2875 ainfo->contents = nullptr;
2876 ainfo->argloc[0].c_length = 0;
2877 ainfo->argloc[1].c_length = 0;
2878
2879 switch (ainfo->type->code ())
2880 {
2881 case TYPE_CODE_INT:
2882 case TYPE_CODE_BOOL:
2883 case TYPE_CODE_CHAR:
2884 case TYPE_CODE_RANGE:
2885 case TYPE_CODE_ENUM:
2886 case TYPE_CODE_PTR:
2887 case TYPE_CODE_FIXED_POINT:
2888 if (ainfo->length <= cinfo->xlen)
2889 {
2891 ainfo->length = cinfo->xlen;
2892 }
2893 else if (ainfo->length <= (2 * cinfo->xlen))
2894 {
2896 ainfo->length = 2 * cinfo->xlen;
2897 }
2898
2899 /* Recalculate the alignment requirement. */
2900 ainfo->align = type_align (ainfo->type);
2901 riscv_call_arg_scalar_int (ainfo, cinfo);
2902 break;
2903
2904 case TYPE_CODE_FLT:
2905 riscv_call_arg_scalar_float (ainfo, cinfo);
2906 break;
2907
2908 case TYPE_CODE_COMPLEX:
2909 riscv_call_arg_complex_float (ainfo, cinfo);
2910 break;
2911
2912 case TYPE_CODE_STRUCT:
2913 riscv_call_arg_struct (ainfo, cinfo);
2914 break;
2915
2916 default:
2917 riscv_call_arg_scalar_int (ainfo, cinfo);
2918 break;
2919 }
2920}
2921
2922/* Used for printing debug information about the call argument location in
2923 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2924 addresses for the location of pass-by-reference and
2925 arguments-on-the-stack memory areas. */
2926
2927static void
2929 struct riscv_arg_info *info,
2930 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2931{
2932 gdb_printf (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2933 TYPE_SAFE_NAME (info->type), info->length, info->align);
2934 switch (info->argloc[0].loc_type)
2935 {
2938 (stream, ", register %s",
2939 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2940 if (info->argloc[0].c_length < info->length)
2941 {
2942 switch (info->argloc[1].loc_type)
2943 {
2946 (stream, ", register %s",
2948 info->argloc[1].loc_data.regno));
2949 break;
2950
2952 gdb_printf (stream, ", on stack at offset 0x%x",
2953 info->argloc[1].loc_data.offset);
2954 break;
2955
2957 default:
2958 /* The second location should never be a reference, any
2959 argument being passed by reference just places its address
2960 in the first location and is done. */
2961 error (_("invalid argument location"));
2962 break;
2963 }
2964
2965 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2966 gdb_printf (stream, " (offset 0x%x)",
2967 info->argloc[1].c_offset);
2968 }
2969 break;
2970
2972 gdb_printf (stream, ", on stack at offset 0x%x",
2973 info->argloc[0].loc_data.offset);
2974 break;
2975
2978 (stream, ", by reference, data at offset 0x%x (%s)",
2979 info->argloc[0].loc_data.offset,
2980 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2981 if (info->argloc[1].loc_type
2984 (stream, ", address in register %s",
2985 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2986 else
2987 {
2988 gdb_assert (info->argloc[1].loc_type
2991 (stream, ", address on stack at offset 0x%x (%s)",
2992 info->argloc[1].loc_data.offset,
2993 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2994 }
2995 break;
2996
2997 default:
2998 gdb_assert_not_reached ("unknown argument location type");
2999 }
3000}
3001
3002/* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA
3003 into a buffer that is at least as big as the register REGNUM, padding
3004 out the DATA with either 0x00, or 0xff. For floating point registers
3005 0xff is used, for everyone else 0x00 is used. */
3006
3007static void
3008riscv_regcache_cooked_write (int regnum, const gdb_byte *data, int len,
3009 struct regcache *regcache, int flen)
3010{
3011 gdb_byte tmp [sizeof (ULONGEST)];
3012
3013 /* FP values in FP registers must be NaN-boxed. */
3014 if (riscv_is_fp_regno_p (regnum) && len < flen)
3015 memset (tmp, -1, sizeof (tmp));
3016 else
3017 memset (tmp, 0, sizeof (tmp));
3018 memcpy (tmp, data, len);
3020}
3021
3022/* Implement the push dummy call gdbarch callback. */
3023
3024static CORE_ADDR
3026 struct value *function,
3027 struct regcache *regcache,
3028 CORE_ADDR bp_addr,
3029 int nargs,
3030 struct value **args,
3031 CORE_ADDR sp,
3032 function_call_return_method return_method,
3033 CORE_ADDR struct_addr)
3034{
3035 int i;
3036 CORE_ADDR sp_args, sp_refs;
3037 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3038
3039 struct riscv_arg_info *arg_info =
3040 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
3041
3042 struct riscv_call_info call_info (gdbarch);
3043
3044 CORE_ADDR osp = sp;
3045
3046 struct type *ftype = check_typedef (value_type (function));
3047
3048 if (ftype->code () == TYPE_CODE_PTR)
3049 ftype = check_typedef (ftype->target_type ());
3050
3051 /* We'll use register $a0 if we're returning a struct. */
3052 if (return_method == return_method_struct)
3053 ++call_info.int_regs.next_regnum;
3054
3055 for (i = 0; i < nargs; ++i)
3056 {
3057 struct value *arg_value;
3058 struct type *arg_type;
3059 struct riscv_arg_info *info = &arg_info[i];
3060
3061 arg_value = args[i];
3062 arg_type = check_typedef (value_type (arg_value));
3063
3064 riscv_arg_location (gdbarch, info, &call_info, arg_type,
3065 ftype->has_varargs () && i >= ftype->num_fields ());
3066
3067 if (info->type != arg_type)
3068 arg_value = value_cast (info->type, arg_value);
3069 info->contents = value_contents (arg_value).data ();
3070 }
3071
3072 /* Adjust the stack pointer and align it. */
3073 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
3074 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
3075
3076 if (riscv_debug_infcall > 0)
3077 {
3078 gdb_printf (gdb_stdlog, "dummy call args:\n");
3079 gdb_printf (gdb_stdlog, ": floating point ABI %s in use\n",
3080 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
3081 gdb_printf (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
3082 call_info.xlen, call_info.flen);
3083 if (return_method == return_method_struct)
3085 "[*] struct return pointer in register $A0\n");
3086 for (i = 0; i < nargs; ++i)
3087 {
3088 struct riscv_arg_info *info = &arg_info [i];
3089
3090 gdb_printf (gdb_stdlog, "[%2d] ", i);
3091 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
3092 gdb_printf (gdb_stdlog, "\n");
3093 }
3094 if (call_info.memory.arg_offset > 0
3095 || call_info.memory.ref_offset > 0)
3096 {
3097 gdb_printf (gdb_stdlog, " Original sp: %s\n",
3098 core_addr_to_string (osp));
3099 gdb_printf (gdb_stdlog, "Stack required (for args): 0x%x\n",
3100 call_info.memory.arg_offset);
3101 gdb_printf (gdb_stdlog, "Stack required (for refs): 0x%x\n",
3102 call_info.memory.ref_offset);
3103 gdb_printf (gdb_stdlog, " Stack allocated: %s\n",
3104 core_addr_to_string_nz (osp - sp));
3105 }
3106 }
3107
3108 /* Now load the argument into registers, or onto the stack. */
3109
3110 if (return_method == return_method_struct)
3111 {
3112 gdb_byte buf[sizeof (LONGEST)];
3113
3114 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
3116 }
3117
3118 for (i = 0; i < nargs; ++i)
3119 {
3120 CORE_ADDR dst;
3121 int second_arg_length = 0;
3122 const gdb_byte *second_arg_data;
3123 struct riscv_arg_info *info = &arg_info [i];
3124
3125 gdb_assert (info->length > 0);
3126
3127 switch (info->argloc[0].loc_type)
3128 {
3130 {
3131 gdb_assert (info->argloc[0].c_length <= info->length);
3132
3133 riscv_regcache_cooked_write (info->argloc[0].loc_data.regno,
3134 (info->contents
3135 + info->argloc[0].c_offset),
3136 info->argloc[0].c_length,
3137 regcache, call_info.flen);
3138 second_arg_length =
3139 (((info->argloc[0].c_length + info->argloc[0].c_offset) < info->length)
3140 ? info->argloc[1].c_length : 0);
3141 second_arg_data = info->contents + info->argloc[1].c_offset;
3142 }
3143 break;
3144
3146 dst = sp_args + info->argloc[0].loc_data.offset;
3147 write_memory (dst, info->contents, info->length);
3148 second_arg_length = 0;
3149 break;
3150
3152 dst = sp_refs + info->argloc[0].loc_data.offset;
3153 write_memory (dst, info->contents, info->length);
3154
3155 second_arg_length = call_info.xlen;
3156 second_arg_data = (gdb_byte *) &dst;
3157 break;
3158
3159 default:
3160 gdb_assert_not_reached ("unknown argument location type");
3161 }
3162
3163 if (second_arg_length > 0)
3164 {
3165 switch (info->argloc[1].loc_type)
3166 {
3168 {
3169 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
3170 && second_arg_length <= call_info.flen)
3171 || second_arg_length <= call_info.xlen);
3172 riscv_regcache_cooked_write (info->argloc[1].loc_data.regno,
3173 second_arg_data,
3174 second_arg_length,
3175 regcache, call_info.flen);
3176 }
3177 break;
3178
3180 {
3181 CORE_ADDR arg_addr;
3182
3183 arg_addr = sp_args + info->argloc[1].loc_data.offset;
3184 write_memory (arg_addr, second_arg_data, second_arg_length);
3185 break;
3186 }
3187
3189 default:
3190 /* The second location should never be a reference, any
3191 argument being passed by reference just places its address
3192 in the first location and is done. */
3193 error (_("invalid argument location"));
3194 break;
3195 }
3196 }
3197 }
3198
3199 /* Set the dummy return value to bp_addr.
3200 A dummy breakpoint will be setup to execute the call. */
3201
3202 if (riscv_debug_infcall > 0)
3203 gdb_printf (gdb_stdlog, ": writing $ra = %s\n",
3204 core_addr_to_string (bp_addr));
3206
3207 /* Finally, update the stack pointer. */
3208
3209 if (riscv_debug_infcall > 0)
3210 gdb_printf (gdb_stdlog, ": writing $sp = %s\n",
3211 core_addr_to_string (sp));
3213
3214 return sp;
3215}
3216
3217/* Implement the return_value gdbarch method. */
3218
3219static enum return_value_convention
3221 struct value *function,
3222 struct type *type,
3223 struct regcache *regcache,
3224 gdb_byte *readbuf,
3225 const gdb_byte *writebuf)
3226{
3227 struct riscv_call_info call_info (gdbarch);
3228 struct riscv_arg_info info;
3229 struct type *arg_type;
3230
3231 arg_type = check_typedef (type);
3232 riscv_arg_location (gdbarch, &info, &call_info, arg_type, false);
3233
3234 if (riscv_debug_infcall > 0)
3235 {
3236 gdb_printf (gdb_stdlog, "riscv return value:\n");
3237 gdb_printf (gdb_stdlog, "[R] ");
3239 gdb_printf (gdb_stdlog, "\n");
3240 }
3241
3242 if (readbuf != nullptr || writebuf != nullptr)
3243 {
3244 unsigned int arg_len;
3245 struct value *abi_val;
3246 gdb_byte *old_readbuf = nullptr;
3247 int regnum;
3248
3249 /* We only do one thing at a time. */
3250 gdb_assert (readbuf == nullptr || writebuf == nullptr);
3251
3252 /* In some cases the argument is not returned as the declared type,
3253 and we need to cast to or from the ABI type in order to
3254 correctly access the argument. When writing to the machine we
3255 do the cast here, when reading from the machine the cast occurs
3256 later, after extracting the value. As the ABI type can be
3257 larger than the declared type, then the read or write buffers
3258 passed in might be too small. Here we ensure that we are using
3259 buffers of sufficient size. */
3260 if (writebuf != nullptr)
3261 {
3262 struct value *arg_val;
3263
3264 if (is_fixed_point_type (arg_type))
3265 {
3266 /* Convert the argument to the type used to pass
3267 the return value, but being careful to preserve
3268 the fact that the value needs to be returned
3269 unscaled. */
3270 gdb_mpz unscaled;
3271
3272 unscaled.read (gdb::make_array_view (writebuf,
3273 arg_type->length ()),
3274 type_byte_order (arg_type),
3275 arg_type->is_unsigned ());
3276 abi_val = allocate_value (info.type);
3277 unscaled.write (value_contents_raw (abi_val),
3278 type_byte_order (info.type),
3279 info.type->is_unsigned ());
3280 }
3281 else
3282 {
3283 arg_val = value_from_contents (arg_type, writebuf);
3284 abi_val = value_cast (info.type, arg_val);
3285 }
3286 writebuf = value_contents_raw (abi_val).data ();
3287 }
3288 else
3289 {
3290 abi_val = allocate_value (info.type);
3291 old_readbuf = readbuf;
3292 readbuf = value_contents_raw (abi_val).data ();
3293 }
3294 arg_len = info.type->length ();
3295
3296 switch (info.argloc[0].loc_type)
3297 {
3298 /* Return value in register(s). */
3300 {
3301 regnum = info.argloc[0].loc_data.regno;
3302 gdb_assert (info.argloc[0].c_length <= arg_len);
3303 gdb_assert (info.argloc[0].c_length
3305
3306 if (readbuf)
3307 {
3308 gdb_byte *ptr = readbuf + info.argloc[0].c_offset;
3310 info.argloc[0].c_length,
3311 ptr);
3312 }
3313
3314 if (writebuf)
3315 {
3316 const gdb_byte *ptr = writebuf + info.argloc[0].c_offset;
3318 info.argloc[0].c_length,
3319 regcache, call_info.flen);
3320 }
3321
3322 /* A return value in register can have a second part in a
3323 second register. */
3324 if (info.argloc[1].c_length > 0)
3325 {
3326 switch (info.argloc[1].loc_type)
3327 {
3329 regnum = info.argloc[1].loc_data.regno;
3330
3331 gdb_assert ((info.argloc[0].c_length
3332 + info.argloc[1].c_length) <= arg_len);
3333 gdb_assert (info.argloc[1].c_length
3335
3336 if (readbuf)
3337 {
3338 readbuf += info.argloc[1].c_offset;
3340 info.argloc[1].c_length,
3341 readbuf);
3342 }
3343
3344 if (writebuf)
3345 {
3346 const gdb_byte *ptr
3347 = writebuf + info.argloc[1].c_offset;
3349 (regnum, ptr, info.argloc[1].c_length,
3350 regcache, call_info.flen);
3351 }
3352 break;
3353
3356 default:
3357 error (_("invalid argument location"));
3358 break;
3359 }
3360 }
3361 }
3362 break;
3363
3364 /* Return value by reference will have its address in A0. */
3366 {
3367 ULONGEST addr;
3368
3370 &addr);
3371 if (readbuf != nullptr)
3372 read_memory (addr, readbuf, info.length);
3373 if (writebuf != nullptr)
3374 write_memory (addr, writebuf, info.length);
3375 }
3376 break;
3377
3379 default:
3380 error (_("invalid argument location"));
3381 break;
3382 }
3383
3384 /* This completes the cast from abi type back to the declared type
3385 in the case that we are reading from the machine. See the
3386 comment at the head of this block for more details. */
3387 if (readbuf != nullptr)
3388 {
3389 struct value *arg_val;
3390
3391 if (is_fixed_point_type (arg_type))
3392 {
3393 /* Convert abi_val to the actual return type, but
3394 being careful to preserve the fact that abi_val
3395 is unscaled. */
3396 gdb_mpz unscaled;
3397
3398 unscaled.read (value_contents (abi_val),
3399 type_byte_order (info.type),
3400 info.type->is_unsigned ());
3401 arg_val = allocate_value (arg_type);
3402 unscaled.write (value_contents_raw (arg_val),
3403 type_byte_order (arg_type),
3404 arg_type->is_unsigned ());
3405 }
3406 else
3407 arg_val = value_cast (arg_type, abi_val);
3408 memcpy (old_readbuf, value_contents_raw (arg_val).data (),
3409 arg_type->length ());
3410 }
3411 }
3412
3413 switch (info.argloc[0].loc_type)
3414 {
3420 default:
3421 error (_("invalid argument location"));
3422 }
3423}
3424
3425/* Implement the frame_align gdbarch method. */
3426
3427static CORE_ADDR
3428riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
3429{
3430 return align_down (addr, 16);
3431}
3432
3433/* Generate, or return the cached frame cache for the RiscV frame
3434 unwinder. */
3435
3436static struct riscv_unwind_cache *
3437riscv_frame_cache (frame_info_ptr this_frame, void **this_cache)
3438{
3439 CORE_ADDR pc, start_addr;
3440 struct riscv_unwind_cache *cache;
3441 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3442 int numregs, regno;
3443
3444 if ((*this_cache) != NULL)
3445 return (struct riscv_unwind_cache *) *this_cache;
3446
3448 cache->regs = trad_frame_alloc_saved_regs (this_frame);
3449 (*this_cache) = cache;
3450
3451 /* Scan the prologue, filling in the cache. */
3452 start_addr = get_frame_func (this_frame);
3453 pc = get_frame_pc (this_frame);
3454 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
3455
3456 /* We can now calculate the frame base address. */
3457 cache->frame_base
3458 = (get_frame_register_unsigned (this_frame, cache->frame_base_reg)
3459 + cache->frame_base_offset);
3461 gdb_printf (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
3462 core_addr_to_string (cache->frame_base),
3464 cache->frame_base_reg),
3465 cache->frame_base_offset);
3466
3467 /* The prologue scanner sets the address of registers stored to the stack
3468 as the offset of that register from the frame base. The prologue
3469 scanner doesn't know the actual frame base value, and so is unable to
3470 compute the exact address. We do now know the frame base value, so
3471 update the address of registers stored to the stack. */
3473 for (regno = 0; regno < numregs; ++regno)
3474 {
3475 if (cache->regs[regno].is_addr ())
3476 cache->regs[regno].set_addr (cache->regs[regno].addr ()
3477 + cache->frame_base);
3478 }
3479
3480 /* The previous $pc can be found wherever the $ra value can be found.
3481 The previous $ra value is gone, this would have been stored be the
3482 previous frame if required. */
3484 cache->regs[RISCV_RA_REGNUM].set_unknown ();
3485
3486 /* Build the frame id. */
3487 cache->this_id = frame_id_build (cache->frame_base, start_addr);
3488
3489 /* The previous $sp value is the frame base value. */
3491
3492 return cache;
3493}
3494
3495/* Implement the this_id callback for RiscV frame unwinder. */
3496
3497static void
3499 void **prologue_cache,
3500 struct frame_id *this_id)
3501{
3502 struct riscv_unwind_cache *cache;
3503
3504 try
3505 {
3506 cache = riscv_frame_cache (this_frame, prologue_cache);
3507 *this_id = cache->this_id;
3508 }
3509 catch (const gdb_exception_error &ex)
3510 {
3511 /* Ignore errors, this leaves the frame id as the predefined outer
3512 frame id which terminates the backtrace at this point. */
3513 }
3514}
3515
3516/* Implement the prev_register callback for RiscV frame unwinder. */
3517
3518static struct value *
3520 void **prologue_cache,
3521 int regnum)
3522{
3523 struct riscv_unwind_cache *cache;
3524
3525 cache = riscv_frame_cache (this_frame, prologue_cache);
3526 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
3527}
3528
3529/* Structure defining the RiscV normal frame unwind functions. Since we
3530 are the fallback unwinder (DWARF unwinder is used first), we use the
3531 default frame sniffer, which always accepts the frame. */
3532
3534{
3535 /*.name =*/ "riscv prologue",
3536 /*.type =*/ NORMAL_FRAME,
3537 /*.stop_reason =*/ default_frame_unwind_stop_reason,
3538 /*.this_id =*/ riscv_frame_this_id,
3539 /*.prev_register =*/ riscv_frame_prev_register,
3540 /*.unwind_data =*/ NULL,
3541 /*.sniffer =*/ default_frame_sniffer,
3542 /*.dealloc_cache =*/ NULL,
3543 /*.prev_arch =*/ NULL,
3544};
3545
3546/* Extract a set of required target features out of ABFD. If ABFD is
3547 nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state. */
3548
3549static struct riscv_gdbarch_features
3551{
3552 struct riscv_gdbarch_features features;
3553
3554 /* Now try to improve on the defaults by looking at the binary we are
3555 going to execute. We assume the user knows what they are doing and
3556 that the target will match the binary. Remember, this code path is
3557 only used at all if the target hasn't given us a description, so this
3558 is really a last ditched effort to do something sane before giving
3559 up. */
3560 if (abfd != nullptr && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
3561 {
3562 unsigned char eclass = elf_elfheader (abfd)->e_ident[EI_CLASS];
3563 int e_flags = elf_elfheader (abfd)->e_flags;
3564
3565 if (eclass == ELFCLASS32)
3566 features.xlen = 4;
3567 else if (eclass == ELFCLASS64)
3568 features.xlen = 8;
3569 else
3570 internal_error (_("unknown ELF header class %d"), eclass);
3571
3572 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
3573 features.flen = 8;
3574 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
3575 features.flen = 4;
3576
3577 if (e_flags & EF_RISCV_RVE)
3578 {
3579 if (features.xlen == 8)
3580 {
3581 warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit"));
3582 features.xlen = 4;
3583 }
3584 features.embedded = true;
3585 }
3586 }
3587
3588 return features;
3589}
3590
3591/* Find a suitable default target description. Use the contents of INFO,
3592 specifically the bfd object being executed, to guide the selection of a
3593 suitable default target description. */
3594
3595static const struct target_desc *
3597{
3598 /* Extract desired feature set from INFO. */
3599 struct riscv_gdbarch_features features
3600 = riscv_features_from_bfd (info.abfd);
3601
3602 /* If the XLEN field is still 0 then we got nothing useful from INFO.BFD,
3603 maybe there was no bfd object. In this case we fall back to a minimal
3604 useful target with no floating point, the x-register size is selected
3605 based on the architecture from INFO. */
3606 if (features.xlen == 0)
3607 features.xlen = info.bfd_arch_info->bits_per_word == 32 ? 4 : 8;
3608
3609 /* Now build a target description based on the feature set. */
3610 return riscv_lookup_target_description (features);
3611}
3612
3613/* Add all the RISC-V specific register groups into GDBARCH. */
3614
3615static void
3617{
3619}
3620
3621/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3622
3623static int
3625{
3626 if (reg <= RISCV_DWARF_REGNUM_X31)
3628
3629 else if (reg <= RISCV_DWARF_REGNUM_F31)
3631
3632 else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR)
3634
3635 else if (reg >= RISCV_DWARF_REGNUM_V0 && reg <= RISCV_DWARF_REGNUM_V31)
3636 return RISCV_V0_REGNUM + (reg - RISCV_DWARF_REGNUM_V0);
3637
3638 return -1;
3639}
3640
3641/* Implement the gcc_target_options method. We have to select the arch and abi
3642 from the feature info. We have enough feature info to select the abi, but
3643 not enough info for the arch given all of the possible architecture
3644 extensions. So choose reasonable defaults for now. */
3645
3646static std::string
3648{
3649 int isa_xlen = riscv_isa_xlen (gdbarch);
3650 int isa_flen = riscv_isa_flen (gdbarch);
3651 int abi_xlen = riscv_abi_xlen (gdbarch);
3652 int abi_flen = riscv_abi_flen (gdbarch);
3653 std::string target_options;
3654
3655 target_options = "-march=rv";
3656 if (isa_xlen == 8)
3657 target_options += "64";
3658 else
3659 target_options += "32";
3660 if (isa_flen == 8)
3661 target_options += "gc";
3662 else if (isa_flen == 4)
3663 target_options += "imafc";
3664 else
3665 target_options += "imac";
3666
3667 target_options += " -mabi=";
3668 if (abi_xlen == 8)
3669 target_options += "lp64";
3670 else
3671 target_options += "ilp32";
3672 if (abi_flen == 8)
3673 target_options += "d";
3674 else if (abi_flen == 4)
3675 target_options += "f";
3676
3677 /* The gdb loader doesn't handle link-time relaxation relocations. */
3678 target_options += " -mno-relax";
3679
3680 return target_options;
3681}
3682
3683/* Call back from tdesc_use_registers, called for each unknown register
3684 found in the target description.
3685
3686 See target-description.h (typedef tdesc_unknown_register_ftype) for a
3687 discussion of the arguments and return values. */
3688
3689static int
3691 const char *reg_name, int possible_regnum)
3692{
3693 /* At one point in time GDB had an incorrect default target description
3694 that duplicated the fflags, frm, and fcsr registers in both the FPU
3695 and CSR register sets.
3696
3697 Some targets (QEMU) copied these target descriptions into their source
3698 tree, and so we're now stuck working with some versions of QEMU that
3699 declare the same registers twice.
3700
3701 To make matters worse, if GDB tries to read or write to these
3702 registers using the register number assigned in the FPU feature set,
3703 then QEMU will fail to read the register, so we must use the register
3704 number declared in the CSR feature set.
3705
3706 Luckily, GDB scans the FPU feature first, and then the CSR feature,
3707 which means that the CSR feature will be the one we end up using, the
3708 versions of these registers in the FPU feature will appear as unknown
3709 registers and will be passed through to this code.
3710
3711 To prevent these duplicate registers showing up in any of the register
3712 lists, and to prevent GDB every trying to access the FPU feature copies,
3713 we spot the three problematic registers here, and record the register
3714 number that GDB has assigned them. Then in riscv_register_name we will
3715 return no name for the three duplicates, this hides the duplicates from
3716 the user. */
3717 if (strcmp (tdesc_feature_name (feature), riscv_freg_feature.name ()) == 0)
3718 {
3719 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
3720 int *regnum_ptr = nullptr;
3721
3722 if (strcmp (reg_name, "fflags") == 0)
3723 regnum_ptr = &tdep->duplicate_fflags_regnum;
3724 else if (strcmp (reg_name, "frm") == 0)
3725 regnum_ptr = &tdep->duplicate_frm_regnum;
3726 else if (strcmp (reg_name, "fcsr") == 0)
3727 regnum_ptr = &tdep->duplicate_fcsr_regnum;
3728
3729 if (regnum_ptr != nullptr)
3730 {
3731 /* This means the register appears more than twice in the target
3732 description. Just let GDB add this as another register.
3733 We'll have duplicates in the register name list, but there's
3734 not much more we can do. */
3735 if (*regnum_ptr != -1)
3736 return -1;
3737
3738 /* Record the number assigned to this register, then return the
3739 number (so it actually gets assigned to this register). */
3740 *regnum_ptr = possible_regnum;
3741 return possible_regnum;
3742 }
3743 }
3744
3745 /* Any unknown registers in the CSR feature are recorded within a single
3746 block so we can easily identify these registers when making choices
3747 about register groups in riscv_register_reggroup_p. */
3748 if (strcmp (tdesc_feature_name (feature), riscv_csr_feature.name ()) == 0)
3749 {
3750 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
3751 if (tdep->unknown_csrs_first_regnum == -1)
3752 tdep->unknown_csrs_first_regnum = possible_regnum;
3753 gdb_assert (tdep->unknown_csrs_first_regnum
3754 + tdep->unknown_csrs_count == possible_regnum);
3755 tdep->unknown_csrs_count++;
3756 return possible_regnum;
3757 }
3758
3759 /* Some other unknown register. Don't assign this a number now, it will
3760 be assigned a number automatically later by the target description
3761 handling code. */
3762 return -1;
3763}
3764
3765/* Implement the gnu_triplet_regexp method. A single compiler supports both
3766 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
3767 recommended) riscv. */
3768
3769static const char *
3771{
3772 return "riscv(32|64)?";
3773}
3774
3775/* Initialize the current architecture based on INFO. If possible,
3776 re-use an architecture from ARCHES, which is a list of
3777 architectures already created during this debugging session.
3778
3779 Called e.g. at program startup, when reading a core file, and when
3780 reading a binary file. */
3781
3782static struct gdbarch *
3784 struct gdbarch_list *arches)
3785{
3786 struct gdbarch *gdbarch;
3787 struct riscv_gdbarch_features features;
3788 const struct target_desc *tdesc = info.target_desc;
3789
3790 /* Ensure we always have a target description. */
3791 if (!tdesc_has_registers (tdesc))
3793 gdb_assert (tdesc != nullptr);
3794
3796 gdb_printf (gdb_stdlog, "Have got a target description\n");
3797
3799 std::vector<riscv_pending_register_alias> pending_aliases;
3800
3801 bool valid_p = (riscv_xreg_feature.check (tdesc, tdesc_data.get (),
3802 &pending_aliases, &features)
3803 && riscv_freg_feature.check (tdesc, tdesc_data.get (),
3804 &pending_aliases, &features)
3806 &pending_aliases, &features)
3807 && riscv_csr_feature.check (tdesc, tdesc_data.get (),
3808 &pending_aliases, &features)
3810 &pending_aliases, &features));
3811 if (!valid_p)
3812 {
3814 gdb_printf (gdb_stdlog, "Target description is not valid\n");
3815 return NULL;
3816 }
3817
3818 if (tdesc_found_register (tdesc_data.get (), RISCV_CSR_FFLAGS_REGNUM))
3819 features.has_fflags_reg = true;
3820 if (tdesc_found_register (tdesc_data.get (), RISCV_CSR_FRM_REGNUM))
3821 features.has_frm_reg = true;
3822 if (tdesc_found_register (tdesc_data.get (), RISCV_CSR_FCSR_REGNUM))
3823 features.has_fcsr_reg = true;
3824
3825 /* Have a look at what the supplied (if any) bfd object requires of the
3826 target, then check that this matches with what the target is
3827 providing. */
3828 struct riscv_gdbarch_features abi_features
3829 = riscv_features_from_bfd (info.abfd);
3830
3831 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3832 features from the INFO object. In this case we just treat the
3833 hardware features as defining the abi. */
3834 if (abi_features.xlen == 0)
3835 abi_features = features;
3836
3837 /* In theory a binary compiled for RV32 could run on an RV64 target,
3838 however, this has not been tested in GDB yet, so for now we require
3839 that the requested xlen match the targets xlen. */
3840 if (abi_features.xlen != features.xlen)
3841 error (_("bfd requires xlen %d, but target has xlen %d"),
3842 abi_features.xlen, features.xlen);
3843 /* We do support running binaries compiled for 32-bit float on targets
3844 with 64-bit float, so we only complain if the binary requires more
3845 than the target has available. */
3846 if (abi_features.flen > features.flen)
3847 error (_("bfd requires flen %d, but target has flen %d"),
3848 abi_features.flen, features.flen);
3849
3850 /* Find a candidate among the list of pre-declared architectures. */
3852 arches != NULL;
3853 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3854 {
3855 /* Check that the feature set of the ARCHES matches the feature set
3856 we are looking for. If it doesn't then we can't reuse this
3857 gdbarch. */
3858 riscv_gdbarch_tdep *other_tdep
3859 = gdbarch_tdep<riscv_gdbarch_tdep> (arches->gdbarch);
3860
3861 if (other_tdep->isa_features != features
3862 || other_tdep->abi_features != abi_features)
3863 continue;
3864
3865 break;
3866 }
3867
3868 if (arches != NULL)
3869 return arches->gdbarch;
3870
3871 /* None found, so create a new architecture from the information provided. */
3873 gdbarch = gdbarch_alloc (&info, tdep);
3874 tdep->isa_features = features;
3875 tdep->abi_features = abi_features;
3876
3877 /* Target data types. */
3889
3890 /* Information about the target architecture. */
3895
3896 /* Functions to analyze frames. */
3900
3901 /* Functions handling dummy frames. */
3905
3906 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3907 unwinder. */
3910
3911 /* Register architecture. */
3913
3914 /* Internal <-> external register number maps. */
3916
3917 /* We reserve all possible register numbers for the known registers.
3918 This means the target description mechanism will add any target
3919 specific registers after this number. This helps make debugging GDB
3920 just a little easier. */
3922
3923 /* Some specific register numbers GDB likes to know about. */
3926
3928
3935
3936 /* Finalise the target description registers. */
3937 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data),
3939
3940 /* Calculate the number of pseudo registers we need. The fflags and frm
3941 registers are sub-fields of the fcsr CSR register (csr3). However,
3942 these registers can also be accessed directly as separate CSR
3943 registers (fflags is csr1, and frm is csr2). And so, some targets
3944 might choose to offer direct access to all three registers in the
3945 target description, while other targets might choose to only offer
3946 access to fcsr.
3947
3948 As we scan the target description we spot which of fcsr, fflags, and
3949 frm are available. If fcsr is available but either of fflags and/or
3950 frm are not available, then we add pseudo-registers to provide the
3951 missing functionality.
3952
3953 This has to be done after the call to tdesc_use_registers as we don't
3954 know the final register number until after that call, and the pseudo
3955 register numbers need to be after the physical registers. */
3956 int num_pseudo_regs = 0;
3957 int next_pseudo_regnum = gdbarch_num_regs (gdbarch);
3958
3959 if (features.has_fflags_reg)
3960 tdep->fflags_regnum = RISCV_CSR_FFLAGS_REGNUM;
3961 else if (features.has_fcsr_reg)
3962 {
3963 tdep->fflags_regnum = next_pseudo_regnum;
3964 pending_aliases.emplace_back ("csr1", (void *) &tdep->fflags_regnum);
3965 next_pseudo_regnum++;
3966 num_pseudo_regs++;
3967 }
3968
3969 if (features.has_frm_reg)
3970 tdep->frm_regnum = RISCV_CSR_FRM_REGNUM;
3971 else if (features.has_fcsr_reg)
3972 {
3973 tdep->frm_regnum = next_pseudo_regnum;
3974 pending_aliases.emplace_back ("csr2", (void *) &tdep->frm_regnum);
3975 next_pseudo_regnum++;
3976 num_pseudo_regs++;
3977 }
3978
3979 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3980
3981 /* Override the register type callback setup by the target description
3982 mechanism. This allows us to provide special type for floating point
3983 registers. */
3985
3986 /* Override the register name callback setup by the target description
3987 mechanism. This allows us to force our preferred names for the
3988 registers, no matter what the target description called them. */
3990
3991 /* Tell GDB which RISC-V registers are read-only. */
3993
3994 /* Override the register group callback setup by the target description
3995 mechanism. This allows us to force registers into the groups we
3996 want, ignoring what the target tells us. */
3998
3999 /* Create register aliases for alternative register names. We only
4000 create aliases for registers which were mentioned in the target
4001 description. */
4002 for (const auto &alias : pending_aliases)
4003 alias.create (gdbarch);
4004
4005 /* Compile command hooks. */
4008
4009 /* Disassembler options support. */
4011 disassembler_options_riscv ());
4013
4014 /* Hook in OS ABI-specific overrides, if they have been registered. */
4016
4018
4019 return gdbarch;
4020}
4021
4022/* This decodes the current instruction and determines the address of the
4023 next instruction. */
4024
4025static CORE_ADDR
4026riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
4027{
4028 struct gdbarch *gdbarch = regcache->arch ();
4029 const riscv_gdbarch_tdep *tdep
4030 = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
4031 struct riscv_insn insn;
4032 CORE_ADDR next_pc;
4033
4034 insn.decode (gdbarch, pc);
4035 next_pc = pc + insn.length ();
4036
4037 if (insn.opcode () == riscv_insn::JAL)
4038 next_pc = pc + insn.imm_signed ();
4039 else if (insn.opcode () == riscv_insn::JALR)
4040 {
4041 LONGEST source;
4042 regcache->cooked_read (insn.rs1 (), &source);
4043 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
4044 }
4045 else if (insn.opcode () == riscv_insn::BEQ)
4046 {
4047 LONGEST src1, src2;
4048 regcache->cooked_read (insn.rs1 (), &src1);
4049 regcache->cooked_read (insn.rs2 (), &src2);
4050 if (src1 == src2)
4051 next_pc = pc + insn.imm_signed ();
4052 }
4053 else if (insn.opcode () == riscv_insn::BNE)
4054 {
4055 LONGEST src1, src2;
4056 regcache->cooked_read (insn.rs1 (), &src1);
4057 regcache->cooked_read (insn.rs2 (), &src2);
4058 if (src1 != src2)
4059 next_pc = pc + insn.imm_signed ();
4060 }
4061 else if (insn.opcode () == riscv_insn::BLT)
4062 {
4063 LONGEST src1, src2;
4064 regcache->cooked_read (insn.rs1 (), &src1);
4065 regcache->cooked_read (insn.rs2 (), &src2);
4066 if (src1 < src2)
4067 next_pc = pc + insn.imm_signed ();
4068 }
4069 else if (insn.opcode () == riscv_insn::BGE)
4070 {
4071 LONGEST src1, src2;
4072 regcache->cooked_read (insn.rs1 (), &src1);
4073 regcache->cooked_read (insn.rs2 (), &src2);
4074 if (src1 >= src2)
4075 next_pc = pc + insn.imm_signed ();
4076 }
4077 else if (insn.opcode () == riscv_insn::BLTU)
4078 {
4079 ULONGEST src1, src2;
4080 regcache->cooked_read (insn.rs1 (), &src1);
4081 regcache->cooked_read (insn.rs2 (), &src2);
4082 if (src1 < src2)
4083 next_pc = pc + insn.imm_signed ();
4084 }
4085 else if (insn.opcode () == riscv_insn::BGEU)
4086 {
4087 ULONGEST src1, src2;
4088 regcache->cooked_read (insn.rs1 (), &src1);
4089 regcache->cooked_read (insn.rs2 (), &src2);
4090 if (src1 >= src2)
4091 next_pc = pc + insn.imm_signed ();
4092 }
4093 else if (insn.opcode () == riscv_insn::ECALL)
4094 {
4095 if (tdep->syscall_next_pc != nullptr)
4096 next_pc = tdep->syscall_next_pc (get_current_frame ());
4097 }
4098
4099 return next_pc;
4100}
4101
4102/* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
4103 for the end of the sequence and put the breakpoint there. */
4104
4105static bool
4107 CORE_ADDR *next_pc)
4108{
4109 struct gdbarch *gdbarch = regcache->arch ();
4110 struct riscv_insn insn;
4111 CORE_ADDR cur_step_pc = pc;
4112 CORE_ADDR last_addr = 0;
4113
4114 /* First instruction has to be a load reserved. */
4115 insn.decode (gdbarch, cur_step_pc);
4116 if (insn.opcode () != riscv_insn::LR)
4117 return false;
4118 cur_step_pc = cur_step_pc + insn.length ();
4119
4120 /* Next instruction should be branch to exit. */
4121 insn.decode (gdbarch, cur_step_pc);
4122 if (insn.opcode () != riscv_insn::BNE)
4123 return false;
4124 last_addr = cur_step_pc + insn.imm_signed ();
4125 cur_step_pc = cur_step_pc + insn.length ();
4126
4127 /* Next instruction should be store conditional. */
4128 insn.decode (gdbarch, cur_step_pc);
4129 if (insn.opcode () != riscv_insn::SC)
4130 return false;
4131 cur_step_pc = cur_step_pc + insn.length ();
4132
4133 /* Next instruction should be branch to start. */
4134 insn.decode (gdbarch, cur_step_pc);
4135 if (insn.opcode () != riscv_insn::BNE)
4136 return false;
4137 if (pc != (cur_step_pc + insn.imm_signed ()))
4138 return false;
4139 cur_step_pc = cur_step_pc + insn.length ();
4140
4141 /* We should now be at the end of the sequence. */
4142 if (cur_step_pc != last_addr)
4143 return false;
4144
4145 *next_pc = cur_step_pc;
4146 return true;
4147}
4148
4149/* This is called just before we want to resume the inferior, if we want to
4150 single-step it but there is no hardware or kernel single-step support. We
4151 find the target of the coming instruction and breakpoint it. */
4152
4153std::vector<CORE_ADDR>
4155{
4156 CORE_ADDR pc, next_pc;
4157
4159
4160 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
4161 return {next_pc};
4162
4163 next_pc = riscv_next_pc (regcache, pc);
4164
4165 return {next_pc};
4166}
4167
4168/* Create RISC-V specific reggroups. */
4169
4170static void
4172{
4174}
4175
4176/* See riscv-tdep.h. */
4177
4178void
4180 struct regcache *regcache, int regnum,
4181 const void *regs, size_t len)
4182{
4183 regcache->supply_regset (regset, regnum, regs, len);
4184
4185 if (regnum == -1 || regnum == RISCV_ZERO_REGNUM)
4187
4188 struct gdbarch *gdbarch = regcache->arch ();
4189 riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
4190
4191 if (regnum == -1
4192 || regnum == tdep->fflags_regnum
4193 || regnum == tdep->frm_regnum)
4194 {
4195 int fcsr_regnum = RISCV_CSR_FCSR_REGNUM;
4196
4197 /* Ensure that FCSR has been read into REGCACHE. */
4198 if (regnum != -1)
4199 regcache->supply_regset (regset, fcsr_regnum, regs, len);
4200
4201 /* Grab the FCSR value if it is now in the regcache. We must check
4202 the status first as, if the register was not supplied by REGSET,
4203 this call will trigger a recursive attempt to fetch the
4204 registers. */
4205 if (regcache->get_register_status (fcsr_regnum) == REG_VALID)
4206 {
4207 /* If we have an fcsr register then we should have fflags and frm
4208 too, either provided by the target, or provided as a pseudo
4209 register by GDB. */
4210 gdb_assert (tdep->fflags_regnum >= 0);
4211 gdb_assert (tdep->frm_regnum >= 0);
4212
4213 ULONGEST fcsr_val;
4214 regcache->raw_read (fcsr_regnum, &fcsr_val);
4215
4216 /* Extract the fflags and frm values. */
4217 ULONGEST fflags_val = fcsr_val & 0x1f;
4218 ULONGEST frm_val = (fcsr_val >> 5) & 0x7;
4219
4220 /* And supply these if needed. We can only supply real
4221 registers, so don't try to supply fflags or frm if they are
4222 implemented as pseudo-registers. */
4223 if ((regnum == -1 || regnum == tdep->fflags_regnum)
4226 (gdb_byte *) &fflags_val,
4227 sizeof (fflags_val),
4228 /* is_signed */ false);
4229
4230 if ((regnum == -1 || regnum == tdep->frm_regnum)
4231 && tdep->frm_regnum < gdbarch_num_regs (gdbarch))
4233 (gdb_byte *)&frm_val,
4234 sizeof (fflags_val),
4235 /* is_signed */ false);
4236 }
4237 }
4238}
4239
4241void
4243{
4245
4246 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
4247
4248 /* Add root prefix command for all "set debug riscv" and "show debug
4249 riscv" commands. */
4251 _("RISC-V specific debug commands."),
4252 _("RISC-V specific debug commands."),
4255
4258Set riscv breakpoint debugging."), _("\
4259Show riscv breakpoint debugging."), _("\
4260When non-zero, print debugging information for the riscv specific parts\n\
4261of the breakpoint mechanism."),
4262 NULL,
4265
4267 &riscv_debug_infcall, _("\
4268Set riscv inferior call debugging."), _("\
4269Show riscv inferior call debugging."), _("\
4270When non-zero, print debugging information for the riscv specific parts\n\
4271of the inferior call mechanism."),
4272 NULL,
4275
4278Set riscv stack unwinding debugging."), _("\
4279Show riscv stack unwinding debugging."), _("\
4280When non-zero, print debugging information for the riscv specific parts\n\
4281of the stack unwinding mechanism."),
4282 NULL,
4285
4287 &riscv_debug_gdbarch, _("\
4288Set riscv gdbarch initialisation debugging."), _("\
4289Show riscv gdbarch initialisation debugging."), _("\
4290When non-zero, print debugging information for the riscv gdbarch\n\
4291initialisation process."),
4292 NULL,
4295
4296 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
4298 _("RISC-V specific commands."),
4299 _("RISC-V specific commands."),
4301 &setlist, &showlist);
4302
4303
4305 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
4307 _("\
4308Set debugger's use of compressed breakpoints."), _(" \
4309Show debugger's use of compressed breakpoints."), _("\
4310Debugging compressed code requires compressed breakpoints to be used. If\n\
4311left to 'auto' then gdb will use them if the existing instruction is a\n\
4312compressed instruction. If that doesn't give the correct behavior, then\n\
4313this option can be used."),
4314 NULL,
4318}
@ ADD
Definition: aarch64-insn.h:102
int regnum
Definition: aarch64-tdep.c:68
const char *const name
Definition: aarch64-tdep.c:67
gdb_static_assert(sizeof(splay_tree_key) >=sizeof(CORE_ADDR *))
static std::vector< const char * > arches
Definition: arch-utils.c:685
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep)
Definition: arch-utils.c:1256
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition: arch-utils.c:177
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
Definition: arch-utils.c:1298
void f()
Definition: 1.cc:36
bool find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr, const struct block **block)
Definition: blockframe.c:373
pv_t fetch(pv_t addr, CORE_ADDR size)
bool find_reg(struct gdbarch *gdbarch, int reg, CORE_ADDR *offset_p)
void store(pv_t addr, CORE_ADDR size, pv_t value)
enum register_status raw_read(int regnum, gdb_byte *buf)
Definition: regcache.c:605
enum register_status cooked_read_part(int regnum, int offset, int len, gdb_byte *buf)
Definition: regcache.c:1033
enum register_status raw_read_part(int regnum, int offset, int len, gdb_byte *buf)
Definition: regcache.c:1013
enum register_status cooked_read(int regnum, gdb_byte *buf)
Definition: regcache.c:692
gdbarch * arch() const
Definition: regcache.c:230
void raw_supply_integer(int regnum, const gdb_byte *addr, int addr_len, bool is_signed)
Definition: regcache.c:1081
enum register_status get_register_status(int regnum) const override
Definition: regcache.c:303
void raw_supply_zeroed(int regnum)
Definition: regcache.c:1101
void cooked_write(int regnum, const gdb_byte *buf)
Definition: regcache.c:861
void raw_write(int regnum, const gdb_byte *buf)
Definition: regcache.c:827
void supply_regset(const struct regset *regset, int regbase, int regnum, const void *buf, size_t size)
Definition: regcache.c:1252
void * get(unsigned key)
Definition: registry.h:211
int rs1() const
Definition: riscv-tdep.c:1585
void decode_cj_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1707
enum opcode m_opcode
Definition: riscv-tdep.c:1737
void decode_s_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1657
void decode_b_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1713
void decode_u_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1691
void decode_cr_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1623
void decode_i_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1631
int decode_register_index(unsigned long opcode, int offset)
Definition: riscv-tdep.c:1602
void decode_j_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1699
int imm_signed() const
Definition: riscv-tdep.c:1596
enum opcode opcode() const
Definition: riscv-tdep.c:1574
int length() const
Definition: riscv-tdep.c:1570
void decode_r_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1614
void decode_cb_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1721
void decode_cs_type_insn(enum opcode opcode, ULONGEST ival, int imm)
Definition: riscv-tdep.c:1669
int rd() const
Definition: riscv-tdep.c:1580
static ULONGEST fetch_instruction(struct gdbarch *gdbarch, CORE_ADDR addr, int *len)
Definition: riscv-tdep.c:1769
void decode_css_type_insn(enum opcode opcode, ULONGEST ival, int imm)
Definition: riscv-tdep.c:1681
void decode(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: riscv-tdep.c:1801
void decode_cl_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1648
int rs2() const
Definition: riscv-tdep.c:1590
int decode_register_index_short(unsigned long opcode, int offset)
Definition: riscv-tdep.c:1608
void decode_ci_type_insn(enum opcode opcode, ULONGEST ival)
Definition: riscv-tdep.c:1640
void create(struct gdbarch *gdbarch) const
Definition: riscv-tdep.c:159
riscv_pending_register_alias(const char *name, const void *baton)
Definition: riscv-tdep.c:152
void analyse_inner(struct type *type, int offset)
Definition: riscv-tdep.c:2661
void analyse(struct type *type)
Definition: riscv-tdep.c:2607
int number_of_fields() const
Definition: riscv-tdep.c:2617
int field_offset(int index) const
Definition: riscv-tdep.c:2634
struct type * field_type(int index) const
Definition: riscv-tdep.c:2624
struct cmd_list_element * showlist
Definition: cli-cmds.c:125
struct cmd_list_element * setlist
Definition: cli-cmds.c:117
struct cmd_list_element * showdebuglist
Definition: cli-cmds.c:165
struct cmd_list_element * setdebuglist
Definition: cli-cmds.c:163
set_show_commands add_setshow_prefix_cmd(const char *name, command_class theclass, const char *set_doc, const char *show_doc, cmd_list_element **set_subcommands_list, cmd_list_element **show_subcommands_list, cmd_list_element **set_list, cmd_list_element **show_list)
Definition: cli-decode.c:428
set_show_commands add_setshow_auto_boolean_cmd(const char *name, enum command_class theclass, enum auto_boolean *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:682
set_show_commands add_setshow_zuinteger_cmd(const char *name, enum command_class theclass, unsigned int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:1190
@ class_maintenance
Definition: command.h:65
@ no_class
Definition: command.h:53
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition: corefile.c:346
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: corefile.c:237
void memory_error(enum target_xfer_status err, CORE_ADDR memaddr)
Definition: corefile.c:185
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition: defs.h:561
auto_boolean
Definition: defs.h:248
@ AUTO_BOOLEAN_TRUE
Definition: defs.h:249
@ AUTO_BOOLEAN_AUTO
Definition: defs.h:251
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
Definition: defs.h:526
return_value_convention
Definition: defs.h:258
@ RETURN_VALUE_REGISTER_CONVENTION
Definition: defs.h:261
@ RETURN_VALUE_ABI_PRESERVES_ADDRESS
Definition: defs.h:280
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
Definition: frame.c:1361
struct value * value_of_register(int regnum, frame_info_ptr frame)
Definition: findvar.c:254
int default_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
Definition: frame-unwind.c:217
enum unwind_stop_reason default_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
Definition: frame-unwind.c:227
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
Definition: frame-unwind.c:107
ULONGEST get_frame_register_unsigned(frame_info_ptr frame, int regnum)
Definition: frame.c:1351
CORE_ADDR get_frame_pc(frame_info_ptr frame)
Definition: frame.c:2592
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:713
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
Definition: frame.c:2907
CORE_ADDR get_frame_func(frame_info_ptr this_frame)
Definition: frame.c:1050
frame_info_ptr get_current_frame(void)
Definition: frame.c:1615
@ NORMAL_FRAME
Definition: frame.h:179
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition: frame.h:608
void set_gdbarch_long_long_bit(struct gdbarch *gdbarch, int long_long_bit)
Definition: gdbarch.c:1467
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:2023
void set_gdbarch_char_signed(struct gdbarch *gdbarch, int char_signed)
Definition: gdbarch.c:1755
void set_gdbarch_disassembler_options(struct gdbarch *gdbarch, char **disassembler_options)
Definition: gdbarch.c:5244
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1370
void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype *breakpoint_kind_from_pc)
const char * gdbarch_register_name(struct gdbarch *gdbarch, int regnr)
Definition: gdbarch.c:2142
void set_gdbarch_valid_disassembler_options(struct gdbarch *gdbarch, const disasm_options_and_args_t *valid_disassembler_options)
Definition: gdbarch.c:5261
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype *frame_align)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype *skip_prologue)
int gdbarch_addr_bit(struct gdbarch *gdbarch)
Definition: gdbarch.c:1708
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *register_name)
void set_gdbarch_push_dummy_code(struct gdbarch *gdbarch, gdbarch_push_dummy_code_ftype *push_dummy_code)
void set_gdbarch_int_bit(struct gdbarch *gdbarch, int int_bit)
Definition: gdbarch.c:1433
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype *return_value)
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
Definition: gdbarch.c:3508
void set_gdbarch_gnu_triplet_regexp(struct gdbarch *gdbarch, gdbarch_gnu_triplet_regexp_ftype *gnu_triplet_regexp)
void set_gdbarch_print_registers_info(struct gdbarch *gdbarch, gdbarch_print_registers_info_ftype *print_registers_info)
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1899
void set_gdbarch_double_bit(struct gdbarch *gdbarch, int double_bit)
Definition: gdbarch.c:1583
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype *inner_than)
enum bfd_endian gdbarch_byte_order_for_code(struct gdbarch *gdbarch)
Definition: gdbarch.c:1379
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition: gdbarch.c:2016
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *register_reggroup_p)
int gdbarch_sp_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:2006
void set_gdbarch_long_double_format(struct gdbarch *gdbarch, const struct floatformat **long_double_format)
Definition: gdbarch.c:1632
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2033
void set_gdbarch_call_dummy_location(struct gdbarch *gdbarch, enum call_dummy_location_type call_dummy_location)
Definition: gdbarch.c:2248
int gdbarch_num_pseudo_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1917
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *register_type)
void set_gdbarch_gcc_target_options(struct gdbarch *gdbarch, gdbarch_gcc_target_options_ftype *gcc_target_options)
void set_gdbarch_float_bit(struct gdbarch *gdbarch, int float_bit)
Definition: gdbarch.c:1550
void set_gdbarch_short_bit(struct gdbarch *gdbarch, int short_bit)
Definition: gdbarch.c:1416
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype *pseudo_register_write)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition: gdbarch.c:1927
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype *dwarf2_reg_to_regnum)
void set_gdbarch_long_bit(struct gdbarch *gdbarch, int long_bit)
Definition: gdbarch.c:1450
void set_gdbarch_ptr_bit(struct gdbarch *gdbarch, int ptr_bit)
Definition: gdbarch.c:1701
int gdbarch_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *reggroup)
Definition: gdbarch.c:3604
void set_gdbarch_type_align(struct gdbarch *gdbarch, gdbarch_type_align_ftype *type_align)
void set_gdbarch_cannot_store_register(struct gdbarch *gdbarch, gdbarch_cannot_store_register_ftype *cannot_store_register)
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype *pseudo_register_read)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:1910
void set_gdbarch_long_double_bit(struct gdbarch *gdbarch, int long_double_bit)
Definition: gdbarch.c:1616
void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype *sw_breakpoint_from_kind)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype *push_dummy_call)
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep_base *tdep)
Definition: gdbarch.c:264
@ ON_STACK
Definition: gdbarch.h:155
static int gdbarch_num_cooked_regs(gdbarch *arch)
Definition: gdbarch.h:377
function_call_return_method
Definition: gdbarch.h:112
@ return_method_struct
Definition: gdbarch.h:124
enum bfd_endian type_byte_order(const struct type *type)
Definition: gdbtypes.c:4018
int is_integral_type(struct type *t)
Definition: gdbtypes.c:3772
struct type * arch_composite_type(struct gdbarch *gdbarch, const char *name, enum type_code code)
Definition: gdbtypes.c:5989
const struct floatformat * floatformats_ieee_quad[BFD_ENDIAN_UNKNOWN]
Definition: gdbtypes.c:91
unsigned type_align(struct type *type)
Definition: gdbtypes.c:3645
void append_composite_type_field(struct type *t, const char *name, struct type *field)
Definition: gdbtypes.c:6065
bool is_fixed_point_type(struct type *type)
Definition: gdbtypes.c:6116
struct type * check_typedef(struct type *type)
Definition: gdbtypes.c:3010
@ FIELD_LOC_KIND_BITPOS
Definition: gdbtypes.h:493
#define TYPE_SAFE_NAME(type)
Definition: gdbtypes.h:2228
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
Definition: gnu-nat.c:1791
size_t size
Definition: go32-nat.c:241
static CORE_ADDR fetch_instruction(CORE_ADDR addr, ia64_instruction_type *it, long long *instr)
Definition: ia64-tdep.c:513
const struct language_defn * current_language
Definition: language.c:83
const char * alias
Definition: nds32-tdep.c:114
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: osabi.c:382
pv_t pv_constant(CORE_ADDR k)
pv_t pv_register(int reg, CORE_ADDR k)
pv_t pv_add(pv_t a, pv_t b)
pv_t pv_add_constant(pv_t v, CORE_ADDR k)
int pv_is_register(pv_t a, int r)
CORE_ADDR regcache_read_pc(struct regcache *regcache)
Definition: regcache.c:1324
int register_size(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:170
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:790
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:819
const reggroup *const general_reggroup
Definition: reggroups.c:251
int default_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
Definition: reggroups.c:147
const reggroup * reggroup_new(const char *name, enum reggroup_type type)
Definition: reggroups.c:34
const reggroup *const system_reggroup
Definition: reggroups.c:253
const reggroup *const float_reggroup
Definition: reggroups.c:252
const reggroup *const save_reggroup
Definition: reggroups.c:256
const reggroup *const all_reggroup
Definition: reggroups.c:255
void reggroup_add(struct gdbarch *gdbarch, const reggroup *group)
Definition: reggroups.c:124
const reggroup *const restore_reggroup
Definition: reggroups.c:257
const reggroup *const vector_reggroup
Definition: reggroups.c:254
@ USER_REGGROUP
Definition: reggroups.h:32
void register_riscv_ravenscar_ops(struct gdbarch *gdbarch)
static int riscv_pseudo_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *reggroup)
Definition: riscv-tdep.c:1461
static struct cmd_list_element * setriscvcmdlist
Definition: riscv-tdep.c:711
static ULONGEST riscv_type_align(gdbarch *gdbarch, type *type)
Definition: riscv-tdep.c:2239
static void riscv_assign_stack_location(struct riscv_arg_info::location *loc, struct riscv_memory_offsets *memory, int length, int align)
Definition: riscv-tdep.c:2461
static void riscv_init_reggroups()
Definition: riscv-tdep.c:4171
bool riscv_abi_embedded(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:770
static const struct target_desc * riscv_find_default_target_description(const struct gdbarch_info info)
Definition: riscv-tdep.c:3596
static void riscv_call_arg_scalar_int(struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo)
Definition: riscv-tdep.c:2492
static unsigned int riscv_debug_breakpoints
Definition: riscv-tdep.c:80
static bool riscv_is_regnum_a_named_csr(int regnum)
Definition: riscv-tdep.c:1315
static enum auto_boolean use_compressed_breakpoints
Definition: riscv-tdep.c:695
static void riscv_regcache_cooked_write(int regnum, const gdb_byte *data, int len, struct regcache *regcache, int flen)
Definition: riscv-tdep.c:3008
int riscv_abi_flen(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:761
static const char * riscv_feature_name_virtual
Definition: riscv-tdep.c:101
static CORE_ADDR riscv_scan_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc, CORE_ADDR end_pc, struct riscv_unwind_cache *cache)
Definition: riscv-tdep.c:1953
static CORE_ADDR riscv_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: riscv-tdep.c:2164
static struct gdbarch * riscv_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
Definition: riscv-tdep.c:3783
static void riscv_print_arg_location(ui_file *stream, struct gdbarch *gdbarch, struct riscv_arg_info *info, CORE_ADDR sp_refs, CORE_ADDR sp_args)
Definition: riscv-tdep.c:2928
static void riscv_call_arg_complex_float(struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo)
Definition: riscv-tdep.c:2567
static struct cmd_list_element * showriscvcmdlist
Definition: riscv-tdep.c:712
static CORE_ADDR riscv_frame_align(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: riscv-tdep.c:3428
static bool riscv_is_unknown_csr(struct gdbarch *gdbarch, int regnum)
Definition: riscv-tdep.c:1336
static unsigned int riscv_debug_unwinder
Definition: riscv-tdep.c:90
static bool riscv_assign_reg_location(struct riscv_arg_info::location *loc, struct riscv_arg_reg *reg, int length, int offset)
Definition: riscv-tdep.c:2435
static bool riscv_is_fp_regno_p(int regno)
Definition: riscv-tdep.c:796
static int riscv_arg_regs_available(struct riscv_arg_reg *reg)
Definition: riscv-tdep.c:2417
void riscv_supply_regset(const struct regset *regset, struct regcache *regcache, int regnum, const void *regs, size_t len)
Definition: riscv-tdep.c:4179
static void riscv_print_one_register_info(struct gdbarch *gdbarch, struct ui_file *file, frame_info_ptr frame, int regnum)
Definition: riscv-tdep.c:1103
static const char * riscv_feature_name_fpu
Definition: riscv-tdep.c:100
static void riscv_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: riscv-tdep.c:977
static unsigned int riscv_debug_infcall
Definition: riscv-tdep.c:85
static int riscv_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *reggroup)
Definition: riscv-tdep.c:1348
int riscv_abi_xlen(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:743
static enum register_status riscv_pseudo_register_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buf)
Definition: riscv-tdep.c:941
static int riscv_breakpoint_kind_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr)
Definition: riscv-tdep.c:805
static struct cmd_list_element * setdebugriscvcmdlist
Definition: riscv-tdep.c:716
static const gdb_byte * riscv_sw_breakpoint_from_kind(struct gdbarch *gdbarch, int kind, int *size)
Definition: riscv-tdep.c:857
static void show_use_compressed_breakpoints(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
Definition: riscv-tdep.c:700
int riscv_isa_xlen(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:734
static bool riscv_has_fp_abi(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:787
static bool riscv_has_fp_regs(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:779
static void riscv_print_registers_info(struct gdbarch *gdbarch, struct ui_file *file, frame_info_ptr frame, int regnum, int print_all)
Definition: riscv-tdep.c:1472
#define BIGGEST_ALIGNMENT
Definition: riscv-tdep.c:65
static char * riscv_disassembler_options
Definition: riscv-tdep.c:105
static unsigned int riscv_debug_gdbarch
Definition: riscv-tdep.c:95
static const char * riscv_gnu_triplet_regexp(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:3770
static const char * riscv_feature_name_vector
Definition: riscv-tdep.c:102
const char * riscv_feature_name_csr
Definition: riscv-tdep.c:98
static struct type * riscv_pseudo_register_type(struct gdbarch *gdbarch, int regnum)
Definition: riscv-tdep.c:1447
static struct value * riscv_frame_prev_register(frame_info_ptr this_frame, void **prologue_cache, int regnum)
Definition: riscv-tdep.c:3519
int riscv_isa_flen(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:752
static const struct frame_unwind riscv_frame_unwind
Definition: riscv-tdep.c:3533
static void show_riscv_debug_variable(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
Definition: riscv-tdep.c:722
static void riscv_add_reggroups(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:3616
static int riscv_cannot_store_register(struct gdbarch *gdbarch, int regnum)
Definition: riscv-tdep.c:1005
static struct type * riscv_fpreg_d_type(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:1013
static const reggroup * csr_reggroup
Definition: riscv-tdep.c:132
static int riscv_dwarf_reg_to_regnum(struct gdbarch *gdbarch, int reg)
Definition: riscv-tdep.c:3624
static struct riscv_gdbarch_features riscv_features_from_bfd(const bfd *abfd)
Definition: riscv-tdep.c:3550
static void riscv_call_arg_struct(struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo)
Definition: riscv-tdep.c:2714
void _initialize_riscv_tdep()
Definition: riscv-tdep.c:4242
#define SP_ALIGNMENT
Definition: riscv-tdep.c:62
static CORE_ADDR riscv_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr)
Definition: riscv-tdep.c:3025
static void riscv_arg_location(struct gdbarch *gdbarch, struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo, struct type *type, bool is_unnamed)
Definition: riscv-tdep.c:2866
static const char * riscv_pseudo_register_name(struct gdbarch *gdbarch, int regnum)
Definition: riscv-tdep.c:1432
static std::string riscv_gcc_target_options(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:3647
static struct type * riscv_register_type(struct gdbarch *gdbarch, int regnum)
Definition: riscv-tdep.c:1051
std::vector< CORE_ADDR > riscv_software_single_step(struct regcache *regcache)
Definition: riscv-tdep.c:4154
static const char * riscv_register_name(struct gdbarch *gdbarch, int regnum)
Definition: riscv-tdep.c:879
static void riscv_call_arg_scalar_float(struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo)
Definition: riscv-tdep.c:2548
static enum return_value_convention riscv_return_value(struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition: riscv-tdep.c:3220
static int riscv_tdesc_unknown_reg(struct gdbarch *gdbarch, tdesc_feature *feature, const char *reg_name, int possible_regnum)
Definition: riscv-tdep.c:3690
static bool riscv_next_pc_atomic_sequence(struct regcache *regcache, CORE_ADDR pc, CORE_ADDR *next_pc)
Definition: riscv-tdep.c:4106
static void riscv_frame_this_id(frame_info_ptr this_frame, void **prologue_cache, struct frame_id *this_id)
Definition: riscv-tdep.c:3498
static struct riscv_unwind_cache * riscv_frame_cache(frame_info_ptr this_frame, void **this_cache)
Definition: riscv-tdep.c:3437
static CORE_ADDR riscv_push_dummy_code(struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache)
Definition: riscv-tdep.c:2189
static struct value * value_of_riscv_user_reg(frame_info_ptr frame, const void *baton)
Definition: riscv-tdep.c:137
static CORE_ADDR riscv_next_pc(struct regcache *regcache, CORE_ADDR pc)
Definition: riscv-tdep.c:4026
static struct cmd_list_element * showdebugriscvcmdlist
Definition: riscv-tdep.c:717
static const char * riscv_feature_name_cpu
Definition: riscv-tdep.c:99
@ RISCV_DWARF_REGNUM_V0
Definition: riscv-tdep.h:72
@ RISCV_DWARF_REGNUM_F0
Definition: riscv-tdep.h:70
@ RISCV_DWARF_REGNUM_X31
Definition: riscv-tdep.h:69
@ RISCV_DWARF_REGNUM_X0
Definition: riscv-tdep.h:68
@ RISCV_DWARF_REGNUM_F31
Definition: riscv-tdep.h:71
@ RISCV_DWARF_LAST_CSR
Definition: riscv-tdep.h:75
@ RISCV_DWARF_FIRST_CSR
Definition: riscv-tdep.h:74
@ RISCV_DWARF_REGNUM_V31
Definition: riscv-tdep.h:73
@ RISCV_PRIV_REGNUM
Definition: riscv-tdep.h:56
@ RISCV_FA0_REGNUM
Definition: riscv-tdep.h:44
@ RISCV_LAST_CSR_REGNUM
Definition: riscv-tdep.h:53
@ RISCV_LAST_REGNUM
Definition: riscv-tdep.h:62
@ RISCV_GP_REGNUM
Definition: riscv-tdep.h:33
@ RISCV_TP_REGNUM
Definition: riscv-tdep.h:34
@ RISCV_RA_REGNUM
Definition: riscv-tdep.h:31
@ RISCV_FIRST_FP_REGNUM
Definition: riscv-tdep.h:43
@ RISCV_V0_REGNUM
Definition: riscv-tdep.h:58
@ RISCV_ZERO_REGNUM
Definition: riscv-tdep.h:30
@ RISCV_NUM_INTEGER_REGS
Definition: riscv-tdep.h:41
@ RISCV_FP_REGNUM
Definition: riscv-tdep.h:35
@ RISCV_SP_REGNUM
Definition: riscv-tdep.h:32
@ RISCV_FIRST_CSR_REGNUM
Definition: riscv-tdep.h:48
@ RISCV_LAST_FP_REGNUM
Definition: riscv-tdep.h:46
@ RISCV_A0_REGNUM
Definition: riscv-tdep.h:36
@ RISCV_V31_REGNUM
Definition: riscv-tdep.h:60
@ RISCV_PC_REGNUM
Definition: riscv-tdep.h:39
const target_desc * riscv_lookup_target_description(const struct riscv_gdbarch_features features)
Definition: riscv.c:117
struct type * builtin_long_long
Definition: gdbtypes.h:2264
struct type * builtin_double
Definition: gdbtypes.h:2258
struct type * builtin_func_ptr
Definition: gdbtypes.h:2314
struct type * builtin_long
Definition: gdbtypes.h:2249
struct type * builtin_data_ptr
Definition: gdbtypes.h:2303
struct type * builtin_int32
Definition: gdbtypes.h:2287
struct type * builtin_float
Definition: gdbtypes.h:2257
const char * name
Definition: cli-decode.h:116
LONGEST loc_bitpos() const
Definition: gdbtypes.h:586
field_loc_kind loc_kind() const
Definition: gdbtypes.h:581
struct type * type() const
Definition: gdbtypes.h:559
void read(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order, bool unsigned_p)
Definition: gmp-utils.c:45
void write(gdb::array_view< gdb_byte > buf, enum bfd_endian byte_order, bool unsigned_p) const
Definition: gmp-utils.c:68
Definition: regset.h:35
enum riscv_arg_info::location::location_type loc_type
union riscv_arg_info::location::@161 loc_data
struct type * type
Definition: riscv-tdep.c:2266
struct riscv_arg_info::location argloc[2]
const gdb_byte * contents
Definition: riscv-tdep.c:2257
riscv_arg_reg(int first, int last)
Definition: riscv-tdep.c:2329
struct riscv_memory_offsets memory
Definition: riscv-tdep.c:2397
struct riscv_arg_reg float_regs
Definition: riscv-tdep.c:2405
struct riscv_arg_reg int_regs
Definition: riscv-tdep.c:2401
riscv_call_info(struct gdbarch *gdbarch)
Definition: riscv-tdep.c:2378
void riscv_create_csr_aliases()
Definition: riscv-tdep.c:567
bool check(const struct target_desc *tdesc, struct tdesc_arch_data *tdesc_data, std::vector< riscv_pending_register_alias > *aliases, struct riscv_gdbarch_features *features) const
Definition: riscv-tdep.c:542
const char * register_name(int regnum) const
Definition: riscv-tdep.c:411
bool check(const struct target_desc *tdesc, struct tdesc_arch_data *tdesc_data, std::vector< riscv_pending_register_alias > *aliases, struct riscv_gdbarch_features *features) const
Definition: riscv-tdep.c:422
struct type * riscv_fpreg_d_type
Definition: riscv-tdep.h:91
int unknown_csrs_first_regnum
Definition: riscv-tdep.h:103
CORE_ADDR(* syscall_next_pc)(frame_info_ptr frame)
Definition: riscv-tdep.h:115
struct riscv_gdbarch_features abi_features
Definition: riscv-tdep.h:88
struct riscv_gdbarch_features isa_features
Definition: riscv-tdep.h:84
std::vector< const char * > names
Definition: riscv-tdep.c:195
bool check(struct tdesc_arch_data *tdesc_data, const struct tdesc_feature *feature, bool prefer_first_name_p, std::vector< riscv_pending_register_alias > *aliases) const
Definition: riscv-tdep.c:236
std::vector< struct register_info > m_registers
Definition: riscv-tdep.c:223
const char * name() const
Definition: riscv-tdep.c:208
riscv_register_feature()=delete
riscv_register_feature(const char *feature_name)
Definition: riscv-tdep.c:179
const char * m_feature_name
Definition: riscv-tdep.c:229
const struct tdesc_feature * tdesc_feature(const struct target_desc *tdesc) const
Definition: riscv-tdep.c:216
DISABLE_COPY_AND_ASSIGN(riscv_register_feature)
trad_frame_saved_reg * regs
Definition: riscv-tdep.c:120
struct frame_id this_id
Definition: riscv-tdep.c:123
CORE_ADDR frame_base
Definition: riscv-tdep.c:127
bool check(const struct target_desc *tdesc, struct tdesc_arch_data *tdesc_data, std::vector< riscv_pending_register_alias > *aliases, struct riscv_gdbarch_features *features) const
Definition: riscv-tdep.c:638
const char * register_name(int regnum) const
Definition: riscv-tdep.c:628
bool check(const struct target_desc *tdesc, struct tdesc_arch_data *tdesc_data, std::vector< riscv_pending_register_alias > *aliases, struct riscv_gdbarch_features *features) const
Definition: riscv-tdep.c:502
bool check(const struct target_desc *tdesc, struct tdesc_arch_data *tdesc_data, std::vector< riscv_pending_register_alias > *aliases, struct riscv_gdbarch_features *features) const
Definition: riscv-tdep.c:320
const char * register_name(int regnum) const
Definition: riscv-tdep.c:312
bool is_addr() const
Definition: trad-frame.h:165
void set_addr(LONGEST addr)
Definition: trad-frame.h:102
void set_value(LONGEST val)
Definition: trad-frame.h:88
Definition: gdbtypes.h:922
struct type * target_type() const
Definition: gdbtypes.h:1000
type_code code() const
Definition: gdbtypes.h:927
ULONGEST length() const
Definition: gdbtypes.h:954
bool has_varargs() const
Definition: gdbtypes.h:1135
struct field & field(int idx) const
Definition: gdbtypes.h:983
bool is_unsigned() const
Definition: gdbtypes.h:1063
bool is_vector() const
Definition: gdbtypes.h:1149
int num_fields() const
Definition: gdbtypes.h:965
void set_name(const char *name)
Definition: gdbtypes.h:945
void set_is_vector(bool is_vector)
Definition: gdbtypes.h:1154
const char * name() const
Definition: gdbtypes.h:939
Definition: value.c:181
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
Definition: symtab.c:3956
tdesc_arch_data_up tdesc_data_alloc(void)
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
static const registry< gdbarch >::key< tdesc_arch_data > tdesc_data
void tdesc_use_registers(struct gdbarch *gdbarch, const struct target_desc *target_desc, tdesc_arch_data_up &&early_data, tdesc_unknown_register_ftype unk_reg_cb)
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
int tdesc_has_registers(const struct target_desc *target_desc)
const char * tdesc_feature_name(const struct tdesc_feature *feature)
void set_tdesc_pseudo_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *pseudo_type)
struct type * tdesc_register_type(struct gdbarch *gdbarch, int regno)
int tdesc_register_bitsize(const struct tdesc_feature *feature, const char *name)
const char * tdesc_register_name(struct gdbarch *gdbarch, int regno)
int tdesc_unnumbered_register(const struct tdesc_feature *feature, const char *name)
bool tdesc_found_register(struct tdesc_arch_data *data, int regno)
int tdesc_register_in_reggroup_p(struct gdbarch *gdbarch, int regno, const struct reggroup *reggroup)
void set_tdesc_pseudo_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *pseudo_reggroup_p)
std::unique_ptr< tdesc_arch_data, tdesc_arch_data_deleter > tdesc_arch_data_up
int target_read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1830
int target_write_memory(CORE_ADDR memaddr, const gdb_byte *myaddr, ssize_t len)
Definition: target.c:1847
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1771
@ TARGET_XFER_E_IO
Definition: target.h:227
trad_frame_saved_reg * trad_frame_alloc_saved_regs(struct gdbarch *gdbarch)
Definition: trad-frame.c:62
struct value * trad_frame_get_prev_register(frame_info_ptr this_frame, trad_frame_saved_reg this_saved_regs[], int regnum)
Definition: trad-frame.c:187
void user_reg_add(struct gdbarch *gdbarch, const char *name, user_reg_read_ftype *xread, const void *baton)
Definition: user-regs.c:122
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: utils.c:3114
void print_spaces(int n, struct ui_file *stream)
Definition: utils.c:1947
void gdb_printf(struct ui_file *stream, const char *format,...)
Definition: utils.c:1865
void gdb_puts(const char *linebuffer, struct ui_file *stream)
Definition: utils.c:1788
#define gdb_stdlog
Definition: utils.h:196
struct value * value_cast(struct type *type, struct value *arg2)
Definition: valops.c:408
void get_formatted_print_options(struct value_print_options *opts, char format)
Definition: valprint.c:145
void get_user_print_options(struct value_print_options *opts)
Definition: valprint.c:128
void print_hex_chars(struct ui_file *stream, const gdb_byte *valaddr, unsigned len, enum bfd_endian byte_order, bool zero_pad)
Definition: valprint.c:1822
void common_val_print(struct value *value, struct ui_file *stream, int recurse, const struct value_print_options *options, const struct language_defn *language)
Definition: valprint.c:1014
struct type * value_type(const struct value *value)
Definition: value.c:1109
int value_entirely_available(struct value *value)
Definition: value.c:408
struct value * allocate_value(struct type *type)
Definition: value.c:1053
gdb::array_view< gdb_byte > value_contents_raw(struct value *value)
Definition: value.c:1167
struct value * value_from_contents(struct type *type, const gdb_byte *contents)
Definition: value.c:3730
gdb::array_view< const gdb_byte > value_contents(struct value *value)
Definition: value.c:1464
LONGEST value_as_long(struct value *val)
Definition: value.c:2791
int value_optimized_out(struct value *value)
Definition: value.c:1481
gdb::array_view< const gdb_byte > value_contents_for_printing(struct value *value)
Definition: value.c:1265