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Icarus Verilog is a Verilog simulation and synthesis tool.  It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some 
target format.  For batch simulation, the compiler can generate an intermediate
form called vvp assembly.  This intermediate form is executed by the 'vvp' 
command.  For synthesis, the compiler generates netlists in the desired format.

 Name                                     Last modified      Size  
 Parent Directory                                              -   
 README                                   26-Nov-2013 10:57  387   
 slack-desc                               26-Nov-2013 10:57  811   
 verilog.SlackBuild                       26-Nov-2013 10:57  2.0K  
 verilog.info                             26-Nov-2013 10:57  301   

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