/* @(#) $Revision: 1.20.106.1 $ */      
/* $Source: /usr/local/kcs/sys.ROSE_800/machine/RCS/psl.h,v $
 * $Revision: 1.20.106.1 $	$Author: root $
 * $State: Exp $   	$Locker: CRT $
 * $Date: 97/07/07 17:53:55 $
 */
#ifndef _MACHINE_PSL_INCLUDED /* allow multiple inclusions */
#define _MACHINE_PSL_INCLUDED

/*
 * Processor Status Word (PSW) Masks
 * Berkeley UNIX calls this the processor status longword
 */

#define	PSW_T	0x01000000	/* Taken Branch Trap Enable */
#define	PSW_H	0x00800000	/* Higher-Privilege Transfer Trap Enable */
#define	PSW_L	0x00400000	/* Lower-Privilege Transfer Trap Enable */
#define	PSW_N	0x00200000	/* PC Queue Front Instruction Nullified */
#define	PSW_X	0x00100000	/* Data Memory Break Disable */
#define	PSW_B	0x00080000	/* Taken Branch in Previous Cycle */
#define	PSW_C	0x00040000	/* Code Address Translation Enable */
#define	PSW_V	0x00020000	/* Divide Step Correction */
#define	PSW_M	0x00010000	/* High-Priority Machine Check Disable */
#define	PSW_CB	0x0000ff00	/* Carry/Borrow Bits */
#define	PSW_R	0x00000010	/* Recovery Counter Enable */
#define	PSW_Q	0x00000008	/* Interruption State Collection Enable */
#define	PSW_P	0x00000004	/* Protection ID Validation Enable */
#define	PSW_D	0x00000002	/* Data Address Translation Enable */
#define	PSW_I	0x00000001	/* External, Power Failure, Low-Priority */
				/*  Machine Check Interruption Enable */

/*
 * The following defines are only applicable to the PA2.0 PSW,
 * which is now a 64-bit register.  It is not meaningful to
 * use these bits for older, PA1.x machines.
 */
#define PSW_CB_HI 0x000000ff	/* Upper Carry/Borrow Bits   */
				/*  (in upper 32 bits of 64 bit doubleword) */
#define	PSW_Y	0x80000000	/* Data Debug Trap Disable */
#define	PSW_Z	0x40000000	/* Instruction Debug Trap Disable */
#define	PSW_W	0x08000000	/*Wide 64bit Addr Enable(not for SSM/RSM inst)*/
#define	PSW_E	0x04000000	/* Little Endian Memory Access Enable */
#define	PSW_S	0x02000000	/* Secure Interval Timer */
#define	PSW_O	0x00000080	/* Ordered References */
#define	PSW_G	0x00000040	/* Debug Trap Enable */
#define	PSW_F	0x00000020	/* Performance Monitor Interrupt Mask */

/*
 * The SSM and RSM instructions need to use a different mask for the
 * PSW W and E bits when the W-bit is set.  The following definitions
 * should be used to represent these two bits for all SSM/RSM instructions.
 */
#define PSW_W_SM	0x200	/* W-bit for RSM/SSM instructions */
#define PSW_E_SM	0x100	/* E-bit for RSM/SSM instructions */


/*
 * PSW Bit Positions
 */

#define	PSW_T_P	7
#define	PSW_H_P	8
#define	PSW_L_P	9
#define	PSW_N_P	10
#define	PSW_X_P	11
#define	PSW_B_P	12
#define	PSW_C_P	13
#define	PSW_V_P	14
#define	PSW_M_P	15
#define	PSW_CB_P	23
#define	PSW_R_P	27
#define	PSW_Q_P	28
#define	PSW_P_P	29
#define	PSW_D_P	30
#define	PSW_I_P	31

/*
 * The following defines are only applicable to the PA2.0 PSW,
 * which is now a 64-bit register.  It is not meaningful to
 * use these bits for older, PA1.x machines.
 */
#define	PSW_Y_P	0
#define	PSW_Z_P	1
#define	PSW_W_P	4	/* not valid for RSM/SSM instructions */
#define	PSW_E_P	5
#define	PSW_S_P	6
#define PSW_W_SM_P 22	/* use with RSM/SSM instructions */
#define	PSW_O_P	24
#define	PSW_G_P	25
#define	PSW_F_P	26

/*
 * PSW Bit Positions (in 64-bit doubleword)
 */

#define PSW_CB_HI_P64	31
#define	PSW_Y_P64	32
#define	PSW_Z_P64	33
#define	PSW_W_P64	36
#define	PSW_E_P64	37
#define	PSW_S_P64	38
#define	PSW_T_P64	39
#define	PSW_H_P64	40
#define	PSW_L_P64	41
#define	PSW_N_P64	42
#define	PSW_X_P64	43
#define	PSW_B_P64	44
#define	PSW_C_P64	45
#define	PSW_V_P64	46
#define	PSW_M_P64	47
#define	PSW_CB_P64	55
#define	PSW_O_P64	56
#define	PSW_G_P64	57
#define	PSW_F_P64	58
#define	PSW_R_P64	59
#define	PSW_Q_P64	60
#define	PSW_P_P64	61
#define	PSW_D_P64	62
#define	PSW_I_P64	63

/*
 * Kernel PSW Masks
 */
#define	SYSTEM_MASK	(PSW_W+PSW_R+PSW_Q+PSW_P+PSW_D+PSW_I)

#ifndef __BTT
#define	GLOBAL_VAR_MASK	(PSW_H+PSW_L+PSW_C+PSW_M)
#else /* not __BTT */
#define	GLOBAL_VAR_MASK	(PSW_H+PSW_L+PSW_C+PSW_M+PSW_T)
#endif /* not __BTT */

/* Use these defines for both 32-bit & 64-bit (low part) PSW */
#ifdef	__LP64__
#define	SAVE_STATE_MASK	(PSW_W+PSW_X+PSW_T+PSW_N+PSW_B+PSW_V+PSW_CB)
#else
#define	SAVE_STATE_MASK	(PSW_X+PSW_T+PSW_N+PSW_B+PSW_V+PSW_CB)
#endif	/* __LP64__ */

#define	PTRACE_MASK	(PSW_N+PSW_V+PSW_CB)

/* Use these defines for 64-bit (high part) PSW */
#define	SAVE_STATE_MASK_HI	(PSW_CB_HI)
#define	PTRACE_MASK_HI	(PSW_CB_HI)

#endif /* _MACHINE_PSL_INCLUDED */
