/* $Source: /usr/local/kcs/sys.DAVIS_800/machine/RCS/cpu.h,v $
 * $Revision: 1.63.98.5 $        $Author: sbinesh $
 * $State: Exp $         $Locker:  $
 * $Date: 97/05/08 19:11:58 $
 */

/*
 * @(#) cpu.h $Date: 97/05/08 19:11:58 $ $Revision: 1.63.98.5 $ PATCH_10.20 (PHKL_11003)
*/

#ifndef _MACHINE_CPU_INCLUDED /* allow multiple inclusions */
#define _MACHINE_CPU_INCLUDED

#ifndef _SYS_STDSYMS_INCLUDED
#ifdef _KERNEL_BUILD
#    include "../h/stdsyms.h"
#else  /* ! _KERNEL_BUILD */
#    include <sys/stdsyms.h>
#endif /* _KERNEL_BUILD */
#endif  /*  _SYS_STDSYMS_INCLUDED  */

/*
 * IO buffer alignment.  This function takes a pointer to a buffer
 * and returns a pointer which is CPU_IOLINE aligned.
 */
#define CPU_IOLINE      64
#define ALIGN_IOBUF(P) ((char *)(((int)(P) + CPU_IOLINE-1) & ~(CPU_IOLINE-1)))

/*
 * Cache alignment---this is used for functions that want to align themselves
 * on cache line boundaries to improve performance by minimizing cache misses.
 */
#define CPU_CACHE_LINE  32

#define IOSPACE         (unsigned)0xF0000000
#define IO_BROADCAST    0xFFFC0000
#define LBROAD_eir      ((struct processorhpa *)IO_BROADCAST)->io_eir
#define LBROAD_flex     ((struct io_module *)IO_BROADCAST)->io_flex
#define LBROAD_command  ((struct io_module *)IO_BROADCAST)->io_command
#define PDC_LOW         0xEF000000
#define PDC_HIGH        0xF1000000
#define FPA             0xFFF80000
#define FLEX_DATA       0xFFF80001
#define DMA_ENABLE      0x00000001

#define FLEX_MASK       0xFFFC0000
#define SPA_ENABLE      0x20
#define NUM_MODS_PER_BUS        64

/*
 *  HP Precision Architecture memory addresses of variables for communications
 *  between HP Precision Architecture and the 9920. The communications area is
 *  one page long just after the area used by PDC.
 */
#define FIRST_PAGE      0x8000  /* First page of memory past the
                                   area reserved by PDC. */

/*
 * for I/O modules, (opt & IODC_INTERRUPTS) is true if module interrupts
 */
#  define IODC_INTERRUPTS         0x80
#  define EXTENDED_ERR_LOGGING    0x08

#  define MOD_TABLE_SIZE  200

/* Module type numbers */

#  define MOD_TYPE_NPROC	0
#  define MOD_TYPE_MEMORY	1
#  define MOD_TYPE_B_DMA_IO	2
#  define MOD_TYPE_B_DIRECT_IO	3
#  define MOD_TYPE_A_DMA_IO	4
#  define MOD_TYPE_A_DIRECT_IO	5
#  define MOD_TYPE_OTHER	6
#  define MOD_TYPE_BUSCONV	7
#  define MOD_TYPE_CIO_CHANNEL	8
#  define MOD_TYPE_CONSOLE	9
#  define MOD_TYPE_FOREIGN_IO  10
#  define MOD_TYPE_BUS_ADAPTER 11
#  define MOD_TYPE_IOA         12
#  define MOD_TYPE_BUS_BRIDGE  13

#  define IS_BUSCONV(x) (x == MOD_TYPE_IOA || x == MOD_TYPE_BUSCONV)

/* Processor HVERSION Model Numbers */
/* NOTE: To avoid name copyright issues, don't use machine nicknames */

#  define CPU_M720	0x200
#  define CPU_M7LC	0x604	/*  */
#  define CPU_M715_D	0x60A
#  define CPU_M715_E	0x60B
#  define CPU_M715_F	0x60C
#  define CPU_M715_G	0x619
#  define CPU_M725_C	0x60D
#  define CPU_M725_D	0x60E
#  define CPU_M743i_A	0x603
#  define CPU_M743i_B	0x604
#  define CPU_M743v_A	0x617
#  define CPU_M743v_B	0x618

#  define CPU_M808	0x103   /* Restricted 815. Use SW_CAP */
#  define CPU_M810	0x100
#  define CPU_M815	0x103
#  define CPU_M822	0x101
#  define CPU_M825	0x008
#  define CPU_M832	0x102
#  define CPU_M834	0x00A	/* 835 2 user WS */
#  define CPU_M835	0x00A
#  define CPU_M836	0x00A	/* 835 2 user Server */
#  define CPU_M840	0x004
#  define CPU_M842	0x104
#  define CPU_M843	0x104	/* 842 Server */
#  define CPU_M844	0x00B	/* 845 2 user WS */
#  define CPU_M845	0x00B
#  define CPU_M846	0x00B	/* 845 2 user Server */
#  define CPU_M850	0x080
#  define CPU_M850_OPDC	0x00C	/* Old number for 850 */
#  define CPU_M852	0x105
#  define CPU_M853	0x105	/* 852 Server */
#  define CPU_M855	0x081
#  define CPU_M860	0x082	/* PN10C */
#  define CPU_M870	0x083

/* SW_CAP fields */

#  define UNRESTRICTED 0      /* unrestricted */
#  define SERVER       1      /* 2 user server */     
#  define WS           2      /* 2 user workstation */
#  define RESTRICTED   1      /* general limited I/O slots */

/* Processor SVERSION Fields */

#  define GET_PROCESSOR_LEVEL(sversion) (((unsigned int)sversion) & 0x3)
#  define LEVEL_0_0	0
#  define LEVEL_1_0	1
#  define LEVEL_1_5	2
#  define LEVEL_2_0	3

/* Memory SVERSION Model Numbers */

#  define MEM_ARCH                0x00008
#  define MEM_IMPL_DEP            0x00009

#  define MEM_CONTROL_INIT        0x0000
#  define MEM_CONTROL_NORMAL      0x0100
#  define MEM_HERR_SPA            0x0400
#  define MEM_AERR_CORR           0x6000
#  define MEM_HERR_UNCORR         0x6400
#  define MEM_AERR_MAP            0x6800   /* treat the same as MEM_AERR_CORR */

/* Memory HVERSION Model Numbers */
#define MEM_850                 0x004    /* 850-model memory controller */
#define MEM_COBRA		0x013
#define MEM_CORAL		0x015
#define MEM_OUTFIELD		0x019
#define MEM_CORAL2    		0x01A
#define MEM_MIOC		0x026
#define MEM_CHEETAH		0x037

/* XXX: delete these after the graphics folks have fixed the drivers */

/* Type-A DMA SVERSION Model Numbers */

#  define NIMBUS_LGB_FB           0x0004A
#  define NIMBUS_LGB_CONTROL      0x0004B

/* Type-B DMA SVERSION Model Numbers */
#  define SVER_MODEL_MAP8024      0x00058    /* MAP 802.4 networking card */

/* Type Other SVERSION Model Numbers */

#  define SPECTRO_LGB_FB          0x00048
#  define SPECTRO_LGB_CONTROL     0x00049

/* XXX: what are these for? */

/* Type-A Direct SVERSION Model Numbers */

#  define SVER_MODEL_RS232        0x0000E    /* RS232 */
#  define SVER_MODEL_PEACOCK      0x0000F    /* Graphics console */
#  define SVER_MODEL_PEACOCK_HIL  0x00014    /* Keyboard */

/* Bus Converter HVERSION Model Numbers */

#  define CHEETAH_BC              0x004
#  define BC1_SMODEL		  0x0000c

#  define BC_RANGE_ALIGN          0xFFFF0000
#  define BC_MODE_MASK            0x180
#  define BC_OFF                  0x000
#  define BC_INCLUDE              0x080
#  define BC_EXCLUDE              0x100
#  define BC_PEEK                 0x180
#  define BC_POWER_LOST_MASK      0x2
#  define BC_POWER_FAIL_MASK      0x5
#  define BC_SEVERE_ERROR_MASK    0x180
#  define BC_PORT_MASK            0x8
#  define BC_UPPER_PORT           0x0
#  define BC_LOWER_PORT           0x8

/* Bus Adapter HVERSION Model Numbers */
#define CORE_LASI_BA 0x016

/* Fields within IO_STATUS register */

#  define SE           0x0200
#  define HE           0x0100
#  define FE           0x0080
#  define RY           0x0040
#  define DG           0x0010
#  define ESTAT_MASK   0xFC00

/* I/O Module States */

#  define ST_ACTIVE(s) (!(s & (RY|DG)))
#  define ST_READY(s)  (s & RY		    && !(s & (DG|FE|HE|SE|ESTAT_MASK)))
#  define ST_AERR(s)   (s & (RY|ESTAT_MASK) && !(s & (DG|FE|HE|SE)))
#  define ST_SERR(s)   (s & (RY|SE)	    && !(s & (DG|FE|HE)))
#  define ST_HERR(s)   (s & (RY|HE)	    && !(s & (DG|FE)))
#  define ST_FERR(s)   (s & (RY|FE)	    && !(s & DG))
#  define ST_DIAG(s)   (s & DG)

/* Commands that are written to IO_COMMAND register */
#  define CMD_CLEAR       3
#  define CMD_RESET       5
#  define CMD_PORT        0x020
#  define CMD_RESET_ST    0x105

/* And just where IS the IO_COMMAND register? */
#define COMMAND 48

#  define MEMRESERVED     NBPG    /* Reserved first page for RDB */

#define GW_PAGE_VADDR   0xC0000000      /* Virtual address of kernel gateways,
                                         * used by libc for system calls. */

/* 
 * Determine ratio of hash entries to pdir entries. The default is 
 * to use the small table. Its possible that some Multi-user machines
 * or specific PA implementations may want to use the large table.
 */
#ifdef _KERNEL
#ifdef	LARGE_HTBL
#define HASH_PDIR_RATIO 2
#else	/* !LARGE_HTBL */
#define HASH_PDIR_RATIO 1       
#endif	/* LARGE_HTBL */
#endif /* _KERNEL */

#define DRV_PSW 0x0004000f      /* Psw for device drivers */

/*
 * Word size for all HP Precision Architecture processors is 4 bytes (32 bits)
 */
#define WORD_SIZE       4
#define WORD_SIZE_BITS  32

#ifdef MP_SDTA
#  define SDTA_PROTID	61002	/* the WD bit is not turned on */
#endif /* MP_SDTA */

#  define MP_RENDEZ_FAILED  -2
#  define MP_NOT_VALID      -1
#  define MPBLOCK 0	/* MUST BE 0, to save instructions in asm_utl.s */
#  define MPIDLE  1
#  define MPUSER  2
#  define MPSYS   3
#  define MPSWAIT 4
/*
 *  Definitions for sdta_flags word
 */
#  define SDTA_F_IGNORE	0x1	/* ignore faults when this bit set */


/*
 * This section has structures used by C.
 */
#ifndef LOCORE
#ifdef _KERNEL_BUILD
#include "../h/types.h"
#else  /* ! _KERNEL_BUILD */
#include <sys/types.h>
#endif /* _KERNEL_BUILD */


/* the following structure holds information about the cpu and key bits */

#define KEY_CNT 1       /* words of keybit info returned by PDC MODEL call */
struct keybit_info {
        int     cpu_version;		/* holds copy of cpu_version       */
        int     fpu_info;		/* holds result of copr,0,0 	   */
        int     keycnt;			/* number of words of key bit info */
        unsigned int key_bits[KEY_CNT]; /* key bits returned from PDC	   */
        int     end;			/* set to -1 to mark end of struct */
}; 

/* map of processor's SRS in hard physical address space */
struct processorhpa {
        volatile u_int   io_eir;
        volatile int     nothing[11];
        volatile u_int   io_command;
};

/* Should point to the primary lasi. Used for soft power switch */
extern struct lasicorehpa *primary_lasi_regs;	

struct corehpa {			/* s700 */
	volatile char	core_ioss_reset;	/* wo	IOSS Reset	      */
	volatile char	reserved1[31];
	volatile char 	core_asp_version;	/* ro	ASP version ctl byte  */
	volatile char	reserved2[31];
	volatile char	error_log;	        /* rw	Asp error log byte    */
};

/* Core commands 			  s700 */
#define CORE_RESET	0x1

struct corehpa2 {
        volatile int           irr; 		/* +0x00 - Interrupt Request  */
        volatile int           imr; 		/* +0x04 - Interrupt Mask     */
        volatile int           ipr; 		/* +0x08 - Interrupt Pending  */
	volatile int	       icr;		/* +0x0C - LASI int control   */
	volatile int	       iar;		/* +0x10 - INT Adress         */
        volatile int           reserved1[3]; 	/* +0x14		      */
        volatile unsigned char led_control;	/* +0x20 - LED Control	      */
        volatile char          reserved2[3]; 	/* +0x21		      */
        volatile int           status; 		/* +0x24 - I/O Subsys Status  */
};

/* Structures and defines for Asp interrupt handling. */

struct asp_isr_link {
    int          (*isr)();
    int          arg1;
    int          arg2;
};

/* GECKO REVISIT */
#define LASI_RTC 			0x9000	/* offset to real time clock */
#define LASI_MISC_REGS                  0xC000	/* offset to misc registers */
#define LASI_LLA_OFFSET 		0x67c4c	/* where to find LAN address */
#define ASP_INT_CONTROLLER_OFFSET       0x2F000

#define ASP_INT_LINES           32

#define EISA_NMI_INT_LINE       31
#define EISA_NMI_INT_MASK       0x00000001
#define HIL_GENERAL_INT_LINE    30
#define HIL_GENERAL_INT_MASK    0x00000002
#define HIL_HIGH_INT_LINE       29
#define HIL_HIGH_INT_MASK       0x00000004
#define SERIAL_1_INT_LINE       26
#define SERIAL_1_INT_MASK       0x00000020
#define SERIAL_2_INT_LINE       25
#define SERIAL_2_INT_MASK       0x00000040
#define PARALLEL_INT_LINE       24
#define PARALLEL_INT_MASK       0x00000080
#define LAN_INT_LINE            23
#define LAN_INT_MASK            0x00000100
#define SCSI_INT_LINE           22
#define SCSI_INT_MASK           0x00000200
#define EISA_INT_LINE           21
#define EISA_INT_MASK           0x00000400
#define GRAPHIC_1_INT_LINE      20
#define GRAPHIC_1_INT_MASK      0x00000800
#define GRAPHIC_2_INT_LINE      19
#define GRAPHIC_2_INT_MASK      0x00001000
#define BUS_ERROR_INT_LINE      17
#define BUS_ERROR_INT_MASK      0x00004000
#define EXTERNAL_INT_LINE       10
#define EXTERNAL_INT_MASK       0x00200000

#define ASP_LEVEL_6_INTS			  \
    (EXTERNAL_INT_MASK	| BUS_ERROR_INT_MASK	| \
     EISA_INT_MASK	| EISA_NMI_INT_MASK)

/* map of s700 memory controller (Viper) registers */
struct viper {
        volatile int     reserved1[9]; 		/* +0x00		      */
        volatile int     io_spa;		/* +0x24 - IO_SPA	      */
        volatile int     reserved2[22];		/* +0x28		      */
        volatile int     control;		/* +0x80 - VIPER_CONTROL      */
        volatile int     status;		/* +0x84 - VIPER_STATUS       */
        volatile int     intr_word;		/* +0x88 - INTERRUPT_WORD     */
        volatile int     reserved3[13];		/* +0x8C		      */
        volatile int     mem_control;		/* +0xC0 - MEM_CONTROL	      */
        volatile int     mem_write_chk_data;    /* +0xC4 - MEM_WRITE_CHK_DATA */
        volatile int     mem_limit;             /* +0xC8 - MEMORY_LIMIT       */
        volatile int     reserved4;             /* +0xCC                      */
        volatile int     mem_err_word_0;        /* +0xD0 - MEM_ERROR_WORD_0   */
        volatile int     mem_err_word_1;        /* +0xD4 - MEM_ERROR_WORD_1   */
        volatile int     mem_err_check_byte;    /* +0xD8 - MEM_ERROR_CK_BYTE  */
	volatile int     mem_read_chk_data;     /* +0xDC - MEM_READ_CHK_DATA  */
	volatile int     error_address;         /* +0xE0 - ERROR_ADDRESS      */
        volatile int     reserved5[967];        /* +0xE4		      */
};


/*
 * In Cobra, this structure is based at 0xfffbc000, but in the general
 * case, it will be pointed to by the variable "venom".
 */
struct venom {
	/* Venom User HPA */
	volatile int	reserved0[0x20];	/* 0x0000 */
	volatile int	user_control;		/* 0x0080 */
	volatile int	span_count;		/* 0x0084 */
	volatile int	graphics_address;	/* 0x0088 */
	volatile int	reserved1;
	volatile int	zslope_fraction;	/* 0x0090 */
	volatile int	zslope_integer;		/* 0x0094 */
	volatile int	z_fraction;		/* 0x0098 */
	volatile int	z_integer;		/* 0x009C */
	volatile int	reserved2[8];
	volatile int	blue_slope;		/* 0x00C0 */
	volatile int	blue_color;		/* 0x00C4 */
	volatile int	reserved3[2];
	volatile int	red_slope;		/* 0x00D0 */
	volatile int	red_color;		/* 0x00D4 */
	volatile int	reserved4[2];
	volatile int	green_slope;		/* 0x00E0 */
	volatile int	green_color;		/* 0x00E4 */
	volatile int	reserved5[0x3C6];
	/* Venom Supervisor HPA */
	volatile int	reserved6[0x20];	/* 0x1000 */
	volatile int	sup_control;		/* 0x1080 */
	volatile int	z_address;		/* 0x1084 */
};

/* For Asp arbitration macros */
#define VIPER_CONTROL_COPY      0xdc

/*
 * These two definitions are used by the lan2 driver. They used to be
 * under ifdef __hp9000s700. As the driver now (release 9.04) is also used on
 * the S800 side, the definitions had to be moved out of the ifdef.
 */
#define CORE_ARBITRATION	0x04
#define EISA_ARBITRATION	0x01

/*
 * The following structures have been defined for Wright Brothers. The
 * first H/W box to combine NIO and CoreIO...  
 */

/* These defines are for Lasi's interrupt handler */
#define LASI_INT_LINES  	32
#define LASI_LAN_INT_LINE	23
#define LASI_LAN_INT_MASK	0x00000100
#define LASI_ERROR_INT_LINE	17
#define LASI_ERROR_INT_MASK	0x00004000
#define LASI_EXT_INT_LINE	10
#define LASI_EXT_INT_MASK	0x00200000

#define LASI_SVERSION_MODEL	0x81

struct lasi_int_regs {

	volatile int	irr;  	/* Interrupt Request Register */

	volatile int	imr;    /* Interrupt Mask Register */

	volatile int	ipr;	/* Interrupt Pending Register */

	volatile int	icr;	/* Interrupt Control Register */

	volatile int	iar;	/* Interrupt Access Register */

	int	undefined[1019];
};

/*
 * Notice that although all of Lasi's miscellaneous registers are one byte 
 * in length, we are defining this structure as if they were one word long.
 * Lasi will respond to a read4 operation to one of these registers by placing
 * the contents of the register in the least significant byte of the word.
 */
struct lasi_misc_regs {

	volatile unsigned int	pcr;	/* Power Control Register */

	volatile unsigned int	elr;	/* Error Logging Register */

	volatile unsigned int 	vcr;	/* Version Contol Register */

	/*
	 * WARNING: The way Lasi has been wired, reseting the LAN transceiver
	 *          (by setting the LAN bit in the I/O Reset register) will 
	 *          also reset the PC floppy and disable memory (while the
	 *          FDC_RESET signal is asserted).
	 *
	 * DO NOT RESET THE LAN (the LAN-transceiver) by using this bit! 
	 */
	volatile unsigned int	iorr;	/* I/O Reset Register */

	volatile unsigned int   amr;	/* Arbitration Mask Register */

	int undefined[1019];
};

/* map of a module's registers in hard physical address space.
 Some are undefined for any particular module. */
struct io_module {
        volatile int     nothing;		/* reg 0 */
        volatile u_int   io_eim;
        volatile u_int   io_dc_adata;
        volatile int     io_ii_cdata;
        volatile caddr_t io_dma_link;		/* reg 4 */
        volatile u_int   io_dma_command;
        volatile caddr_t io_dma_address;
        volatile int     io_dma_count;
        volatile caddr_t io_flex;		/* reg 8 */
        volatile caddr_t io_spa_address;
        volatile int     reserved1[2];
        volatile u_int   io_command;		/* reg 12 */
        volatile u_int   io_status;
        volatile u_int   io_control;
        volatile u_int   io_data;
        volatile int     reserved2;		/* reg 16 */
        volatile caddr_t chain_addr;
        volatile u_int   sub_mask_clr;
        volatile int     reserved3[13];
        volatile int     undefined[480];
        volatile int     unpriv[512];
};

struct io_module_adma {
        volatile u_int   reserved0;		/* reg 0     (0x00) SRS */
        volatile u_int   io_eim;
        volatile u_int   io_dc_adata;
        volatile u_int   io_ii_cdata;
        volatile u_int   reserved1[4];		/* reg 4-7   (0x10) */
        volatile u_int   reserved2;		/* reg 8     (0x20) */
        volatile caddr_t io_spa_address;
        volatile u_int   reserved3[2];
        volatile u_int   io_command;		/* reg 12    (0x30) */
        volatile u_int   io_status;
        volatile u_int   io_control;
        volatile u_int   io_data_inout;

        volatile caddr_t io_err_sadd;		/* reg  0    (0x40) ARS */
        volatile u_int   io_err_info;
        volatile caddr_t io_err_madd;
        volatile u_int   reserved4;
        volatile caddr_t io_ars_dma_link;	/* reg  4    (0x50) */
        volatile u_int   io_ars_dma_command;
        volatile caddr_t io_ars_dma_address;
        volatile u_int   io_ars_dma_count;
        volatile int     io_ars_reserved[8];	/* reg 8-15  (0x60) */

        volatile int     io_admars_reserved0;	/* reg 0     (0x80) ADMARS */
        volatile u_int   io_admars_eim;
        volatile int     io_admars_reserved1;            
        volatile int     io_admars_cdata;
        volatile caddr_t io_admars_dma_link;	/* reg 4     (0x90)*/
        volatile u_int   io_admars_dma_command;
        volatile caddr_t io_admars_dma_address;
        volatile u_int   io_admars_dma_count;
        volatile int     io_admars_reserved2[4];/* reg 8-11  (0xA0) */
        volatile u_int   io_admars_io_command;  /* reg 12    (0xB0) */
        volatile u_int   io_admars_io_status;
        volatile u_int   io_admars_io_reserved3;
        volatile u_int   io_admars_data_inout;

        volatile int     lower_trs1[16];	/* (0x0C0) lower page TRSes */
        volatile int     lower_trs2[16];	/* (0x100) */
        volatile int     lower_trs3[16];	/* (0x140) */
        volatile int     lower_trs4[16];	/* (0x180) */
        volatile int     lower_trs5[16];	/* (0x1C0) */
        volatile int     lower_trs6[16];	/* (0x200) */
        volatile int     lower_trs7[16];	/* (0x240) */
        volatile int     lower_trs8[16];	/* (0x280) */
        volatile int     lower_trs9[16];	/* (0x2C0) */
        volatile int     hvrs[320];		/* (0x300) HVRSes */
        volatile int     upper_trs[512];	/* upper page TRSes */
};

struct bc_module {
        volatile int     unused1[12];
        volatile u_int   io_command;
        volatile u_int   io_status;
        volatile u_int   io_control;
        volatile int     unused2[1];
        volatile u_int   io_err_resp;
        volatile u_int   io_err_info;
        volatile u_int   io_err_req;
        volatile int     unused3[11];
        volatile u_int   io_io_low;
        volatile u_int   io_io_high;
};

/* XXX: delete this when all code (pll_utl.c & pdc_rqsts.h) have changed
 * to use iodc_hversion, iodc_spa, and iodc_type.
 */

struct mod_type {
        u_int   hw_rev:16,      /* HVERSION model and rev */
                io_spa:1,       /* 1 = io_spa, 0 = memory spa */
                :1,             /* zero bit */
                :1,             /* SV bit */
                shift:5,        /* max spa_size = 2 ** shift */
                :1,             /* mr bit (unused) */
                :1,             /* wd bit (unused) */
                :1,             /* reserved bit */
                mtype:5;        /* module type */
};

/* definitions for mod_type.io_spa */
#  define MEM_MOD 0
#  define IO_MOD  1

/* XXX: delete this superfluous definition when all code (cent0.c, scsi1.c,
 * pll_utl.c, & pdc_rqsts.h) have changed use iodc_sversion.
 */

struct swrev {
        u_int   srev:4,         /* software revision number */
                model:20,       /* software model number */
                opt:8;          /* module dependent option */
};

/* IODC Fields */

typedef struct {
    u_int   model:12,
	    rev:4;
} iodc_hversion_type;

typedef struct {
    u_int   io:1,
	    Z:1,
	    sv:1,
	    shift:5;
} iodc_spa_type;

typedef struct {
    u_int   mr:1,
	    wd:1,
	    R:1,
	    type:5;
} iodc_type_type;

typedef struct {
    u_int   rev:4,
	    model:20,
	    opt:8;
} iodc_sversion_type;



#define NUM_SBUS_MODS	   16	/* Num Modules on S700 buses */


/* To deal with fixed address devices' additional addresses */
#define MAX_ADD_ADDR 1

struct fix_addr {
	caddr_t		io_addr;
	u_int		io_pages;
};

/* Native Module Table Entry */

typedef struct native_mod_ENTRY {

	iodc_hversion_type	iodc_hversion;
	iodc_spa_type		iodc_spa;
	iodc_type_type		iodc_type;
	iodc_sversion_type	iodc_sversion;
	u_short			iodc_reserved;
	u_char			iodc_rev;
	u_char			iodc_dep;
	u_short			iodc_check;
	u_short			iodc_length;
	int			fixed;
	struct native_mod_ENTRY	*next;
        struct io_module        *hpa;
	int			user_mod_index;
	union {
	    struct {
		caddr_t			spa;
		int			spa_size;
		int			mem_size;
		u_int			io_status;
		u_int			io_err_info;
		u_int			io_err_resp;
		u_int			io_err_req;
		struct io_module	*chieftain; /* memory interleave */
	    } mem;
	    struct {
		caddr_t			spa;
		int			spa_size;
		int			eim;
		caddr_t			poll_entry;
		u_int			io_status;
		struct fix_addr		other_addrs[MAX_ADD_ADDR];
	    } io, other;
	    struct {
		struct native_mod_ENTRY	*next_bus;
		caddr_t			io_low;
		caddr_t			io_high;
		int			is_lower_port;
		u_int			io_status;
		u_int			io_err_info;
		u_int			io_err_resp;
		u_int			io_err_req;
		struct native_mod_ENTRY	*other_port;
	    } bc;
	    struct {
		struct native_mod_ENTRY	*first_module;
		int			eim;
		u_int			lasi_elr;
		u_int			lasi_icr;
		struct fix_addr		other_addrs[MAX_ADD_ADDR];
	    } ba;
	} type;
} native_mod_entry;

/* Defined for the LAN-DDB. This structure will generate code who's data 
 * alignment will actually match IODC return data (llt)
 */
typedef struct real_IODC_data {
        u_int           hw_model:12;
        u_int           hw_rev:4;
        u_int           spa_io:1;
        u_int           spa_Z:1;
        u_int           spa_sv:1;
        u_int           spa_shift:5;
        u_int           more:1;
        u_int           word:1;
        u_int           resv:1;
        u_int           type:5;
        u_int           sw_rev:4;
        u_int           sw_model:20;
        u_int           sw_opt:8;
        u_char          iodc_rev;
        u_char          iodc_dep;
        u_short         iodc_reserved;
        u_short         iodc_check;
        u_short         iodc_length;
} real_IODC_bytes;

typedef struct IODC_data {
	iodc_hversion_type	iodc_hversion;	/* IODC data fields 	*/
	iodc_spa_type		iodc_spa;
	iodc_type_type		iodc_type;
	iodc_sversion_type	iodc_sversion;
	u_char			iodc_rev;
	u_char			iodc_dep;
	u_short			iodc_reserved;
	u_short			iodc_check;
	u_short			iodc_length;
} IODC_bytes;


/* s700 I/O table */
typedef struct vsc_mod_ENTRY {

	iodc_hversion_type	iodc_hversion;	/* IODC data fields 	*/
	iodc_spa_type		iodc_spa;
	iodc_type_type		iodc_type;
	iodc_sversion_type	iodc_sversion;
	u_char			iodc_rev;
	u_char			iodc_dep;
	u_short			iodc_reserved;
	u_short			iodc_check;
	u_short			iodc_length;

	caddr_t			hpa;   /* avail for mapping regs onto   */
	u_int			more_pgs;/* additional pages            */
	int                     user_mod_index; /* for diagnostics      */

	union {				/* mod-specific data		*/
	    struct {  			/* for SGC I/O modules		*/
		struct isc_table_type *isc_table; 
		struct vsc_mod_ENTRY  *next_ftn;
		int		       ftn_no;
	    } fio;

	    struct {
		/* Creating an array of vsc_mod_entry ptrs for the slots. */
		struct vsc_mod_ENTRY *ba_mod_table[NUM_SBUS_MODS];
	    } ba;
	} type;

} vsc_mod_entry;

extern vsc_mod_entry *vsc_mod_table[];

/*
 * structures/unions that make low-level kernel debugging easier
 */

typedef union _psw {
	unsigned int word;
	struct {
		unsigned int Y : 1;
		unsigned int Z : 1;
		unsigned int RV1 : 3;
		unsigned int E : 1;
		unsigned int S : 1;
		unsigned int T : 1;
		unsigned int H : 1;
		unsigned int L : 1;
		unsigned int N : 1;
		unsigned int X : 1;
		unsigned int B : 1;
		unsigned int C : 1;
		unsigned int V : 1;
		unsigned int M : 1;
		unsigned int CB : 8;
		unsigned int RV2 : 1;
		unsigned int G : 1;
		unsigned int F : 1;
		unsigned int R : 1;
		unsigned int Q : 1;
		unsigned int P : 1;
		unsigned int D : 1;
		unsigned int I : 1;
	} field;
} psw_t;


#endif  /* not LOCORE */

#endif /* not _MACHINE_CPU_INCLUDED */
