From 12623687c4bd5eeb5b3ca8f23cf3b646357e2bc3 Mon Sep 17 00:00:00 2001 From: Marcelo Tosatti Date: Tue, 20 Aug 2013 21:42:24 +0200 Subject: [PATCH 25/28] kvm: i386: fix LAPIC TSC deadline timer save/restore RH-Author: Marcelo Tosatti Message-id: <20130820214224.GA9334@amt.cnet> Patchwork-id: 53623 O-Subject: [RHEL7 qemu-kvm PATCH] kvm: i386: fix LAPIC TSC deadline timer save/restore Bugzilla: 972433 RH-Acked-by: Paolo Bonzini RH-Acked-by: Eduardo Habkost RH-Acked-by: Gleb Natapov BZ: 972433 commit 7477cd3897082d2650d520a4e9aa7f8affa3dd5d of uq/master branch of qemu-kvm.git repository The configuration of the timer represented by MSR_IA32_TSCDEADLINE depends on: - APIC LVT Timer register. - TSC value. Change the order to respect the dependency. Signed-off-by: Marcelo Tosatti Signed-off-by: Paolo Bonzini Signed-off-by: Miroslav Rezanina --- target-i386/kvm.c | 29 ++++++++++++++++++++++++++--- 1 files changed, 26 insertions(+), 3 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 8da6a0d..c5a9416 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1042,6 +1042,26 @@ static void kvm_msr_entry_set(struct kvm_msr_entry *entry, entry->data = value; } +static int kvm_put_tscdeadline_msr(X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + struct { + struct kvm_msrs info; + struct kvm_msr_entry entries[1]; + } msr_data; + struct kvm_msr_entry *msrs = msr_data.entries; + + if (!has_msr_tsc_deadline) { + return 0; + } + + kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline); + + msr_data.info.nmsrs = 1; + + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); +} + static int kvm_put_msrs(X86CPU *cpu, int level) { CPUX86State *env = &cpu->env; @@ -1065,9 +1085,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_tsc_adjust) { kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust); } - if (has_msr_tsc_deadline) { - kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); - } if (has_msr_misc_enable) { kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, env->msr_ia32_misc_enable); @@ -1705,6 +1722,12 @@ int kvm_arch_put_registers(CPUState *cpu, int level) return ret; } } + + ret = kvm_put_tscdeadline_msr(x86_cpu); + if (ret < 0) { + return ret; + } + ret = kvm_put_vcpu_events(x86_cpu, level); if (ret < 0) { return ret; -- 1.7.1