From 4cefed8b739105669126682df52b28e33ded235a Mon Sep 17 00:00:00 2001 Message-Id: <4cefed8b739105669126682df52b28e33ded235a.1349175436.git.minovotn@redhat.com> In-Reply-To: <94968b7fa9b14e71f004474d7ce77e189e6a2bf3.1349175436.git.minovotn@redhat.com> References: <94968b7fa9b14e71f004474d7ce77e189e6a2bf3.1349175436.git.minovotn@redhat.com> From: Eduardo Habkost Date: Fri, 28 Sep 2012 16:50:21 +0200 Subject: [PATCH 16/34] enable TSC-deadline on SandyBridge CPU model (on rhel6.4.0 only) (v2) RH-Author: Eduardo Habkost Message-id: <1348851023-31907-17-git-send-email-ehabkost@redhat.com> Patchwork-id: 42506 O-Subject: [RHEL6 qemu-kvm PATCH 16/18] enable TSC-deadline on SandyBridge CPU model (on rhel6.4.0 only) (v2) Bugzilla: 767944 RH-Acked-by: Alex Williamson RH-Acked-by: Paolo Bonzini RH-Acked-by: Igor Mammedov Bugzilla: 767944 Upstream status: not applicable (Upstream SandyBridge already has TSC-deadline enabled) This enables TSC-deadline on the SandyBridge CPU model, and adds a new compatibility variable to disable the bit on rhel6.3.0 and older. Signed-off-by: Eduardo Habkost Conflicts: hw/pc.c Changes v1 -> v2: - Add disable_tsc_deadline() call to pc_rhel630_compat() only, as pc_rhel620_compat() now is kept calling pc_rhel630_compat() Signed-off-by: Eduardo Habkost --- hw/pc.c | 1 + hw/pc.h | 1 + target-i386/cpuid.c | 13 ++++++++++++- 3 files changed, 14 insertions(+), 1 deletion(-) Signed-off-by: Michal Novotny --- hw/pc.c | 1 + hw/pc.h | 1 + target-i386/cpuid.c | 13 ++++++++++++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/pc.c b/hw/pc.c index 82663c9..ed83d72 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -1633,6 +1633,7 @@ static void pc_rhel630_compat(void) { disable_kvm_pv_eoi(); set_pmu_passthrough(true); + disable_tsc_deadline(); } static void pc_rhel620_compat(void) diff --git a/hw/pc.h b/hw/pc.h index 051dab8..73bbf10 100644 --- a/hw/pc.h +++ b/hw/pc.h @@ -181,5 +181,6 @@ int cpu_is_bsp(CPUState *env); /* machine-type CPU compatibility functions: */ void set_pmu_passthrough(bool enable); void disable_kvm_pv_eoi(void); +void disable_tsc_deadline(void); #endif diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index 1b914c4..ad6300e 100644 --- a/target-i386/cpuid.c +++ b/target-i386/cpuid.c @@ -90,6 +90,7 @@ int enforce_cpuid = 0; /* machine-type compatibility settings: */ static bool kvm_pv_eoi_disabled; static bool pmu_passthrough_enabled; +static bool tsc_deadline_disabled; static void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); @@ -573,7 +574,8 @@ static x86_def_t builtin_x86_defs[] = { .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | - CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER, .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, .ext3_features = CPUID_EXT3_LAHF_LM, .xlevel = 0x8000000A, @@ -852,6 +854,9 @@ static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) if (pmu_passthrough_enabled) { x86_cpu_def->pmu_passthrough = true; } + if (tsc_deadline_disabled) { + x86_cpu_def->ext_features &= ~CPUID_EXT_TSC_DEADLINE_TIMER; + } /* end of machine-type compatibility bits */ @@ -1406,6 +1411,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, */ void set_pmu_passthrough(bool enable); void disable_kvm_pv_eoi(void); +void disable_tsc_deadline(void); void set_pmu_passthrough(bool enable) { @@ -1416,3 +1422,8 @@ void disable_kvm_pv_eoi(void) { kvm_pv_eoi_disabled = true; } + +void disable_tsc_deadline(void) +{ + tsc_deadline_disabled = true; +} -- 1.7.11.4