Welcome to ftp.nluug.nl Current directory: /os/Linux/distr/salix/sbo/15.0/academic/DRAMsim3/ |
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Contents of README:DRAMsim3 models the timing paramaters and memory controller behavior for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5, GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected oriented model that includes a parameterized DRAM bank model, DRAM controllers, command queues and system-level interfaces to interact with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed to be accurate, portable and parallel. |
Name Last modified Size
Parent Directory - DRAMsim3.SlackBuild 05-Nov-2022 15:20 3.5K DRAMsim3.info 05-Nov-2022 15:20 317 README 20-Oct-2022 18:35 451 slack-desc 20-Oct-2022 18:35 1.1K
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