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Contents of README:= OVERVIEW = The Synacor Challenge is a fun programming exercise with a number of puzzles built into it. You can find more details about it here: https://challenge.synacor.com/ The first puzzle is writing an interpreter for their custom ISA. This is a simulator for that custom CPU. The CPU is quite basic: it's 16-bit with only 8 registers and a limited set of instructions. This means the port will never grow new features. See README.arch-spec for more details. Implementing it here ends up being quite useful: it acts as a simple constrained "real world" example for people who want to implement a new simulator for their own architecture. We demonstrate all the basic fundamentals (registers, memory, branches, and tracing) that all ports should have. |
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Parent Directory - CVS/ 13-Aug-2024 05:02 - ChangeLog-2021 12-Aug-2024 22:02 3.1K Makefile.in 12-Aug-2024 22:02 954 README 12-Aug-2024 22:02 766 README.arch-spec 12-Aug-2024 22:02 2.9K interp.c 12-Aug-2024 22:02 5.0K local.mk 12-Aug-2024 22:02 897 sim-main.c 12-Aug-2024 22:02 17K sim-main.h 12-Aug-2024 22:02 1.2K
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